L14 Notes-Loop
L14 Notes-Loop
This is a lecture based on our long-lasting (and on-going) research on nanomagnetic logic
(NML) devices. You might be astonished of the simple way I introduce the research in
the beginning: this talk is based on a presentation I gave at Deutsches Museum for
TEDxTUM in 2018. The idea was to keep it generally comprehensible.
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Thanks to …
Lehrstuhl für Technische Elektronik, TUM, Germany.
S. Breitkreutz-v. Gamm, I. Eichwald, J. Kiermaier, F. Riente, G. Turvani, G. Žiemys
and D. Schmitt-Landsiedel
Center for Nano Science and Technology, University of Notre Dame, Indiana, USA.
M. Niemier, G. Bernstein and W. Porod
Magnets are known for early memory solutions. Magnetic core Memory? Ever heard of?
It was the really in the beginning of the computing era. Tape? It was there and it is still
there. The bubble memory died out, when electronic solutions took over. But it was a
product at the time. And magnets for computation?
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Nanomagnets Today
Recording Media in HDDs & Tape Magnetic RAM Magnetic Sensors
Magnetic easy axis
Source
Source
RL
RKKY
PL
NAF
Source 100nm Exchange Bias Source
Nanomagnets: Magnets with at least one spatial dimension in the nanometer range
▪ Field-Coupled logic
Nevertheless, it is the memory solutions in which magnets are used. They are also widely
used in sensor technology. For computations? We have taken two paths: field-coupled
logic and spin waves for data processing. This talk, however, is about the former.
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pNML 1.0
The well known ERD roadmap. Choose whatever entry you want, but be cautious when
you overlap with CMOS – it might be challenging!
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[Link]
switches
[Link]
times per second
This are just rough numbers, but in principle this is a problem, that even though tran-
sistors are low power switching elements, the mere amount of them + high clocking
frequencies on chip, dissipate a lot of power.
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The shortcomings are grumbling at high level. But indeed, dynamic power losses exist.
Furthermore, before having high-k dielectric gates and FinFET technology, leakage cur-
rent was responsible for up to 50% of the overall losses and data loss, is especially in
devices without battery a big issue. But imagine, that also computation could be made
more efficient, having a nonvolatile memory close to the arithmetic logic unit (ALU), i.e.
at the computing cores of a processor.
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No currents!
Keep the
switch!
No data loss! 9
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With the start of the new century, there was plenty of research on patterned ferromag-
netic islands, domain wall conductors and the magnetostatic interaction between them.
Famous groups published new results on nano-scaled single domain behavior and device
ideas for computation and memory.
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First, Cowburn/Welland showed circular single domain magnets, that will align in a
ferromagnetic way and form something that looks like a head-to-head domain-wall that
could be moved back and forth — it was called Soliton in the Science Paper of 2000.
Second, there was the domain-wall logic of Cowburn/Allwood — a NOT gate is shown
here. It were our partners, i.e. G. Csaba who proposed a computing scheme with field
coupled magnets that are aligned in a anti-ferromagnetically coupled manner: neighbor-
ing ellipsoidal magnets will align an an up-down-up way. I’ve presented a 1-bit-full-adder
in this technology in previous lectures.
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Here is the more technical approach we are using for our magnets. During fabrication,
we 1) shoot Ga+ ions into a multilayer stack of magnetic material with PMA, PMA is
lowered at this site. Note, this process is done once during fabrication, we can somehow
change the properties of a magnet to our will. Now, when we 2) apply a magnetic field,
we can nucleate a reversed domain and 3) move this domain through the magnet and
finally 4) the full magnetization is reversed. Nucleate, propagate → switched. That is
the basic concept of field-driven magnetization reversal.
Tickle with Ga
Magnetic Field
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Reversing magnetization and hence, switching from 1 to 0 and back is something, that
reminds us on memory. But binary functions and Boolean algebra needs interaction,
needs inputs and outputs. The principle is given here. We have seen, that magnets
interact, when they are close by. But due to symmetry reasons, having two equal magnets
side by side as shown on the left, it is not clear at all, which one is input (speaker) and
which one is output (listener). The Ga+ radiation does the trick here: The left magnet
produces magnetostatic fields, and the right magnet is sensitive to these stray-field,
because it has this area of low anisotropy (we call it artificial nucleation center, (ANC)).
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Of course, we have to fabricate the magnetic films. Over years we did it with a manual
sputtering tool. Multilayers of magnets are fabricated with typical recipes as given at
the bottom. N bilayers of Co/Pt stacked between a seed (for crystalline growth) and
capping (environmental protection) of Pt. For N = 5 , 10 and 40, the hysteresis loops are
measured and typical domain-patterns are given, measured by MFM. The higher N , the
smaller the domain-sizes, as the demagnetization fields increase a lot and domain walls
are energetically favorable.
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Becherer et al., IEEE TNANO, 2008. > 500 magnets ordered perfectly 17
This was an experiment, that probably triggered my academic career most. Having fabri-
cated a 40 ML film, I wrote a square pattern of thin (20 nm) thin lines with our focused ion
beam tool. Voila, having the right dose, we get a beautiful ordered checkerboard pattern
of magnetic poles. Even dislocation interfaces in magnetization (frustration) happens,
because ordering starts at different sites in the patterned area. This experiment resulted
in my first publication.
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Images by courtesy of
TEM for atomic resolution Notre Dame Integrated Imaging Facility.
Later, we wanted to understand in more detail, what happens during FIB irradiation.
Transmission Electronc Microscopy (TEM) is one way to look at the crystallinity of
multilayers and the intermixed multilayer stack after FIB. As mentioned before, those
measurements are costly, but it turned out to be as expected: one looses the distinct
bilayer repetitions and gets an intermixed alloy of Co/Pt having little to no PMA left.
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Even though, checkerboard patterns triggered the research on FIB irradiated films, it
turned out, that irradiating the edges of magnets, is not of much use for us. We have
to irradiate islands in a controlled way. We are able to lower the as-grown switching
field (coercivity) of magnetic island by introducing larger FIB damage as the as-grown
defects. With sufficient ion dose we reduce coercivity from 400 mT to 100 mT. We also
found, that varying the size of the irradiation area matters: The larger the area, the
smaller the dose needed — a very intuitive result.
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Fabrication Technology
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Now, we have all ingredients for a fabrication platform. The layer composition changed
over time, 4 bi-layer stacks with increased Co thickness were optimum and etching islands
with physical Ar+ ion, followed by irradiation with the FIB close to one edge of the
magnet is the techniques we applied over many many years. However, we will see later,
especially the placement of the nucleation center and lateral resolution is key to fabricate
reliable structures. Something, we are kind of stuck right now with the grown old tools
we are applying.
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This slide summarizes the field-coupling and nucleation of domain-walls of two coupled
magnetic islands: one of tow magnets is FIB irradiated close to the neighbor magnet.
Anti-parallel orientation of the magnetic poles is the lowest energy state. In order to have
the FIB irradiated magnet in opposite alignment, we apply a magnetic field and due to
FIB, coercivity is smaller — as the magnetic field of the neighbor helps in switching. In
other words, the ANC is the summing point of all coupling fields and coercivity of the
ANC magnet is reduced (increased) by the amount of coupling fields.
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Showing, that magnetic ordering (up/down/up etc.) has a direction, we performed this
experiment. Three magnets in a row, the center magnet (T for transfer) is irradiated on
the left and such it should be more sensitive on the coupling field of D1 then to the fields
of D2. This is exactly what we see in the measurement graph: Polarization of D2 does
have almost no influence on T, and D1 is more or less fully controlling the state of T.
Perpendicular Nanomagnetic Logic (pNML) is a form of Nanomagnetic Logic (NML) where information is processed
using magnetic nanodots with perpendicular magnetization instead of conventional CMOS transistors. In pNML, logic states (0 and 1)
are represented by the up or down magnetization of nanomagnets, which interact through dipolar coupling.
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One snapshot of lowest energy configuration. One magnet pair is in parallel configu-
ration, and in the next clocking cycle, the frustration will move one magnet further to
right. It is the frustrated magnetization configuration that carries the binary information
and a lateral homogeneous magnetic clocking field (we used cm-large electromagnets) is
sufficient to direct signals on chip. By the way, having two magnets coupled, we already
can talk about an inverter, as magnetization is reversed at each magnet.
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 0
In order to do Boolean algebra, we need a functionally complete set of gates: the natural
gate in field-coupled devices is the so-called Majority Gate. Three (five) inputs, one
output. Depending on the majority of inputs, the output will align in opposite manner
—- the truth-table is given on the right. Looking closely, the experts see, that we do
have a NAND gate for the first input being 0, and a NOR gate for the first input being
1 — hence, we can have NAND or NOR technology by fixing one input (or changing it
during runtime).
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One gate is not sufficient for computation: putting two majority gates together (including
magnetic domain-wall conduits from the same material as the gates), one gate with 3
inputs, one gate with 5 inputs, we built something more complex.
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This is a 1-bit full-adder in a very compact version. As gates and connections are the
same material (Co/Pt islands), five magnets are sufficient to generate 3 needed inputs
and 2 outputs.
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Full-adder circuit
A B Cin Cout Su
m
0 0 0 1 1
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 0 0
And that is the result. To my knowledge the world record in compactness of a full-adder
(even though the outputs are still inverted).
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This as how the chips look like: we put them on chip-carriers, we apply magnetic fields,
we look at them with tailored KERR microscopes and play with tiny coils and on-chip
coils for micro- to nanosecond magnetic field-pulses.
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Many instruments in our lab are home-made. Playground for Master’s theses in pro-
gramming, automation, measurement technology and optimization. Hands-on welcome.
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5 magnets 28 transistors
No leakage Leakage currents
No data loss Data loss when not powered 31
This comparison is unfair in a sense, that MOSFET full-adder circuits are very reliable
and commercially available in processors. Our demonstrator is even lacking electrical in-
and output. But the beauty is in the size and number of magnets ... and scaling would
make it even better in terms of coupling strength and hence, reliable operation.
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The DW-gate was not discussed in the lecture. But in principle you can store information
depending on the state of the gates G1 and G2 .
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If you want to compete with stat-of-the-art microelectronic devices, you have to compete
with 3D integrated devices.
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As soon as you plot layouts of 2D pNML circuits, you figure out, that there is no easy
way of crossing magnetic signals. In electronic circuits you would use complex wiring
with vias in many layers of metallization, even your printed circuit boards might contain
up to 16 layers of interconnects. There is need for it in NML too.
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Browsing publications of the 70s, we recognized, that magnetic memories and circuits
were heavily researched. At that time, microelectronics was in its beginnings but soon
after it outdated magnetic technologies for on-chip memory and computation. However,
at that time, researchers played with magnetic domain walls and already had 3D devices
working. Not all was sub-micrometer in size, but already pretty sophisticated.
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We had he following thougths. Magnetic stray-fields not only interact with magnets in
one plane, they are acting on neighboring volume. Why not putting a second magnet
in a second layer above the first layer of magnets, and placing the ANC at the point,
where it would see sufficient field to be influenced? The field direction above a magnetic
points in the same direction: the magnet above will align in the same polarization as the
magnet below → ferromagnetic coupling over a insulating barrier.
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These thoughts triggered our vision of a 3D pNML co-processing unit. Use a CMOS
microprocessor to give electrical in- and output for a pNML chip, that is fabricated by
3D arranged layouts of magnetic gates and memory devices. The pNML chip will by
clocked by magnetic fields of an on-chip coil. To keep currents for on-chip magnetic field
low, a soft-magnetic yoke shall be used.
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Stacking
of
magnetic
islands
in
3D
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In a) yous see the cross-sectional sketch of the problem: two stacked magnetic layers,
including a Ti-hard mask for fabrication (red) and a blue separation layer (HSQ). In the
left simulation, you can see, that Ga ions are still penetrating the lower magnetic stack,
because the Ti hardmask was 3 nm thick only. Increasing this hardmask to 8 nm, the
penetration depth is significantly reduced and the lower magnetic layer is safe.
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This engineering task resulted in the first 3D pNML gate. The SEM shows Input I3
in a lower layer, I2 , I3 and O are in the upper layer (the electrons during measurement
penetrate the both thin layers and give sufficient contrast). The magnetic measurement
is shown on the right of the SEM image.
The 3D NAND/NOR in all beaty, it cost 1 year of building it!
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The press release and media response of EETimes — replacing transistors was simply
nothing we have ever claimed, but they were looking for a highlight.
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Finally, we were able to present a device family of 3D NML with crossings, vias ...
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4545
2 µm
2 µm
4646
At least 3D stacking of NML is very dense and as we have only magnetic layers and
dielectric and no need for high-temperature Silicon CMOS processing, we could do it in
the back-end-of-line of CMOS.
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Riente et al., AIP Advances 2017. 1½ metal layer BEOL by courtesy of INFINEON. 47
To show, that one has the capability to process it in the BEOL, we got an Infineon dummy
wafer with tungsten metallization, processed pNML structures and they — believe it or
not — (partly) worked. Hence, we published the results.
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However, there is a major part of pNML still missing. The on-chip clocking circuitry.
Meander like wires on a chip, sandwiched between two soft-magnetic layers for field-
guidance. Even more difficult to fabricate, as we would be not able to access the pNML
magnets with optical Kerr-microscopes or MFM.
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Power loss of pNML 45X smaller at only 30% reduced data throughput
compared to Si-CMOS*(Pden = 160 Wcm−2, Source: ITRS ERD, 2015).
At least simulations show, that it could work. Rule of thumb calculations predict, that
we could be competitive with CMOS when it comes to low power operation, parallel or
pipelined computation ... but this is another story to tell.
Summary 3D pNML
In case, that it will never be a product: it was quite a challenge, lots of lessons to be
learned and not least quite some fun to develop this vision.
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And who knows, we continue with magnetic device research and maybe you aim to be
part in it.
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And maybe in future, magnets are part of your smartphones. It is not impossible.
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[Link]
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Q 11: Slide 37
One advantage of pNML is the capability of 3D integration. However, how would you con-
nect different 2D layers of pNML devices for signal flow? Do you think one could achieve
inter-chip connections (connections between different computing chips) with magnetic
field-coupled signals?
Q 12:
Why are on-chip inductors with incorporated ferromagnets similar to the on-chip field
clock for pNML circuits?
Q 13:
CMOS circuits have to be provided with a synchronization clock. pNML circuits instead
need a clock for power supply. Why do pNML circuits need a so-called clocking zone
formed by a meander-like copper wire and soft-magnetic cladding (yoke)?
Q 14:
Often, people benchmark the speed of a computing system by clocking-frequency. Could
you provide a better benchmark (figure-of-merit) for digital computation including power,
logic function and area.
Q 15:
In beyond CMOS device (and system) research, researchers proposed logic-in-memory
concepts. However, it would mean, that for logic operations, one had to switch the
non-volatile memory-cells with high repetition frequencies. Which implications does this
have on memory endurance? Why do we not expect endurance issues for pNML from
magnetic multilayers?
Q13.
- It generates a controlled magnetic field for switching nanomagnets (instead of using voltage like CMOS).
- The meander wire structure ensures uniform and efficient field application.
- The soft-magnetic yoke enhances, directs, and localizes the field, making the system more energy-efficient and precise.
- It enables controlled and synchronized logic operations, just like a clock in CMOS, but using magnetic fields instead of
electronic pulses.