Module 3

Design of Combinational Logic Circuits

➢ Design Procedure
➢ Half Adder, Full Adder
➢ Half Subtractor, Full Subtractor
➢ Multiplexers, Demultiplexers
➢ Decoders, Encoders
➢ Parity generator and checker
➢ Applications of Decoder, Multiplexer and De-multiplexer.
➢ Modelling of Combinational logic circuits using Verilog HDL.

1
 COMBINATIONAL CIRCUITS

Logic gates are connected together to produce a specified output for certain
specified combination of I/P variables, without storage device is called
combinational logic circuit.
Example: Adder, Subtractor, Multiplexer, Demultiplexer, Decoder, Encoder

Block Diagram

2
 Design procedure for Combinational circuit Design

The design procedure of the combinational circuit involves the following

steps
1. The problem definition
2. The determination of number of available input variables and required
output variables and draw the block diagram.
3. Assigning letter symbols (A, B, …,Y) to input and output variables
4. The derivation of truth table indicating the relationship, between input
and output variables
5. Obtain simplified Boolean expression for each O / P through K map.
6.3 Obtain the logic diagram
AND Gate design Ex-OR Gate design OR Gate design
A B Y A B Y
A B Y
0 0 0 0 0 0
0 0 0
0 1 1 0 1 1
0 1 0
1 0 1 1 0 1
1 0 0
1 1 0 1 1 1
1 1 1
𝑩 𝑩 𝑩 𝑩 𝑩 𝑩 𝑩 𝑩
𝑨 𝑨 𝑨 𝑩
𝑨 0 𝑨 0 1 𝑨
0 𝟎 𝟏 0 1
𝟎 𝟏 𝟎 𝟏
𝑨 0 1 𝑨 1 0 𝑨 1
𝟐 𝟑 𝟐 𝟑 1 𝟐 𝟑

Y = 𝐴𝐵 Y = 𝐴𝐵 + 𝐴𝐵 Y=𝐴+𝐵

4
5
Example:
Design a combinational logic circuit with three I/p parameters, i.e Temperature, Humidity
and Time of the day. Depends upon the above variables Air conditioner going to switch
on as per user requirements.
Decimal Temperature Humidity Time of the Day Air
Number >35o C < 30 Between 8 pm to Conditioner
5 am. Output
(A)
(B) (C) (Y)
0 0 0 0 0
1 0 0 1 0
2 0 1 0 0
3 0 1 1 1
4 1 0 0 0
5 1 0 1 1
6 1 1 0 1
7 1 1 1 1

Y = ∑ m( 3,5,6,7)

6
 𝐵C 𝐵𝐶 𝐵𝐶 𝐵𝐶 𝐵𝐶
𝐴
𝐴 0 𝟎 0 𝟏 1 𝟑
0 𝟐
𝐴 0 𝟒 1 𝟓 1 1
𝟕 𝟔
Y =AC +BC + AB

Logic Diagram

7
➢ EXAMPLE-2: Design a combinational logic circuit used to instruct a Floor
cleaning robot to recharge (R=1) itself only when a specific set of following
conditions is met.
(i). When its battery is low (B = 1) or
(ii). When the working time is over (T=1) or
(iii). When vacuuming is complete (V=1), and when waxing is complete
(W=1).

a) Construct the truth table

b) Find the simplified expression using K-Map
c) Obtain the logic circuit using AND-OR gate
d) Convert the obtained circuit to its NAND equivalent gates.

8
STEP1: The problem statement - output R=1 (to recharge robot battery) if low
battery (B=1) or worktime is over (T=1) or vacuuming (V=1)and waxing (W=1) is
done

STEP2: Identify the input and output variables

➢ No. of inputs required: 4
➢ No. of output required: 1

STEP3: The input & outputs are assign with letter symbols
➢ Letter symbol for inputs: B, T, V, W
➢ Letter symbol for output: R

STEP4: Construction of a truth table for the given logic

STEP5: obtain the simplified expression for output variable using K-map

STEP6: Logic diagram is realized from the simplified expression using logic gates

9
 (a) Truth Table

10
 (b) K-Map (c) Logic diagram

Y = B + T + VW

(d) NAND Implementation

11
ADDDER CIRCUIT DESIGN

An adder is a digital logic circuit in electronics that implements addition of

numbers. In many computers and other types of processors, adders are used
to calculate addresses, similar operations and table indices in the ALU and
also in other parts of the processors.

TYPES :
1. Half Adder Design
[Link] Adder Design

1
0 0 1 1 1
+ 0 + 1 + 0 + 1 + 1
0 1 1 1 0 1 1
12
HALF ADDER DESIGN
•Half Adder is a combinational logic circuit.
•It is used for the purpose of adding two single bit numbers.
•It contains 2 inputs and 2 outputs (sum and carry
Input bits : Augend and addend bits
Output bits : Sum and Carry Bits

Block diagram:

13
 Truth Table:
Input Output
A B Carry Sum
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Design: K map Simplification For Sum = ∑ m (1,2)
For Carry = ∑ m(3) 𝐵
𝐵 𝐵
𝐵 𝐴
𝐵 𝐵
𝐴 𝐴 0 1
𝐴 0 0 𝟎 𝟏
𝟎 𝟏 𝐴
𝐴 1 0
1 𝟐 𝟑
0
𝟐 𝟑
Sum = 𝐴𝐵 +𝐴𝐵
14
Carry =𝑨𝑩 = A⊕B
 Logic Diagram:

Limitation:

The Half Adders is that there is no scope for them to add the carry bit from
previous bit. This is a major limitation of half adders.

15
FULL ADDER DESIGN
Full adder is a combinational circuits that form the arithmetic sum of 3 bits. It
consists of three inputs and two outputs.

Block diagram:

16
Truth Table:

Input Output
A B C Carry Sum
0 0 0 0 0
0 0 1 0 1 Carry = ∑ m (3,5,6,7)
0 1 0 0 1
0 1 1 1 0 Sum = ∑ m (1,2,4,7)
1 0 0 0 1
1 0 1
1 0
1 1 0
1 0
1 1 1
1 1

17
 Carry = ∑ m (3,5,6,7)

𝐵C 𝐵𝐶 𝐵𝐶 𝐵𝐶 𝐵𝐶
𝐴
𝐴 0 𝟎 0 𝟏 1 𝟑
0 𝟐
𝐴 0 𝟒 1 𝟓 1 1
𝟕 𝟔

Carry =𝑨𝑪 + 𝑩𝑪 + 𝑨𝑩

= 𝐀𝐁 + 𝐁𝐂 + 𝐀𝐂

= 𝐀𝐁 + 𝐁𝐂 𝐀 + 𝐀 + 𝐀𝐂 ( 𝐁 + 𝐁 )

= 𝐀𝐁 + 𝐀𝐁𝐂 + 𝐀𝐁𝐂 + 𝐀𝐁𝐂 + 𝐀𝐁 𝐂

= 𝐀𝐁 𝟏 + 𝐂 + 𝐂 (𝐀𝐁 + 𝐀𝐁 )
18 Carry = 𝑨𝐁 + 𝐂 (𝑨⊕ B)
 Sum = ∑ m (1,2,4,7)

𝐵C 𝐵𝐶 𝐵𝐶 𝐵𝐶 𝐵𝐶
𝐴 0 𝟎 1 𝟏 0 𝟑
1 𝟐
𝐴 1 𝟒 0 𝟓 1 0
𝟕 𝟔

Sum = 𝐀 𝐁 𝐂 + 𝐀𝐁 𝐂 + 𝐀 𝐁 𝐂 + ABC

= 𝐀𝐁 𝐂 + 𝐀 𝐁 𝐂 + 𝐀 𝐁 𝐂 +ABC

= 𝐂 (𝐀𝐁 + 𝐀 𝐁 )+ 𝐂 (𝐀 𝐁 +AB)

= 𝐂 (𝑨⊕ B)+ 𝐂 (𝑨⊕ B)

Sum = 𝑨⊕ B ⊕ 𝑪

19
 Logic Diagram:

Sum = 𝑨⊕ B ⊕ 𝑪 Sum = 𝐀 𝐁 𝐂 + 𝐀𝐁 𝐂 + 𝐀 𝐁 𝐂 + ABC

Carry = 𝑨𝐁 + 𝐂 (𝑨⊕ B) Carry =𝑨𝑪 + 𝑩𝑪 + 𝑨𝑩

20
SUBTRACTOR CIRCUIT DESIGN

The Binary Subtractor is another type of combinational arithmetic circuit

that produces an output which is the subtraction of two binary numbers.

TYPES :
1. Half Subtractor Design
[Link] Subtractor Design

0 1 1 1 0

-0 - 0 - 1 - 1
0 1 0 1

21
 HALF SUBTRACTOR DESIGN
•Half subtractor is a combinational logic circuit.
•It is used for the purpose of subtracting two single bit numbers.
•It contains 2 inputs and 2 outputs (difference and borrow)
Input bits : minuend, subtrahend and borrow
Output bits : difference and borrow

Block diagram:

22
 Truth Table:
Input Output
A B borrow Diff
0 0
0 0
0 1
1 1
1 0
0 1
1 1
0 0
Design: K map Simplification For Diff = ∑ m (1,2)
For borrow = ∑ m(1) 𝐵
𝐵 𝐵
𝐵 𝐴
𝐵 𝐵
𝐴 𝐴 0 1
𝐴 0 1 𝟎 𝟏
𝟎 𝟏 𝐴
𝐴 1 0
0 𝟐 𝟑
0
𝟐 𝟑
Diff = 𝑨𝑩 +𝑨𝑩
23
Borrow = 𝐴𝐵 = A⊕B
 Logic Diagram:
Carry = 𝐴𝐵
Diff = A ⊕ B

Limitation:
Half subtractors do not take into account “Borrow-in” from the previous
circuit. This is a major drawback of half subtractors. This is because real time
scenarios involve subtracting the multiple number of bits which can not be
accomplished using half subtractors.
24
FULL SUBTRACTOR DESIGN
Full subtractor is a combinational circuits that subtracts 3 bit produces their
difference and borrow is called Full subtractor.

Block diagram:

25
Truth Table:

Input Output
A B C Borrow Difference
0 0 0 0 0
0 0 1 1 1 Borrow = ∑ m (1,2,3,7)
0 1 0 1 1
0 1 1 1 0 Sum = ∑ m (1,2,4,7)
1 0 0 0 1
1 0 1
0 0
1 1 0
0 0
1 1 1
1 1

26
 Borrow = ∑ m (1,2,3,7)

𝐵C 𝐵𝐶 𝐵𝐶 𝐵𝐶 𝐵𝐶
𝐴
𝐴 0 𝟎 1 𝟏 1 𝟑
1 𝟐
𝐴 0 𝟒 0 𝟓 1 0
𝟕 𝟔

Borrow =𝐀𝐂 + 𝐀𝐁 + 𝑩𝑪

Get the borrow by other method (From truth table − by boolean method)
=𝐀 𝐁 𝐂+𝐀𝐁 𝑪+𝐀𝐁𝐂 + A𝐁𝐂
= 𝐀𝐁 𝑪+𝐀𝐁𝐂 +𝐀 𝐁 𝐂+ A𝐁𝐂
= 𝐀𝐁 (𝑪+𝐂 ) + C (𝐀 𝐁 + A𝐁)

Borrow = 𝐀𝐁 + C (𝑨⊕ B )

27
 Difference = ∑ m (1,2,4,7)

𝐵C 𝐵𝐶 𝐵𝐶 𝐵𝐶 𝐵𝐶
𝐴 0 𝟎 1 𝟏 0 𝟑
1 𝟐
𝐴 1 𝟒 0 𝟓 1 0
𝟕 𝟔

Difference = 𝐀 𝐁 𝐂 + 𝐀𝐁 𝐂 + 𝐀 𝐁 𝐂 + ABC

= 𝐀𝐁 𝐂 + 𝐀 𝐁 𝐂 + 𝐀 𝐁 𝐂 +ABC

= 𝐂 (𝐀𝐁 + 𝐀 𝐁 )+ 𝐂 (𝐀 𝐁 +AB)

= 𝐂 (𝑨⊕ B)+ 𝐂 (𝑨⊕ B)

Difference = 𝑨⊕ B ⊕ 𝑪

28
 Logic Diagram:
Difference = 𝑨⊕ B ⊕ 𝑪 Borrow =𝐀𝐂 + 𝐀𝐁 + 𝑩𝑪
Borrow =𝐀𝐁 + C (𝑨⊕ B ) Difference = 𝐀 𝐁 𝐂 + 𝐀𝐁 𝐂 + 𝐀 𝐁 𝐂 + ABC

29
 Multiplexers And Demultiplexers

30
 Typical Application of a MUX

Multiple Sources Selector Single Destination

MP3 Player
Docking Station

D0
Laptop
D1

MUX
Sound Card Y
D2

D3

Surround Sound System

Digital B A Selected Source

Satellite
0 0 MP3
0 1 Laptop
1 0 Satellite
Digital
1 1 Cable TV
Cable TV
 Multiplexer
• It is a combinational logic circuit which is used as switch.
• It has many input lines and single output lines. The connections are
controlled by using selection lines.
• It has 2n input lines and ‘n’ number of selection lines.
eg; 4 input = 22 → 2 selection lines
8 input = 23 → 3 selection lines
16 input = 24 → 4 selection lines
• Multiplexers are also called as MUX (or) Data line selector (or)
Many to one converter.
32
Advantages:
[Link] number of wires
2. Reduces circuit complexity and cost
[Link] of various circuits using MUX

Logic Symbol :

Types:
Multiplexers are classified as
• 2-to-1 Mux (1 select line)
• 4-to-1 Mux (2 select lines)
33
• 8-to-1 Mux (3 select lines)
• 16-to-1 Mux (4 select lines) etc..
 4:1 MULTIPLEXER :
Logic Diagram:

Truth Table : Selection lines Output

S1 S0
0 0 D0
0 1 D1
1 0 D2
34 1 1 D3
Logic Diagram:

35
 8:1 MULTIPLEXER :
Logic Diagram:

36
Truth Table :

37
 Logic Diagram:

38
 MULTIPLEXERS TREE

➢ It is possible to expand the range of input for multiplexer beyond the

available range in the integrated circuits by interconnecting several MUX.

➢ For example two 8:1 and one 2:1 mux can be used together to form a 16:1
mux and two 16:1 and one 2:1mux can be used to realize the 32:1 mux.

➢ Even we can realize 32:1 mux can be realized with a smaller sized mux like
8:1 or 4:1 or 2:1 by properly assigning the selection lines to those MUX.

➢ To implement 8:1 MUX using two 4:1 MUX require three selection lines
(S2,S1,S0).

39
 MULTIPLEXERS TREE

➢ The select inputs S1 and S0 of both MUX provided to the selections lines of
4:1 mux i.e S1, S0.

➢ Whereas the S2 selection input of the second level 2:1 multiplexer is

connected to S3 selection line.

➢ So, for S2 = 0, the upper multiplexer is selected and input lines d0 to d3 are
selected according to the selected inputs and data is transmitted to an output
through the OR gate.

➢ When S2 = 1, the lower multiplexer is activated and input lines d4 to d7 are

selected according to the selected inputs.

40
41
 16:1 MUX using 4 : 1 MUX

42
Example-1

0 1

43
Example-2: Implement the following Boolean function using 8:1 mux, F
(A,B,C)=∑m (1, 3, 5, 6).
Solution:
Variables, n= 3 (A, B, C) ; Select lines= 3 (S2, S1, S0)
Input lines = 23 = 8 (D0, D1, D2, D3, D4, D5, D6, D7)
➢ The three variables A, B, C are applied to selection lines.
➢ Given minterm to be included by connecting to logic-1.

➢ Missing Minterm are not included by connecting to logic-0.

44
Using 8:1 MUX

A
D0 D1 D2 D3 D4 D5 D6 D7 0
𝐴ҧ 0 1 2 3 4 5 6 7
A 8 9 10 11 12 13 14 15
0 A 𝐴ҧ 0 1 1 0 0

45
Example-4: Implement the following Boolean function using 4:1 multiplexer,
F (A, B, C) = ∑m (1, 3, 5, 6).

IMPLEMENTATION TABLE

TRUTH TABLE

MUX IMPLEMENTATION
46
Example-3: Implement the following Boolean function using 8:1 multiplexer.
F (P, Q, R, S) = ∑m (0, 1, 3, 4, 8, 9, 15)
Solution:
Variables, n= 4 (P, Q, R, S);
Select lines= n-1 = 3 (S2, S1, S0)
2n-1 to MUX i.e., 23 to 1 = 8 to 1 MUX
Input lines= 2n-1 = 23 = 8 (D0, D1, D2, D3, D4, D5, D6, D7)

IMPLEMENTATION TABLE

47 MUX IMPLEMENTATION
48
49
50
51
52
53
Applications of Multiplexer:
Multiplexer are used in various fields where multiple data need to be transmitted using
a single line. Following are some of the applications of multiplexers –

[Link] system –Multiplexer allow the process of transmitting different

type of data such as audio, video at the same time using a single transmission line.

[Link] network – In telephone network, multiple audio signals are integrated

on a single line for transmission with the help of multiplexers. In this way, multiple
audio signals can be isolated and eventually, the desire audio signals reach the intended
recipients.

[Link] memory – Multiplexers are used to implement huge amount of

memory into the computer, at the same time reduces the number of copper lines
required to connect the memory to other parts of the computer circuit.

54
 DEMULTIPLEXER

55
 Typical Application of a DEMUX

Single Source Selector Multiple Destinations

B/W Laser
Printer

Fax
Machine

D0

DEMUX
X D1

D2 Color Inkjet
Printer
D3

B A Selected Destination
0 0 B/W Laser Printer Pen
0 1 Fax Machine Plotter

1 0 Color Inkjet Printer

1 1 Pen Plotter
 DEMULTIPLEXER
• The word Demultiplexer means one into many.

• A Demultiplexer is a logic circuit that receives information on a single input and

transmits the same information over one of several (2n) output lines.

• The selection of a specific output line is controlled by the values of n selected

lines.

57
Logic Symbol :

Types:
▪ 1-to-2 (1 select line)
▪ 1-to-4 (2 select lines)
▪ 1-to-8 (3 select lines)
▪ 1-to-16 (4 select lines) etc..

58
 1 : 4 Demultiplexer
Logic Diagram:

Truth Table :
Data I/P Select Input Outpus
D S1 S0 Y3 Y2 Y1 Y0
D 0 0 0 0 0 D
D 0 1 0 0 D 0
D 1 0 0 D 0 0
D 1 1 D 0 0 0
59
 Logic Diagram:

60
 1 : 8 Demultiplexer
Logic Diagram:

Truth Table :

61
 Logic Diagram:

62
Example-1: Implement the following Boolean function using 1:8 Demux.
F (A, B, C) = ∑m (1, 3, 5, 6).

Inputs Outputs
A B C Y
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0

LOGIC DIAGRAM
TRUTH TABLE

63
➢ Example-2: Implement full Subtractor using demultiplexer
Inputs Outputs
Difference Borrow
A B Bin
(D) (Bout)
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1 FULL SUBTRACTOR USING 1:8 DEMUX
TRUTH TABLE

64
Implement the Full Adder using Demultiplexer circuit

65
 Implement the Full adder using 1x4 Demultiplexer circuit

66
Implement the Full Subtractor using Demultiplexer circuit

67
68
Parity Generator and Checker
 Error detection and correction
• In digital systems, during data transmission and processing, data gets
distorted.
• This is due to the noises added to it. Such noises change 0s to 1s and 1s
to 0s. Due to this the content of the information is changed.
• So it is necessary to identify and remove these errors.
• One of the most widely used error detection techniques for transmission
of data for sharing information between devices is Parity checking.
 Error detection
• The most common error detection code used is the parity bit.

• The parity bit is an extra bit added to the word containing data in
order to make number of 1s either even or [Link] it is used to detect
errors , during the transmission of binary data .

• The message containing the data bits along with parity bit is transmitted
from transmitter node to receiver node.

• At the receiving end, the number of 1s in the message is counted and if

it doesn’t match with the transmitted one, then it means there is an
error in the data.

Types:
[Link] parity
[Link] Parity
 Even Parity Method Odd Parity Method

Transmitted signal as Parity bit = 0 Parity bit = 1

Even number of ones
Transmitted signal as Parity bit = 1 Parity bit = 0
Odd number of ones

72
Exercise :
A. Assign the proper even parity bit to the following groups
1. 1010 - 01010
2.111000 - 1111000
3.101011 - 0101011
B. An even parity system receives the following code of groups
Determine which groups, if any error are in.
1. 101101 - No error
2. 01011 - Error
3. 101101 - No error
C. Assign the proper odd parity bit to the following groups
1. 1110 - 01110
2.101000 - 1101000
3.0101011 - 1101011
D. An odd parity system receives the following code of groups Determine
which groups, if any error are in.
1. 111001 - error
2. 10001 - Error
3. 110001 - No error
 Even Parity Method Odd Parity Method

Transmitted signal as Parity bit = 0 Parity bit = 1

Even number of ones
Transmitted signal as Parity bit = 1 Parity bit = 0
Odd number of ones

Three Bit Message Even parity bit Odd parity bit

generator generator
A B C Y Y
0 0 0 0 1
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 0
 Design For Even Parity Generator

Three Bit Message Even parity bit

generator
A B C Y
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1

= Ʃ m (1,2,4,7)
75
 K map Simplification
𝐵C 𝐵𝐶 𝐵𝐶 𝐵𝐶 𝐵𝐶 = Ʃ m (1,2,4,7)
𝐴
𝐴 0 𝟏 0 𝟏
𝟎 𝟏 𝟑 𝟐
𝐴 𝟏 0 𝟏 0
𝟒 𝟓 𝟕 𝟔

76
 Design For Even Parity Checker

77
 = Ʃ m (1,2,4,7,8,11,13,14) K map Simplification
𝐶𝐷 𝐶𝐷 𝐶𝐷 𝐶𝐷 𝐶𝐷
𝐴B

𝐴𝐵 𝟎 𝟎 𝟏 𝟏
𝟎 𝟑
𝟏 𝟐

𝐴𝐵 𝟏 𝟒 𝟎 𝟓 𝟏 𝟎
𝟕 𝟔
𝐴𝐵 0 𝟏𝟐 1 𝟏𝟑 0 15 1 𝟏𝟒

𝐴𝐵 1 𝟖 0 𝟗 1 𝟏𝟏 0 𝟏𝟎

78
 Logic Diagram:

79
 •Single-bit errors are detected using parity.
•Two-bit errors can go undetected.
•Parity does not correct errors, only detects them.
•More advanced methods like Hamming Code or CRC are
used to detect and correct errors.

80
 APPLICATIONS

➢ Parity bit generator is used in digital communications

where the messages are transmitted in the form of 1’s
and 0’s.

➢ The SCSI and PCI buses use parity to detect

transmission errors, and many microprocessor instruction
caches include parity protection.

➢ In serial communication contexts, parity is usually

generated and checked by interface hardware (e.g., a
UART)

81
 Decoder and Encoder

82
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•Gujarati: વ ૃક્ષ (Vruksh)
•Kannada: ಮರ (Mara)
•Malayalam: മരം (Maram)
•Odia: ଗଛ (Gacha)
•Punjabi: ਰੁੱ ਖ (Rukh)
•Urdu: ‫( درخت‬Darakht)
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 Encoder and Decoder Applications

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 Encoder and Decoder Applications

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 Encoder and Decoder Applications

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 Encoder and Decoder Applications

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 ENCODER
• An Encoder is a combinational logic circuit.
• It performs the inverse operation of Decoder.
• The opposite process of decoding is known as Encoding.
• An Encoder converts an active input signal into a coded output signal.
• Block diagram of Encoder is shown in Fig.10. It has ‘M’inputs and ‘N’outputs.
• An Encoder has ‘M’ input lines, only one of which is activated at a giventime,
and produces an N-bit output code, depending on which input is activated.

A0 B0
‘2N’ Inputs

‘N’ Outputs
A1 B1
A2 B2

- - - - - --
- - - - - --

Encoder

AM-1 BN-1

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• Encoders are used to translate the rotary or linear motion into a digital
signal.
• The difference between Decoder and Encoder is that Decoder has Binary
Code as an input while Encoder has Binary Code as an output.
• Encoder is an Electronics device that converts the analog signal to digital
signal such as BCD Code.
• Types of Encoders
i. Priority Encoder
ii. Decimal to BCD Encoder
iii. Octal to Binary Encoder
iv. Hexadecimal to Binary Encoder

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 4:2 ENCODERS

➢ In 4:2 encoder, 4 inputs are encoded into 2 outputs,

each output representing one of the binary
equivalent of the four input variables.

BLOCK DIAGRAM TRUTH TABLE LOGIC DIAGRAM

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 8:3 ENCODERS

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 PRIORITY ENCODERS
➢ One of the main disadvantages of standard digital encoders is
that they can generate the wrong output code when there is
more than one logic-1 input.

➢ For example, if we make inputs D1 and D2 HIGH at logic "1"

both at the same time, the resulting output is neither at "01" or
at "10“.

➢ But it will be at "11" which is an output binary number that is

different to the actual input present.

➢ One simple way to overcome this problem is to "Priorities" the

level of each input pin and if there was more than one input at
logic level "1" the actual output only correspond to the input with
the highest designated priority.
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 PRIORITY ENCODERS

➢ Then this type of digital encoder is known commonly as a Priority

Encoder which includes the priority function.

➢ In priority encoder, if two or more inputs are equal to 1 at the

same time, the input having the highest priority will take
precedence.

➢ The higher the subscript number, higher the priority of the input. In
4:2 priority encoder, input D3, has the highest priority. So,
regardless of the values of the other inputs, when D3 is 1, the
output for xy is 11.

➢ D2 has the next priority level. The output is 10, if D2= 1 provided
D3= 0. The output for D1 is generated only if higher priority inputs
are 0, and so on down the priority levels.
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 4:2 PRIORITY ENCODERS

TRUTH TABLE

MODIFIED TRUTH TABLE

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96
 DECODER
• A decoder is a combinational circuit.
• A decoder accepts a set of inputs that represents a binary number and
activates only that output corresponding to the input number. All
other outputs remain inactive.
• Fig. 1 shows the block diagram of decoder with ‘N’ inputsand ‘M’outputs.
• There are 2N possible input combinations, for each of these input
combination only one output will be HIGH (active) all other outputs
are LOW
• Some decoder have one or more ENABLE (E) inputs that are used to
control the operation of decoder.

Input Output Input Output

n=2 22=4 n=3 23=8
 BLOCK DIAGRAM OF DECODER

A0 B0
A1 B1
A2 B2
. DECODER .
. .
. .
. .
AN-1 BM-1
N- Inputs M- Outputs
Only one output is High for
each input
Fig. 1
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 2 to 4 Line Decoder:
➢ Block diagram of 2 to 4 decoder is shown in fig. 2
➢ A and B are the inputs. ( No. of inputs =2)
➢ No. of possible input combinations: 22 = 4
➢ No. of Outputs : 22=4, they are indicated by D0, D1, D2 and D3
➢ From the Truth Table it is clear that each output is “1” for only specific
combination of inputs.
TRUTH TABLE
A D0
INPUTS OUTPUTS
2X4 D1
Decoder A B D0 D1 D2 D3
B D2
0 0 1 0 0 0
D3
0 1 0 1 0 0
Inputs Outputs
1 0 0 0 1 0
Fig. 2
1 1 0 0 0 1

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 BOOLEAN EXPRESSION:
From TruthTable
D0 = AB D1 = AB
D2 = A B D3 = AB
LOGIC DIAGRAM: INPUT OUTPUTS
A B S
A B
A B D0 D1 D2 D3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1

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 3 to 8 Line Decoder:
➢ Block diagram of 3 to 8 decoder is shown in fig. 4
➢ A , B and C are the inputs. ( No. of inputs =3)
➢ No. of possible input combinations: 23=8
➢ No. of Outputs : 23=8, they are indicated by D0 toD7
➢ From the Truth Table it is clear that each output is “1” for only specific
combination of inputs.

A
. D0
B 3X8 .
Decoder .
C .
D7
Inputs Outputs

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TRUTH TABLE FOR 3 X 8 DECODER:
INPUTS OUTPUTS

A B C D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 1 0 0 0 0 0 0 0 D0 =
0 0 1 0 1 0 0 0 0 0 0 D1 =
0 1 0 0 0 1 0 0 0 0 0 D2 =
0 1 1 0 0 0 1 0 0 0 0 D3 =

1 0 0 0 0 0 0 1 0 0 0 D4 =
1 0 1 0 0 0 0 0 1 0 0 D5 =

1 1 0 0 0 0 0 0 0 1 0 D6 =

1 1 1 0 0 0 0 0 0 0 1 D7 =

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 LOGIC DIAGRAM OF 3 X 8 DECODER:
INPUTS
A B C
A B C

D0 = A B C

D1 = A B C

D2 = A B C
D3 = A BC
OUTPUTS
D4 = A B C

D5 = A B C

D6 = A B C

D7 = A B C

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 CASCADING DECODERS

➢ To implement 4:16 decoder How many 2:4

decoders are need.
FIVE

➢ Decoder-1 is used to enable one of the

decoder 2, 3, 4 and 5. Inputs of the first
decoders are A and B i.e. MSB inputs of
4:16 decoders.

➢ The inputs of decoders are connected

together forming C and D inputs of 4:16
decoders.

➢ When AB=00 decoder-1 is enabled, for

AB=01 decoder-2 is enabled, for AB=10
decoder-3 is selected, and for AB=11
decoder-4 is enabled.
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 REALIZATION OF BOOLEAN EXPRESSION USING DECODERS
➢ The combination of decoder and external logic gates can be used to
implement single or multiple output function.

➢ The decoder can have one of the two output states either active low or high.

➢ For active high output (SOP function implementation) :

➢ When the decoder output is active high it generates minterm for input
variables (i.e) it makes the selected output logic1.

➢ In such cases to implement the SOP function we have to take sum of

selected product terms generated by decoder.

➢ This can be implemented by ORing the selected decoder output.

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➢ POS function implementation:
➢ When the decoder output is active high POS function in similar manner as
per SOP function except function output is complemented.

➢ This can be achieved by connecting NOR gates instead of OR gates .

SOP IMPLEMENTATION USING DECODER AND OR GATE

POS IMPLEMENTATION USING DECODER AND NOR GATE

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➢ Implement following SOP Boolean expression using suitable decoder:

F(A,B,C)=∑m(3,4,5,6,7)

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Implement following SOP Boolean expression using 3x8
decoder F(A,B,C,D)=∑m(3,8,11)

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 ➢ Implement following truth table using suitable decoder by considering only minterm

F(A,B,C)=∑m(3,5,6,7)
W(A,B,C)=∑m(1,2,4,7)

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➢ Implement following POS Boolean expression using suitable decoder:
F(A,B,C) = (A+B).(B+C).(A+C)
= (A+B+C.C’).(A.A’+B+C).(A+B.B’+C)
= (A+B+C).(A+B+C’).(A+B+C).(A’+B+C).(A+B+C).(A+B’+C)
= (A+B+C).(A+B+C’).(A’+B+C).(A+B’+C)
F(A,B,C) = πM(0,1,2,4)

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➢ Implement following truth table using suitable decoder by considering
only maxterm:

F(A,B,C)=πM(0,1,2,4)
W(A,B,C)=πM(0,3,5,6)

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 Full adder design using Decoder:

112
 Verilog Coding:
Refer to Lab Record Note

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 PARITY GENERATOR

(b) Testbench:
module tb_PG;
(a) Verilog code: reg a,b,c;
wire Peven;
module PG(Pe,A,B,C); PG PG1(Peven, a, b, c);
initial
input A,B,C; begin
a = 0; b = 0; c = 0;
output Pe; #100; a = 0; b = 0; c = 1;
#100; a = 0; b = 1; c = 0;
assign Pe = A^B^C; #100; a = 0; b = 1; c = 10;
#100; a = 1; b = 0; c = 0;
endmodule #100; a = 1; b = 0; c = 1;
#100; a = 1; b = 1; c = 0;
#100; a = 1; b = 1; c = 1;
end
endmodule
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 PARITY CHECKER

(b) Testbench:
module tb_PC;
reg a,b,c,d;
(a) Verilog code: wire pec;
PC PC1(pec, a, b, c,d);
module PC(PEC,A,B,C,D);
initial
begin
input A,B,C,D;
a = 0; b = 0; c = 0; d=0;
#100; a = 0; b = 0; c = 1; d=1;
output PEC;
#100; a = 0; b = 1; c = 0; d=0;
#100; a = 0; b = 1; c = 10; d=1;
assign PEC = A^B^C^D;
#100; a = 1; b = 0; c = 0; d=0;
#100; a = 1; b = 0; c = 1; d=1;
endmodule
#100; a = 1; b = 1; c = 0; d=0;
#100; a = 1; b = 1; c = 1; d=1;
end
endmodule
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 4:2 Encoder

module ENCODER(Q,D);
input [3:0]D;
output [1:0]Q;
reg [1:0]Q;
always@(D)
begin
case(D)
4'b0001:Q=2'b00;
4'b0010:Q=2'b01;
4'b0100:Q=2'b10;
4'b1000:Q=2'b11;
endcase
end
endmodule
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 4:2 Encoder Circuit – Test Bench

module tb_ENCODER;
reg [3:0]D;
wire [1:0]Q;
ENCODER E1(Q,D);
initial
begin
D =4'b0001;
#100 D =4'b0010;
#100 D =4'b0100;
#100 D =4'b1000;
end
initial
begin
$monitor($time,"D=%b, Q=%b", D,Q);
$dumpfile("[Link]");
$dumpvars();

end
endmodule

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 2:4 Decoder Circuit

module DECODER(Y,A,B,EN);
input A,B,EN;
output [3:0]Y;
reg [3:0]Y;
always@(A or B or EN)
begin
if (EN==1)
case({A,B})
2'b00:Y=4'b0001;
2'b01:Y=4'b0010;
2'b10:Y=4'b0100;
2'b11:Y=4'b1000;
endcase
else
Y=4'b0000;
end
endmodule

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 2:4 Decoder Circuit – Test Bench
module tb_DECODER;
reg A,B,EN;
wire [3:0]Y;
DECODER D1(Y,A,B,EN);
initial
begin
A =1'b0; B= 1'b0; EN = 1'b1;
#100 A =1'b0; B= 1'b1; EN = 1'b1;
#100 A =1'b1; B= 1'b0; EN = 1'b1;
#100 A =1'b1; B= 1'b1; EN = 1'b1;
#100 A =1'b1; B= 1'b0; EN = 1'b0;
end

initial
begin
$monitor($time,"EN=%b, A=%b,B=%b, Y=%b", EN,A,B,Y);
$dumpfile("[Link]");
$dumpvars();
end
endmodule

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 4:1 MUX

module mux_man(Y,D0,D1,D2,D3,S0,S1);
output Y;
input D0,D1,D2,D3,S0,S1;
wire S0bar, S1bar, and0,and1,and2,and3;
not (S0bar, S0);
not (S1bar, S1);
and(and0,D0,S0bar, S1bar);
and(and1,D1,S0bar, S1);
and(and2,D2,S0, S1bar);
and(and3,D3,S0, S1);
or(Y, and0,and1,and2, and3);
endmodule

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 4:1 MUX Test Bench
module mux_man_TB;
wire out;
reg D0,D1,D2,D3,S0,S1;
mux_man dut(Y,D0,D1,D2,D3,S0,S1);
initial
begin
S0 = 0; S1 = 0;D0=0;
#100; S0 = 0; S1 = 0; D0=1;
#100; S0 = 0; S1 = 1; D1=0;
#100; S0 = 0; S1 = 1; D1=1;
#100; S0 = 1; S1 = 0; D2=0;
#100; S0 = 1; S1 = 0; D2=1;
#100; S0 = 1; S1 = 1; D3=0;
#100; S0 = 1; S1 = 1; D3=1;
end
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endmodule
 1:4 DEMUX

module demux1_4(Y0,Y1,Y2,Y3,S0,S1,D);
input S0,S1,D;
output Y0,Y1,Y2,Y3;
assign Y0 = D & (~S1) & (~S0);
assign Y1 = D & (~S1) & (S0);
assign Y2 = D & (S1) & (~S0);
assign Y3 = D & (S1) & (S0);
endmodule

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 1:4 DEMUX Test Bench
module tb_demux1_4;
wire Y0,Y1,Y2,Y3; initial

reg s0,s1,D; begin

demux1_4 de(Y0,Y1,Y2,Y3,s0,s1,D); $monitor($time,"D=%b, s0=%b,s1=%b,

Y0=%b,Y1=%b,Y2=%b,Y3=%b",D,s0,s1,Y
initial 0,Y1,Y2,Y3 );
begin
D = 0; s1 = 0; s0 = 0; $dumpfile("[Link]");
#100; D = 1; s1 = 0; s0 = 0; $dumpvars();
#100; D = 0; s1 = 0; s0 = 1; end
#100; D = 1; s1 = 0; s0 = 1; endmodule
#100; D = 0; s1 = 1; s0 = 0;
#100; D = 1; s1 = 1; s0 = 0;
#100; D = 0; s1 = 1; s0 = 1;
#100; D = 1; s1 = 1; s0 = 1;
end
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