MICROPROCESSOR AND ITS APPLICATIONS

78

MEMORY INTERFACING WITH 8085

3.9.

ory made uup of

is made
semiconductor material used to store the programs and data. Three types ofmemory are
mem ory
The
.Processmemory

or main memory
.Primary

Secondary memory

EPROM and Static AM

3.9.1. Typical
semiconductor memory IC will have n address pins, m data pins (or output pins).
A VDical
A typic
other for connecting ground).
pins (one for connecting required supply voltage V and the
Having two power supply write
needed for static RAM are select (chip enable), read control
chip (output enable) and
.The control signals
control (write enable).
and read control (output
needed for read operation in EPROM are chip select (chip enable)
. The control signals
enable).

Number of Number of
Memory IC Capacity
address pins data pins
EPROM/RAM

2708/6208 1kb 10

2716/6216 2kb 11 8
12 8
2732/6232 4kb
13 8
8kb
2764/6264
15 O coy(2 8
27256/62256 32kb
16 8
27512/62512 64kb
128kb 17
27010/62128
256kb 18
27020/62138
512kb 19
27040/62148

Data Pins in Memory 1Cs

TABLE 3.4 Number of Address Pins and

3.9.2. Decoder
execution of a program. Number of ICs
used for decoder
the
It is used to select the memory chip of processor during
1S,
2-4 decoder (74LS139)
3-8 decoder(74LS138)
Input Output

Y3 (Active low) B
2-4 Y2 (Active low) 10
DECODER
74LS139 Y (Activelow) 0 1
Yo (Active low) 0 1 1
1 1

Fig. 3.9: Block Diagram and Truth

table of 2-4 decoder
 NERFACING AND DATA TRANSFER TECHNIQOE

Power aupply Input Output

GND
81 B
0

10,96
3-to-8
Decoder
74LS138 1 0
1 1 01
Y
Yo 1 01 11
0111

Enables
Fig. 3.10: Block Diagram and
Truth Table of 3-8 Decoder
EXAMPLE 1
onsider a system in which the full memory space 64KB is utilized for EPROM memory. Interface the FPD
8085 processor. EPROM wi
The memory capacity is 64 Kbytes, i.e.
2 xn= 64 x 1000 bytes where n =address lines.
So, n = 16.
I n this system, the entire 16 address lines of the processor are connected to address input pins of memorvIc-
order to address the internal locations of memory.
The clip select (CS) pin of EPROM is permanently tied to logic low (i.e., tied to ground).
Since the processor is connected to EPROM, the active low RD pin is connected to active lowoutput enablepind
EPROM.
The range of address for EPROM is 0000H to FFFFH.

Do-D7 Do-D7

ADg-AD7 8-bit Ag-AT Ao-A15

Latch
16
EN
8085
ALE
A-A15
A-A15
15 64KB
RD EPROM
27512

CS

Fig. 3.11 : Interfacing 64KB EPROM with 8085

 MICROPROCESSOR AND ITS APPLICATIONS
80

EXAMPLE2

which the available 64KB memory space is equally divided between EPROM and RAM.
system
in which
in
C o n s i d e r
a
and RAM
with
with 8085 processor.
EPROM

memory capacity ot EPROM using single IC 27256.

32KB
Implement 32K
mented using single IC 62256.
capacity is
32KB RAMf requires 15 address lines and so the address lines Ag-Ai4 of the processor are connected to l
memory requires
15
32KB.
and RAM.
The both EPROM
addresspins.
EPROM.
Theunused address line is used as to
A5 chip select. If A15 is 1, it select RAM and if A s is 0, it select
ed addres.
the m e m o
is used for selecting
Inverter
to low WE
ry 1sed is both RAM
and EPROM, so the low RD and WR pins of processor are connected
.The
respectively.
of memory
and OE pins
will be 0000H to 7FFFH and that of RAM will be 8000H to FFFFH.
of EPROM
TTha address range

8
Do-D7 Do-Dz
Ao-A15
Ag-A7
ADo-AD7 8-bit 8 WR
Latch
RD 16 RD
8085
ALE
Ag-A15
Ag-A15 16 62256
27256
RD RD
WR WR
CS
CS

A15
and 32 KB RAM with 8085
Fig. 3.12: Interfacing 32KB EPROM

EXAMPLE 3 Interface the

using four numbers of 8KB memory.
space is implemented
Consider a system in which 32KB memory
EPROM and RAM with 8085 processor. two
EPROM and the remaining
8KB memory be
let two number of
n
The t lal
memory capacity is 32KB. So,
numbers be RAM. to 13
are connected
the address lines Ag-A2 of the
processor
memory requires 13 address lines and
so
O
address pins of all the memory.
four chip select signals.
C dddress lines and A2- Au can be decoded using a 2-to-4 decoder to generate
one unc.
four memory IC at any
Ese four chip select signals can be used to select one of the
The address line
As is used as enable for decoder.
c Simplified schematic memory organization is shown in Fig. 3.15.
 TECHNIQUES Do-D7
TRANSFER
DATA
NTERFACING AND
AgA15

ADo-AD7 8-bit
Latch

8085 EN
8KB
ALE 8KB
8KB
RAM-II
ApA15 8KB EPROM-II RAM 6264
EPROM- 6264
RDRD 2764
2764
WRWRR CS S
CS
CS
A13
Ats
AE
with 8085
3.13: Interfacing 16 KB EPROM and 16KB RAM
Fig.
table.
The address allotted to each memory IC is shown in following
Binary address

Hex
Decoder Input to address pins of memory IC addres
Device enable/input
A10 Ag Ag A A As A Ag Ap A Ap
A1s A14 A3 A2 A 0
0 0 0 0 0 0 0 0 0 0 0000
00
0 0 0 0 0 0 0001
0 0 0 0 0
0 0 0 0 0 0 0002
8KB
EPROM-I
1 lFFF
1
0 0 0 0 0 0 0 0 2000
0
0 0 0 0 0 0 0 0 0 0 0 2001
0 0 0 0 0 0 0 2002
8KB
EPROM-II

0
0 : 000 00 0 0 0
1

0 0
1

0 0
1

0
1

0
3FFF
4000
0 0 0 0 0 0 0 0 0 00 0 0 0 1 4001
8KB 0 0 0 0 0 0 0 0 0 0 0 4002
RAM-I

11 1 1 5FFF
0 0 00 0 0 0 0 0 0 0 0 6000
0 0 0 0 0 0 0 0 0 0 0 0 1 6001
8 B 0 0 0 0 0 0 0 0 0 6002
RAM-II

1 1 7FFF

TABLE 3.5. Address allocation to each memory 1C.

82

EXAMPLE4
MICROPROCESSOR AND ITS APPLICATIONS
Consider a system which the 64KB
svstem in which 64KB memor
memory space is
EPRO and RAM with 8085 processo implemented using eight numbers of 8KB
the memory. Intertace
fol
.The memory capacity 1s 64KB, So, let 3 numbers of
8KB EPROM and 5
Each 8KB B memory requires I3 address
numbers, of 8KB RAM.
ines. So, the
address line ADA of the
address pins of all the memory ICs. processor are connected to l5

The address lines A13, A14 and Ai5 are decoded

using a 3-to-8 coder to generate eight
eicht chip select signals can be used to select one of chip select signals. These
the eight memories at any one time.
The memory interfacing is shownin following figure

Do-D7

D-Lat
ADg AD78 74LS373
(8-bit)
8085 EN
ALE
AoA15 Os Jols
RD RD
WR WR
2764 2764 2764 6264 6264 6264 6264 6264
8kx 8 8kx8 8k * 8 8k x 8 Bk x8 8k x 8 8k x B 3kx8
EPROM EPROMHI EPROM-II RAMA RAM-I RAM-II RAM-V RAM-V
CS CS CS CS CS S S CS

+5V
2
28

8 EPROMS and five 8K x 8 RAMS with 8085

Fig. 3.14 Interfacing three 8K x
 INTERFACING AND DATA TRANSFER TECHNIQUES
83
Binary address

Memory Decoder address pins Hex

IC chip input
Input to memory

As A A Ap
address
A1o Ag As A6 As
A15 A14 A13 A2 A 0 0
EPROM I 0 0 0 0000
0 0001
0 0002

1FFF
EPROM II 0 0 0
0
2000
0 0 2001
0 0 0 0 0 0 0
2002

3FFF
EPROM II 0
O
0 0 0 0 0 0 0 0
0 4000
0
4001
0 0 0 4002

RAMI
0
l 0 0 0 0 0
0
0 0 0
0
0
0
SFFF
6000
0 0 0 0 0 0
6001
6002

RAM II 7FFF
0 0
0 0 8000
0 0 0
0 8001
0 0
8002

RAM III 0 0 0
9FFF
0 0 0 0 0
0 0 0 0 0
0
O 0 0 0 0 0 0 A000
0 0 0 A001
0 0
A002

RAM IV
0 0 0 BFFF
0 0
0
0 0 0 0 0
0 0 0 CO00
0
0
0
0 0 CO01
CO02

RAM V
0 0 DFFF
0 0 0 0
0 0 0
0 0 0 O E000
0 0
0 E001
EO02

TABLE 3.6: address

allocation for Interfacing three 8K x 8
FFFF
EPROMS and five 8K 8
x RAMS with 808
 84
MICROPROCESSOR AND ITS APPLICATIONS
3.10. INE
NPUT OUTPUT INTERFACE
onnection between twO or more devices, Interfaces
An interarices, The type of intertace used consist of one or more wires and suppor o r
moreperiplheral depends upon the data requirements,
information between internal
storage and external /O Input/Output interface units a re
sed
f o rt r a n s f e r r i n g

devices.
Definition: VO
/ 0Interface:
rface: An
An interface is a
connection between two or more
support two or more peripheral devices devices, Interfaces consist of one o
m o r e w

ires and
i r e s a

these interfaces is to resolve the differences that exist between

T h ep u r p o :
are
the CPU and each peripheral connected.
differences

Themajor
1. Extemal peripherals are neripherals electromechanieal and
electromagnetic devices and their operating functions are different
from theoperation oerations performed dy the P u and
memory, which are electronic devices. Therefore, conversions of
values are required.
signal
mechanism sho should be needed between CPU and
A ynchronization external
are slowerthan the transfer rate
of CPU. peripherals because data transfer rate
ofpenphe
codes and formats in peripherals are different from word format in
Data the CPU and memory.
operating modes ofperipherals are different from each other and each peripheral device must be controlled so
4 The
a not to disturb the operation of other peripherals connected to the CPU.

problems are resoved by using vo modules or

These components as interface between the CPU and the
(components) termed as /O intertace or l/O modules. VO modules control the peripheral and peripherals.
nles are

ation with that of the CPU. CPU communicates with the peripheral through an I/O module. I/O modules synchronize
are used for
and error detection.
data buffering
and Interface Modules
s.10.1. 10 Bus
The bus connects the various peripheral devices (magnetic disk, printer and display terminal etc.) with
processor
1/0

shown in Fig. 3.15.

afa computer system is

Keyboard Mouse Magnetic Magnetic Printer

Disk Tape

Interface Interface Interface

Device
Interface Interface
Device Device Device Device

Data lines

CPU Address
lines
Control
VObus lines

Fig. 3.15: Connection of I/O Bus to Input/Output Devices

i sconsists of data lines, address linesandcontrol lines. The magnetic disk, printerandterminalareemployed
y any general purpose computer. The magnetic tape is used in some computers for backup storage. Each

devIce has associated with it an interface unit. Each interface unit decodes the address and control received
,nerprets them for the peripheral and provides signals for the peripheral controller. Each interface unit also
from
if s he data flow and takes control for the transfer between peripheral and processor. Each peripheral device has
s Own controller that operates the
particular I/O device.
 TECHNIQu 85
INTERFACING AND DATA TRANSFER
peripheral
devicee
s.
lines
major and
In
thisconfiguration, the I/O bus onsists ofthree the
processor
device
data
between

select a
specific
peripheral

wante
To differentiate
fe
Data Lines: The data lines
transfer
used to software
CSare
processor
to When
the to accesSS SOme
by the
are used each I/O
device.
wit
The
Anes:
VO devices, the system
address lines
unique a d d r e s s
designer assigns aa unique
to lines.
Circuitry
associated
the VO
crassigns

particular I/O device, it places the corresponding

a d d r e s s on
the
address

from or place
data on
the address line
nes. In
the data line
r Ca device
the data v a l u e on
device to read matches the intereOnds
ecognizes this address and instructs the /O
whose
address
addresS
l i n e s . when the
Each
ner /O devices ignore the request. Only the device the whosedetee
decoder that
monitors
All peripherals cts its
interface attached
Own
to the /O bus
us contar an
contains
address

address, it activates the path between the bus lines and

the device
that it
controls.
address does
espond to the address in the bus are disabled by theirinterta the flow
of data ween thes
between the
Control Lines: The control lines provide timing signals
to synchronize processor and
penipheral devices.
3.10.2. VO Commands
the paricular
VO module intere.
issues an address, specifying
nstructions, the CPU
commands that an
interrace nay receive whenit is ada nd
by
y aa CPIT
CPU.
d an vO command. There are 4 types of /O ressed
the peripheral and specifies the operas
COntrol Command: A control command. issued by CPU to activate ation of
peripheral i.e. to inform the peripheral what to do.
Example: A CD-ROM may be instructed by the CPU to go back or forward one track, printer may be instructe
by CPU to print the documents, etc.
hese commands belong to the particular type of peripheral device and each peripheral device receivesits
OWD
snguished sequence of control commands, depending on its mode of operation.
lest Command: A test command, issued by CPU to test various status conditions associated with an I/O modnla
(1nterface) and its peripherals after it is connected with external
whether the connected
The various peripherals. status conditions are
peripheral is ON or OFF, whether the peripheral is available for use (or busy),
most recent I/O
operation is completed or to check if any errors occurred. whether the
Read Command: A read
command, issued by CPU to read an item from of data the external
This command causes the /O
module to obtain an item of data from the peripheral connected
The CPU can then obtain an
item of data by
peripheral and place it in an internal buffer
requesting to the I/O module and place it on the
.Write Command : A write
command, causes the I/O module to take an item of data bus.
subsequently transmit that data item to the peripheral connected. data from the
data bus and
3.11. ADDRESS SPACE PARTITIONING
An address
space is defined as the set of addresses
address space allows a that can be
generated by microprocessor.
has 216= 65,536 or 64Kdesigner provide at least one memory or IO location
to
locations ranging from 0000H to in the
Each address in the
devices using this address FFFFH. The system. The address space of 8083
space. Microprocessor designer
provides separate instructions for has to connect both
This is done by 10/M memory and u
signal in 8085. addressing memory and I/O systems
1O/M =0;
microprocessor communicates with
IO/M =1 memory system
In /O
microprocessor communicates with I/O
addressing mode, 8085
has system
Mi capability
Mieroprocessor also provides 1acility to treat of
8-bit 1/O
I/o devices as address, through
memory map. Thus, due t two methods memory location. In which it can address
1. VO Mapped 1/O Scheme
of
interfacing 1/0 devices, we this case, one can map 255 VO pos in
I/O device
have two
2. Memory Mapped VO Scheme techniques of I/O ma
mapping i.e.
 86

[Link]
Mapped Vo VO MICROPROCESSOR AND ITS
Scheme (O Port Addressing) APPLICATIONS
1/Odevice is treat as IVO device
the /C

In
this
case,
only.
e
uses bits of address lines, and
8Rbi
IO
device
control signals
Each 1OR (Input Output Read) and
Write).
eO85 1OW (Input Output
address
bus of 80 microprocessor
8-bit address is tran
is of
16-bits,
but for VO
The
implement this, transferred on both
address groups devices only 8-bits address is used.
So, to
can use
group or combination of i.e. Ag to Aq and Ag to
ane ca
so one any one
are same,
available
of I/O
device is 50H. two A5. The
groups. Let us consider an contentsi
address
T h e c o n t e n t st r a nsferred
sfe on Ag A5 will be as follows:
to example
A15 A14 A13 A12 A1 A1o Ag As
A A6 As A4 As A2 A Ao
1 0 10 0 0 0
1 0 1 0

S o , we
can
use 50H address or we canuse Ag Or
Ag, A or Ag, Aq or Ajs and so on.0 0

as follows:
.This will be represented
AlA15 A/A14 As/A13 A/A12 Az/A11
A2/A10 A/Ag Ao/Ag
The above representation specifies that the line contents are same.
So, to address an /O device we can use or
be taken not to use Ao or
Ag. But a care m u s t
Ag and both.
Similarly, we can use other address lines also. Ag
are
two SDecial instructions available for data transfer between an /O
uO spec)
.There device and microprocessor. In VO
mappedI/O:
IN address
OUT address
In VO Mapped VO Scheme
31L.1.1. Input/Output Interfacing
.The address for I/O devices is of 8 bits. So, 2° = 256 1O devices can be connected to system.

.For input device, we requre 1OR Signal and for output device IOW signal. As with 1OW and 1OR one can
differentiate between input and output devices. So even if both the devices have same address there will be no

problem.
. The number of devices which can be connected are 256 input and 256 output devices.
.The simple example of input device is a buffer and output device is a latch. So, as an example of interfacing, we
interface a tri-state buffer IC 74244 (as an input device) and IC 74373 latch (as output device).
The IC 74244 contains two groups of 4 buffers.
The buffers are controlled by control pins 1G and 2G. When both are connected to logic low the 8 bit data from
input of buffer is transferred to output of buffer.
The IC 74373 contains eight D flip flops with tri-state buffer as output.

The (enable) latches are controlled by 2 signals G and OC is (output control).

Ine enable G is connected to CLK of each D flip flop. When G l the data is transferred from D input to output

and when G =0 the data will get latched in D flip flop.

when
1e
Output control is used to enable the tri-state buffer. When OC
=
0, the buffer will be on and transfer data,
OC=1, the buffer will be off and will not transfer data.
should be synchronised with 8085,
mtertace these devices to 8085, the control pins of I/O devices
and controlsignal TOR
.

combination of address
evIce control pins 1G and 2G should be connected to
on to bus.
C IG and 2G and are active the buffer will get enabled and transfer data
latch. So, the G input
Sin
OC to eround and use enable G input to control the
1 0 r output device we connect

nected to combination of address and control signal 1Ow

INTERFACING AND DATA TRANSFER TECHNIQUES
3.16.
is shown in Fig.
The interfacing ofinput and output device
Oo4
O14
O24- Buffer
O3 74244
O44
O54
O64
O7

TOR-

C mT
Oo
OW- O1
Latch
Ap 74373
Os
O6
O7

Fig. 3.16 : Input/Output Interfacing in 1/O Mapped I/O

The interfacing diagram is dividedinto two separate parts:

1. For input device i.e. buffer.
2. For Output device i.e. latch.

For both the interfacing diagrams, the combination of address lines is done by 8 input NAND gate. Theadk
lines used are Ag to A7, (or you can use Ag to As also).
.When the combination of input get satisfied the output will be low and for all other combinations it will be
This output is then combined with control signal IOR or IOW to generate signals to enable buffer and latc
The output of buffer is connected to data bus and input of latch is connected to data bus.
The address of input and output device is calculated from combination of address lines as follows:
1. Input device = 1111 111l = FFH

2. Output device = 1111 1110 = FEH

Instead of logic gates, decoder logic can also be used to do the same function. When the decoder logic is usec
its many outputs one of the is used to enable one
output device.
The general interfacing of I/O devices is shown in Fig. 3.16.
The two cases of
address selection logic:
1. Using logic gates
2. Using 3:8 decoder
are shown in Figures 3.16 and 3.17 respectively.
 MICROPROCESSOR AND ITS APPLICATIONS
8 8

ALE

LE Ao-A7 Address
ADo-AD7 Latch
decoder Enable

O/P VP
Do-D7
Buffer
GND- Vcc 74244
8085
G2B G2A G1
TOW
IO/M C 8
decoder IOR
RD 74138 MEMW Enable
WR MEMR
oIP VP

Latch
74373

Fig. 3.17: General /O Device Interfacing

is shown. The inputs applied are
the address decoder A7-
In Fig. 3.17,
Ap4
The details Ao-A7. Use of 3: 8 decoder is shown in
of
Fig. 3.18.
devices can be calculated as follows: 4
The address of/O
the decoderwillbe enabled
When A-l A=l As=l A4=l A^=l,
A, B and C. When A=0, A =0 and A,-0 GB G2A G
and will accept inputs
the 0th output
will get activated and A=l, A-0, A=0 the first A2
activated.
output will get A B 3:8
address will be decoder
So the F8H Ao- 74138
To latch
To buffer
Buffer 1 11 11 000
Latch 1 11 11 001 FOH Fig. 3.18: The use of 3:8 Decoder
for generation ofcontrol signals IOR,
Ifwe are using 3 :8 decoder IO/M-
generation of select lines for input/output devices. A7
IOW and for
decoder A6
These two decoders can be combined so that need of one
same function using one
decoder and few A5-
can be reduced and we get
gates.
with few
I t will be same as we have used in memory interfacing,
G2B G2A GL
changes but the basic concept remains same. It is shown in Fig. 3.19.
C
is added. When
lo enable the decoders one condition of IO/M
1O/M =1, it is an I/O related operation and so the decoder will get A 3:8
decoder
Cnabled. Now in this case, instead of using IOR and IOW , we can 74138
Ao
Use RD and 1OW directly. Fig. 3.19: The use of 3:8 Decoder
Ihe address will remain same i.e.
F8H, F9H only a need of decoder
wnich is used for generation of control signals is reduced.

3.11.2. Memory Mapped /0 Scheme

in this case, I/O devices treated as memory locations.
are
There will be no
separation like memory or /O.
Each VO device will have 16-bit address.
The con MEMR and MEMW,
dis used will be same as memory i.e.
 INTERFACING AND DATA TRANSFER TECHNIQUES
The interfacing between the I/O and microprocessor will be same as single memory
nstructions for I/O device will be memory related instructions, for e.g. LDA, STA, LDAX, STAx, Mohinis
MOV M, A etc. cationAX, MOV A
location.
Because oe
th
The number of /O device will be 64K shared
by I/O and memory.
For data transfer,
microprocessor will send address on Ag to As lines and generates control
signals or
and MEMw.
The interfacing diagram is shown in
MEM
Fig. 3.20.

Oo-O7 Buffer
lo-I7 Ap lo-17 Latch
O0-O7
A14
Oc
A15
A15 MEMW
MEMR-
Fig. 3.20 : VO Interfacing in Memory Mapped VO
I n MEMR , it accepts data from I/O device while in MEMW it transfers data to lO device.

[Link]. Input/Output Interfacing in Memory Mapped 1/O Scheme

The general interfacing diagram of an /O device with 8085 in memory mapped IIO scheme is shown
in Fig. 321
RD MEMR RD
As-A15 DE Buffer

Oo-O7 lo-17
A15

8085
Ag-A14
ALE
D- Latch
ADo-AD7 VLatch Ao-A7.
Mlo-7 Oo-O7
WR MEMW
OC
Fig. 3.21: Interfacing of Input and Output Devices
.The simple input device is a buffer and output device is latch. To interface these devices to
1G, 2G of buffer and G input of latch is controlled from 8085. 8085, the control lines

The address is of 16 bits Ag to

As and control signal MEMR and MEMW are used to control the buffer latcn.
.The combination of address lines
Ag to Ajs can be done by using NAND gates and then it is combined wiu
MEMR and MEMW signal.
.For buffer when A to As all are 1's the output of NAND gate will be low.
I t is then combined with
MEMR using NAND gate with inverted and connected the
address of buffer will be FFFFH. inputs to 1G
and 20. D
For latch when
Ao to Aj4 all are 1's and the line
Ais MEMW =
0, the output of NAND gate will be low,1tis t hen
combined with MEMW using AND gate with inverted be
TFFFH. inputs and connected to G, so the address of latch wi
Instead of gates, a 3:8 decoder logic can be selected the appropriate device.
 MICROPROCESSOR AND ITS APPLICATIONS

9 0
MEMORY
MPARISON OF ME MAPPED AND VO MAPPED VO SCHEME
3 . 1 2 .C O M

hetween memory mapped and I/O mapped VO scheme is very small; one cannot say that On
b e t w e e n
memor
unc

The
difference

In the final analysis,

wnich scheme is
actually used is a matter of convenience and depends upon
i
o t h e r tho two schemes are as follows
the
of
to cons
and
i/o
pros
scheme, we can typically address more I/O devices. This is because in /O mapped
supernor

The
mapped I/O scheme.
I/O
mapped
designer.

Using
memory nited numbe
limited
number of address lines usually carry the useful information. For example, the 8085 Can
scheme,
only a
64K memory locatio. tions but only 256 /O ports using I/O mapped I/O scheme, whereas in memory mapped
e r number
of addresses can be assigned for VO ports. This is at the most a very dubious advantage
/ O scheme
V Os c h e m e

maPped
of m e m o r y
in favor edVO
/0 sscheme, we can distinguish between separate I/O and memory address spaces.
mapped

Using
/O
implement
direct memory address (DMA) technique while using /O mapped I/Oscheme
dire
ier to for 1/O mapped I/O scheme, to transfer the data from I/0 devices is limited 1.e.
instructions available
ofins
varietyof other hand, in
can be used for the data transfer from input/output ports. On the
The OUT instructions
and O0
A, M etc. can be
scheme, a variety of instructions such as MOV r, LDA addr, IN, OUT, MOV
IN
only I/O sch
mapped
memory
transter from the VO ports.
data
ITsed for the comparison between memory mapped and I/O mapped IVO schemes:
the
Following is

Memory Mapped /O Mapped

1. 8-bit device address is used.
address is used.
device and
1. 16-bit general-purpose register 2. Data is transfer only between accumulator
between any
[Link] transfer VO port
and 1/O port 256
1s shared between
I/O device 3. The IO map is independent of the memory map;
map (64K) be connected.
input device and 256 output device
can
The memory
Th
3
and system memory.
8-bit address.
decode 16-bit address. 4. Less hardware is required to decode
is required to cannot be directly
4. More hardware 5. Arithmetic or logical operation
can be directly
or logic operation data.
5. Arithmetic with performed with I/O
/O data.
performed can be used for data
can be used for 6. Only IN and OUT instructions
related to memory
6. All instructions transfer.
data transfer. interfaced.
can be interfaced.
7. Only 256 ports can be
number of I/O ports available.
7. A large 8. Whole address space is
is available due to partitioning.
8. Less memory space and 9. The devices are accessed by I/O read and IO write
accessed by memory read
9. The devices are cycle.
memory write cycle. cannot be directly
can be directly 10. Arithmetic and logical operations
10. Arithmetic and logical operations performed with I/O data.
performed with I/O data.

3.13. INPUT/OUTPUT INTERFACE or

more wires and support two
Interfaces consist of one or
is connection between two or more devices. intertace units are
data requirements. InputOutput
An Intertace a
the
interface used depends upon
peripheral devices. The type of vo devices.
IOr information between internal storage and external connected.
cd transferring between the CPU and
each peripheral
differences that exist
of these interfaces is to resolve the
pupose
The major differences are functions are different
devices and their operating c o n v e r s i o n s or
electromagnetic
are electromechanical and Therefore,
Penpnerals
electronic devices.
fr performed by the CPU and memory,
which are
perations
isignal values are required. rae
external peripherals
because data transrer
between CPU and
ynchronization mechanism should be needed
Or peripherals are slower than the transfer rate of CPU.
CPU and memory.
and formats in peripherals are different from
word format in the so
COdes must be controlled
4. T other and each peripheral device
different from each
as ho g modes of peripherals are to the CPU.
O o disturb the
operation of other peripherals connected
 TECHNIQUES
INTERFACING AND DATA TRANSFER
as interface between
the CPU and thea 91
I/O modules or comnponents control the peripheral and sPhea
These problems are resolved by using I/O modules
interface or I/O modules. module. I/O moduleshron

usedonizfor
(components) are termed as I/O an I/O les are
These modules that of the CPU. PU c o m m u n i c a t e s with the peripheral through
itsoperationwith
data buffering and error detection.
TRANSFER
3.14. MODES OF VO DATA stored in memory
device 1s mostly for
to an external
transferred from central computer or
the main storage for input oat
Binary information instructions and store data temporarily,
but
the /O TheCPU Canda
processing. The CPU
executes transter functions.
to handle I/O data
Is the memory unit. There
different modes have been adopted the path ect
CPU as an intermediate
Some modes use
methods mentioned ahead.
control peripherals or uses one of the are discussed as [Link]
unit. These modes
transfer and others transfer the data directly to and the memory
from
2. Interrupt-Initiated Input/Output
3. Direct Memory Access
1. Programmed Input/Output
3.14.1. Programmed Input/Output
all needs of an Input/Output device. If data tr
A CPUis general purpose processor. It is capable of addressing
a transfer
that initiates, directs and terminat
the CPU executes a program
operations are completely controlled by the CPU, i.e. This is the simplest strategy for handie
lnputOutput operation, the computer is said to be using Programmed Input/Output. dling
communication between the CPU and an /O device.
hardware costs need to be minimized.
Programmed Input/Output is a useful method for computers where
I n Programmed Input/Output, the CPU is responsible for all communication with /O devices and for extracti
data from the main memory for output and storing data in main memory for input.
ng
Entire Input/Output is handled by CPU with the help of small software (system software/device driver) without anny
additional hardware.
Programmed Input/Output involve two operations:
Transfer of data from VO devices to the CPU registers.
Transfer of data from CPU registers to I/O devices.
Programmed Input/Output operations can be done by writing I/O instructions in the computer program. Each data
item transfer is initiated by an instruction written in the program.
Example: Suppose the CPU wants to send data to a device using programmed I/O. CPU issues an instructiontothe
appropriate VO interface belonging to that device. Then CPU waits until the module responds. After that, CPU sendsthe
data. Generally VO interface are slower than the CPU. That means CPU has to wait until the data transfer is complete
[Link]. Data Transfer from VO Devices to Memory through CPU
The data transfer from an /O device through an
interfacing unit into the CPU is shown in Fig. 3.22. How the data is
transferred from IO device to CPU through an interface is explained in steps below:
1. As the byte of data is available into an VO device, it transfers bytes of data one ata time into an I/O bus
its data valid line. and enables
2. The interfacing unit
accepts the byte from the I/O bus and stores into its data register and enables the
line. As the data is accepted, the
interfacing unit sets its flag bit F in the status register. data accepted
3. CPU constantly checks the status
flag bit. If the flag bit is equal to 1, the CPU reads the data from
After the data transferred, the the data registet
flag bit is cleared to 0.
4. Once the flag is
cleared, the
interfacing unit disables the data accepted line and the I/O device can then
next data byte.
transfer tne
Data bus Interface Unit
I/O bus
Address bus
Data Register
CPU Data valid
/ORead /O device
VO Write Data accepted
Status register F

Fig. 3.22: Data transfer from

I/O device to CPU
b
 MICROPROCESSOR AND ITS APPLICATIONS
wn in Fig. 3.25 shows the sequence of steps that must occur. The transfer of each byte requires three
92
The
flowchart.

instructtons status
register.

the
the flag bit F and go to step 1 if itis
[Link] the
ctafus of
status
the of
p3 if it is SET (logic 1).
Check o r go to step.
0)
2.
not
SET (logic Read data register
register.
data
the
Read programming for
called software
3. iane is also
is also
performs all transfers to
technique

Check flag bit

Here the processor
This
1 0
d a t a t r a n s f e r

In this programmed
I/OO method, fore
PU constantly check the
devices.

the CPU
and
from is performed,
peration tis free or it has
has finished
fi inputting
I n p u tO
/ utput is free orit
w h e t h e r i t
= 0
device nding a read or write commands, Flag
status oas ofI/O o r data,
sending a
series
When the CPU issues a command to
thecurrent he data. 1
wait untilthe /O coperation is complete.
the I/O
must
it
theI/O
module,
faster
than VO module, this is wasteful of
CPU is Read status register
Ifthe
CPU
time.
3 . 1 4 . 1 . 2 . D r a w b a c k s

I/O technique is very

time consuming Transfer data to memory
lot of time checking and verifying
1.
Programmed

CPU wastes
bed
device.
of an I/O
the status for character
and suitable
i/0 1s slow
2. Programmed printers, keyboards
VO devices such as
transmission No
Operation
and monitors. Complete

inefficient in terms of CPU usage.

3. This is a great deal of CPU
I/O mode requires
The programmed this inefficiency, Yes
transfer. Because of
to carry
the data
Overhead DMA was created
to increase
initiated and
the interrupt I/O method is particularly
useful Continue with
programmed
performance. The that are dedicated
program
or in systems
low speed computers
insmall difference in information The data
tomonitor a
device continuously.
this Fig. 3.23: Flowchart for CPU program to input
between the CPU and
the I/O device makes
transfer rate where high transfer
inefficient. So, it is used
type of transfer
ratesare not required.

Initiated I/O
3.14.2. Interrupt Initiated Input/Output. In
CPU performance is known as Interrupt
Another technique that can considerably
improve When the I/O operation
device and starts executing other programs.
the I/O command to /O shown in Fig. 3.24.
CPU
thmis technique, the CPU issues CPU by informing the CPU that Input/Output has finished as
Complete, VO device interrupts
s be
then may proceed with execution of original program. efficient. The device send interrupt
when there is data to
transfers technique is more the processor to
Tpt initiated I/O data the devices. This releases
need to continuously
check the status
need not to check out
the of
.iere the processor does not programmed I/O because CPU
is better than data.
during this period. This method it has to transfer the
the CPU whenever
lasks
dei the devices itself will interrupt The sequence or
w a n t to transfer the data. Instead, the level of performance of the system.
ime. initiated I/O technique increase
Interrupt
evon Or
eventsis as follows: other instructions.
to execute
then CPU continues
I/O command to the I/O module and
S u e s an module interrupts the
CPU.
2. data with CPU, I/O
is to exchange the
o d u l e ready
S. The CPU
finishes executing the current instruction.
4. The CPU
acknowledges the interrupt.
 INTERFACING AND DATA TRANSFER TECHNIQUES

5. The CPU saves its current state. 93

6. The CPU jumps to a sequence of instructions that will handle the interrupt.
This situation is somewhat complicated by the fact that most computer systems will have several devices (periph
connected to them. This means the processor must be able to detect the interrupting device and to decide which inter
handle if more than one intermupt occur simultaneously. This decision is usually based on interrupt priority. Some de
will require quickly response from the CPU more quickly than others. device
Erample: An intemupt from a disk drive must be hand i more quickly than an interrupt from a keyboard
Interrup
is an asynchronous mechanism. Each device is connected to an interrupt line. When a device needs service, it asserte
intemapt line to roquest the processor attention. the
Memory

Data busS
CPU

INT

Fig. 3.24: Interrupt Initiated /O Transfer

142.1. Working of Interrupt Initiated /O

From 1/0 Module's Point of View
For input, 1/O module receives a read command from the CPU. The IVO module then proceeds to read information
(data) from an associated peripheral. Once the data is transferred to the I/O module's data register, the VO module issues
am intemupt
signal (INT) to the CPU over a control line as shown in Fig. 3.25. The 1/O module then waits until its dataare
iegucsted by the CPU. When the requestis granted by interrupt acknowledge (INTA), the V/O module transfersitsdataon
the data bus of CPU and the 1/O module is ready for another operation.
From CPU's Point of View
For input, the CPU issues a read command to the I/O module, CPU then
goes off (in high impedance state) from the
O module and execute other instructions because the CPU works several different
programs at the same time. At the end
of each instruction cycle, the CPU checks for from
interrupts the VO module. When the interrupt from the VO module
occurs, the CPU saves the curent
program and processes the interrupt. Now, the CPU reads the data from the I/O module
and stores it in main memory. CPU then restores the it was
program working
on and resumes execution.
VO Read

INT

INTACK
CPU Data bus
Device
Address bus

/O Write

Fig. 3.25: Data Transfer between CPU and VO device

[Link]. Comparison between Programmed and Interrupt Initiated I/O
1.
Programmed Input/Output can be implemented with the
help of software without any additional
Whereas,in interrupt initiated, additional
hardware is required to handle hardware COs
interrupt.
 MICROPROCESSOR AND ITS APPLICATIONS

is simp implement and it is used in low end systems where cost is a very important
94 Input/Output mple to
ed are based on interrupt initiated Input/Output.
c o n t e m p o r a r y computer systems
2 Progra
of the device.
factor. M o s t
nut/Output is based on busy waiting. CPU keeps checking the status of the input/output
to become
Programnied
Inpui
ce, input/oup devices are very
slow, CPU will have to waste lot of time waiting for the device
device to
I/0, CPU SWitches to some other program without waiting for the input/output
initiated I/0,.
initiated
interrupt
In free
Whereas, multiple Input/Output
become
dy
o r to
complete
tlOutput activity
can be
handled using Programmed Input/Output.
one
Input/Ou
in overlapped fashion with interrupt driven Input/Output.
camiedou
Only be
4 can
activities
Memory Access (DMA)
S.14.3.D i r e c tM e r
In thiscase,
do other useful work while the I/O is in progress.
to allow the CPU to
desirable
be desi and I/O devices. The
it may can be used to transfer data between memory
led aa DMA Controller data
cases,

address,
cessorcalled over control of the system bus from the CPU, and like the CPU, generates
e
in
tically takes
between memory and 1/0 devices.
DMA r o l e rp e r i o d i c a

nsfer data to send data

signals
to
in modern computers that allows peripheral devices
Access, a capability used for
t Memory
is an I/O technique commonly without
cantrol
nd StandsforDirect intervention from the CPU. Direct Memory Access
DMA
and memory
nemory without
main
memory
Access is a method
Memory
transferring data between peripherals
of
Direct
othe dota transfer.
hghspeed
asingtheCPU to device or from device to memory.
blocks of data from memory
transfer large
DMA
can
lines on system
bus.
Address/LData
same
.Uses
bus.
Controls the system transfer.
require
the processor for data device and main memory
without the
intervention

D o e s not transfer information

data is directly
transferred
between
a peripheral external devices to directly
Inthistechnique, to improve
system performance by allowing
designed
nfthe CPU. I is and allow multitasking.
Normally,
from the system
memory.
bus
architectures to speed up computer operationsreading/writing data in the internal
in computer the DMA allows
DMAis implemented read/write operation. Enabling available for other tasks.
occupied in any thus making the processor
heCPU willbe computer operations
fully CPU involvement,
without common
and peripherals is one
ofthe most
memory, external memory of data to/from memory controller in a sense
movement The DMA
improvementin performance.
as
operations,
Thisensures streamlinedthis overhead can lead to a significant

andfreeing the CPU of the system. to and from a memory

subsystem
without

is2 second processor in

I/O subsystem transfer
to data
Access: The ability of an
Direct Memory in the
memory subsystem
an /O subsystemand a
processorintervention. transfers between
that can control data
DMA Controller: A device
control such transters.
Same manner that a processor can is
microprocessor
while the
3.143.1. Basic DMA Operation access to the
memory

(DMA) I/O technique

provides direct
e direct memory
access

from the microprocessor

and
control bus
temporarily disabled data bus, and
the address bus,
series of memory locations
borrows
A temporarily
ontroller between an 1/0 port and a
the data bytes directly
sCts memory-to-memorytranstets. system.
lhe DMA transfer is also used to do high-speed transfer in the
microprocessor-based

buses after
the
a DMA
and acknowledge
release control of the
Two control signals are used to reque
uest to
microprocessor
asks the
The HOLD signal is a bus reque
quest signal which control of its
released
current bus cycle, has indeed
microprocessor
indicates that the
which
bus grant signal
ne HLDA signal is a states,
by placing the buses at their high-impedance
interrupt inputs.
ucs
or TRAP
than the INTR
The HOLD input has a higher iority
 INTERFACING AND DATA TRANSFER TECHNIQUES

DMA controller takes control of the buses and transfers data directly between source and destination w 95
involvement of CPU, thus bypassing the CPU.
thest
Memory DMA
HOLD

CPU
Data Bus

UOO
Fig. 3.26: DMA Controller operation with HOLD signal
Then transfers the data bytes directly between an /O port and a series of memory locations.
At the end of the data
transfer, the DMA controller disables the HOLD line. The CPU disables the HLDA regains
control of the buses and return to its normal
operation.
[Link]. Transfer Modes
Direct Memory Access (DMA) is much more efficient technique for data transfer between peripherals and main
memory. DMA uses an additional
piece of hardware called DMA Controller. The DMA Controller takes over the control of
system buses and transfer data between
the DMA Controller cannot use the
peripheral and main memory without the intervention of the CPU. The CPU and
system bus at the same time. DMA controller use three methods for data transfer:
1. Burst Transfer
2. Cycle Stealing
3. Transparent Mode
Burst Transfer
In DMA, burst transfer i.e. a block of memory words, is transferred
peripheral device.
continuously between main memory and
.It is the fastest DMA transfer.
.The microprocessor is disconnected from the system bus during DMA transfer i.e. the
executes its own program during this transfer. microprocessor cannot
.Nnumber of DMA cycles are added into the machine
cycles of the microprocessor where Nis the number of
to be transferred. bytes
In this mode, the DMA controller sends HOLD' signal to the
After receiving HLDA
microprocessor and waits for 'HLDA' signal.
signal, the DMA controller gains control of the system bus and execute
byte. to cycle transfer one
After transferring one byte, it increments memory address and decrements counter and
In this way, it transfers all data transfers next byte.
bytes between memory and VO devices. After transferring all data
controller disables 'HOLD'
signal and enters into slave mode. bytes, the DMA
Cycle Stealing
The cycle stealing mechanism
allows the DMA controller to transfer one
After transfer of one byte of data, DMA byte of data at a time.
controller handover the
This type of DMA is slower than burst DMA. system buses back to the CPU.
The DMA controller transfers one word
at a time by
DMA controller takes control of buses for pausing the CPU for a single clock cycle on each
that clock instruction.
cycle to transfer the data between peripheral and main
memory
 MICROPROCESSOR AND ITS APPLICATIOONS
96 down the CPU slightly overall, but will still be very efficient. The CPU will delay its processing for
This mayk cycle. DMA controller steals out one clock cycle rapidly after sometime for data transfer between
o n l yo n e c l o c
peripheral.
and
memory

main
the DMA
oller sends 'HOLD' signal to the microprocessor and waits for HLDA signal.
controll
mode,
In this HLDA signal, the DMA controller gains control of the system bus and execute only one DMA
A f t e rr e c e i v i n

cycle. ceing One byte, it disables 'HOLD' signal and enters into slave mode.
After transferring

zains control of the system bus and executes next machine cycle.
T h e m i c r o p r o c e s s o r

ic not zero and next data is available then the DMA controllersends "HOLD' signal to the microprocessor
count is n o t .
block.
I fthe next byte of data
transfers
and
T r a n s p a r e n tM o d e

controlleroonly transmits data when the CPU doesn't need the system buses.
DMA
mode,
In this CPU does not require the system buses. At that time DMA controller may use ystem
During micro-operation

buses.
called hid idden DMA transfer mode.
is also
This transfer is not widely used because pipelining makes this difficult to do.
This mode
ofdata controller monitors the execution
bus when the processor is not using it. The DMA
T h e DMA
A controller controller grabs the
and
takes control of the system buses when CPU does not require.
processor
ofthe but continues processing normally.
This processor is not slowed down, to be using the
ofthis technique. As the processor likely
the use
is
utilizing cache and pipelining prohibit
Processors
while decoding the current opcode.
bus (pre-fetching)

GLOSSARY
O
Address Bus locations (addresses)
that is used to identify particular
CPU with main memory
wires connecting the
location or device is being
carried over by address bus.
A collection of The address of memory
called address bus.
in main memory is

Address Register contains the starting

location in memory. It
address tospecify the desired data are available
The address register of DMA contains an
be stored (write operation) or where
where data are to
data bus to memory.
address of memory block through incremented after each
word that is transferred
is
through (read operation). The address register

Burst Transfer burst between main memory

and
transferred in a continuous
words, is
transfer, a block of memory
Durst devices like magnetic
disks.
transfer of data in
u
DA, needed for faster
Penipheral. This mode of transfer is

Bus Controller data transmitted on a

bus.

for sequencing and timing

of the
d t generates commands and control signals

Control Bus within the computer

is

between the CPU

and other devicesc o m m u n i c a t e s witn the
The d
call Connections that carry control
information
that control how
the processor
DUs. The control bus is a
collection of signals
oe0L
rest of the
Tect
system.
Cycle Stealing word at a time.
transfer one data
ycle stealing mechanism allows the DMA controller to
INTERFACING AND DATA TRANSFER TECHNIQUES
97
Data Bus
A Collection of wires through which data is transmitted from one part of a computer to another 1s caled data bus
. It is

used to carry data among the various components of computer system.

Data Lines
devices.
h e data lines are used to transfer data between the processor
and peripheral

Direct Memory Access (DMA)

data transfer. In this technique, dat.
Direct Memory Access is I/O technique commonly used for high speed
an
CPU. For examni
without the intervention of
directly transferred between a peripheral device and main memory mple
data transfer between system memory and a floppy disk.

DMA Controller
The DMA controller manages data transfer between the system memory and a peripheral under its control. DM
controller communicates with the CPU via the data bus and control lines. It needs an address register, a word co
count
register and a set of address lines.

Inputlnput
Devices
devices are an electromechanical devices that accepts data and instructions from the outside world i.e. users d
the examples of the input devices
put them in a form the computer can understand. Keyboard and the Mouse are

Interrupt Initiated VO
In this technique, the CPU issues the I/O command to I/O device and starts executing other programs. When the I/O
operation is complete, VO device interrupts CPU by informing the CPU that Input/Output has finished. Interrupt
initiated IO data transfers technique is more efficient. The device send interrupt when there is data to be moved. Here
the processor does not need to continuously check the status of the devices.

VO Interface
An interface is a connection between two or more devices. Interfaces consist of one or more wires and supporttwoor
more peripheral devices.

VO mapping
The assignment of addresses to various I/O devices in the memory chip is called as I/O mapping

Keyboard
A peripheral device consisting of alphanumeric, punctuation marks, and other special function keys that aremechanically
arranged to allow the entry of data, commands, and other information into the system.

Monitor
The screen for viewing computer information is called a monito.

Mouse
In d the
computer parlance a be both the physical object moved around to control
mouse can
pointer itself. Unlike the animal, the proper plural of computer mouse is "mouses".
a pointer on the sereen, andu

Non-Impact Printers
A non-impact printer forms characters and graphics on a piece of paper without actually striking the
paPo
Output Devices
Output devices the devices that
are are used to display the results. Printer,
ples

of the output devices.

speaker and the monitor are the c
 Sanala Noun
MICROPROCESSOR AND ITS APPLICATIONS

vices
P e r i p h e r a lD e v i c

or daa
are e the computer devices that are internal or external to a computer and used in the transfer
vices
Peripheral
de computer.

a
from
or
to

Plotter
nrinter that generates high-quality documents by moving ink pens over the surface of a page

ater is
a
largrv useful to engineers and architects, as they produce high-quality blueprints, maps, and floor
P l o t t e r sa r e p a r t i c u l a r

plans.

the
(either parallel or serial), terminated at a connector on the computer. It interconnects
Port channel
An input/outp

and/or
minals to an appropriate source and/or destination.
output termi
's input
com

Printer
outnut device that produces text and graphics on a physical medium such as paper. Printed information
that
than
1sSa n c
because
because the information exists physically and is a more permanent form of output
hardcopy
printer

A called,
often
is (Monitor).
VDU
presentedona
P r o g r a m m e dI n p u t / O u t p u t

and for extractingdata

the CPUUisis responsible for all communication with I/O devices
Input/Output,
and storing data in main memory for input. Data
transfer operations are completely
In Programm
a the main memory for output terminates the Input/Output operation.
from th
the CPU executes a program that initiates,
directs and
nlle the CPU, i.e. by

Storage D e v i c e s
disk and
device that is used to store
the information such as hard disk drive, flash drive, floppy
Actorage device is a

the tape drive.

Word Count Register one after each

transferred. This register is
decremented by
number of words to be
The word count register
holds the indicates that whole data is
for zero. When word count register reaches zero, it
tested
transfer and internally line.
word controller disables the bus request (BR)
At the end transfer, the DMA of data
transferred.
SOLVED QUESTIONS A N S W E R S

QUESTIONS
SHORT ANSWER TYPE
(May 2006)
1. Describe the concept of DMA data transfer.
(Dec. 2006, May 2006)
Explain briefly. DMA mode of data transfer. devices to send
that allows peripheral
Direct Memory Access, a capability
in modern computers commonly
banas
for
Memory Access is an I/O technique
without intervention from the CPU. Direct and
m a i n memory data between peripherals
used f Access is a method oftransferring
speed data transfer. Direct Memory
memory without using the CPU.
C a n transfer large blocks of data from memory to device or from device to memoy

Uses same Address/Data lines on system bus.

Controls the system
bus.
Does not require the processor for data transfer. intervention
without the
In this device and main memory
hnique, data is directly transferred between a peripheral
rectly trans transfer information
f the external devices to directly
CPU. It is ystem performance by
allowing
from the
to designed imp
system memory.
 INTERFACING AND DATA TRANSFER TECHNIQUES

Q.2. Diagrammatically explain the difference memory mapped and peripheral mapped O 99
Or
(Dec. 2005
Compare peripheral I/O and memory mapped I/O.
Or
(May 200
What is the difference between memory mapped and VO mapped I/O ?
Ans. Refer to Section 3.12 Comparison of Memory Mapped and 1/0 Mapped I/O Scheme
Q.3. Why data transfer with DMA is accelerated ?
Ans. Data transfer with DMA is accelerated because DMA scheme of data transfer is commonly used for hiok
data transfer. For example, data transfer between the memory and a floppy disk. A DMA controller is neceePe
the DMA transfer which can allow the peripheral to transfer the data into or from the memory. necessary o
Q.4. Why the number of I/O ports in peripheral mapped 10 is restricted to 256 ?
Ans. In VO addressing mode 8085 has capability of 8-bit I/O address, through which it can address 255 I/O Do
Q.5. Name the two modes used by the DMA processor to transfer data. ports.
Ans. The modes used by the DMA processor to transfer data are
Burst or Block Transfer DMA
Cycle Steal or Single Byte Transfer DMA
Q.7. Discuss the memory mapped /O technique and its use.
Ans. Refer to section 3.11.2
Dec. 2008
Memory Mapped I/O Scheme.
Q.8. What is cycle stealing and block transfer in DMA ?
Ans. Refer tosection 3.14.3. Modes of I/O Data Transfer.
Q.9. Why DMA access is faster method than other methods ?
Ans. In DMA, data is Dec. 20
directly transferred between memory and I/O devices without the intervention of microproCeco
In DMA,
microprocessor gives up the control of address/data bus to I/O devices.
Q. 10. What are the control signal
necessary in the memory mapped IVO
Ans. Refer to section 3.11.2.
Memory Mapped /O Scheme.
Q. 11. Discuss RAM and ROM.
Ans. Refer to section 3.7. RAM and ROM (Dec. 2009
Chips.
Q. 12. Distinguish between primary and secondary
memory.
Ans. Refer to section 3.2.1. A Dec. 2006
Types of Memory Technologies.
Q. 13. What is the various type of semi-conductor
memory.
Ans. Refer to section 3.2.1. Types of Dec. 2006
Memory Technologies.
Q. 14. Why is handshaking required between a CPU and VO
deivces?
Ans. Byhandshaking the status of the I/O device i.e. whether the device is Dec. 206
before the data are transferred. ready or not, is checked by the microprocessr

LONG ANSWER TYPE

Q. 1. QUESTIONS
Using diagram explain how many address lines are
the memory used to identify an /O port in the peripheral I/O and
mapped I/O method.
Ans. Refer to section 3.11 Address (Dec. 2001
Q. 2. Space Partitioning.
Explain the memory mapped I/O mode used in 8085.
May 200
Or
Explain what is memory mapped I/O
Ans. Referto section 3.11.2. scheme.
Q.3. Compare memory and I/O Memory Mapped I/O Scheme.
Ans. Refer to section 3.12.
mapped VO. (Dec. 200
Q. 4. Compare peripheral VO Comparison of Memory Mapped and I/O
Ans. Refer
and
memory-mapped I/O. Mapped VO Scheme.
to section 3.12.
Comparison of Memory Mapped and I/O
Mapped VO Scheme.