UNIT 2: Fault Modeling & Test Pattern
Generation
[Link] (VLSI) - Subject Code: G6806
1. Define a Logic Fault Model. Explain the "Single Stuck-at Fault" model in
Q
detail. (10 Marks)
Answer:
● L ogic Fault Model: An abstract representation of how physical defects (like short
circuits or broken wires) behave as logical errors (0 instead of 1, or vice versa).
● Single Stuck-at Fault (SSF) Model:
○ The Assumption: It assumes that only one line in the entire circuit is faulty at
any given time.
○ Types:
1. Stuck-at-0 (s-a-0): A line is permanently held at logic '0' regardless of
other inputs.
2. Stuck-at-1 (s-a-1): A line is permanently held at logic '1'.
○ Properties: The fault can occur at any primary input, primary output, or internal
gate terminal.
2. Explain Fault Equivalence and Fault Dominance with examples. (12
Q
Marks)
Answer:
These concepts are used for Fault Collapsing, which reduces the number of faults we need to
test.
1. F ault Equivalence: Two faults are equivalent if every test that detects one also detects
the other. Their faulty functions are identical.
○ Example: For an AND gate, all input s-a-0 faults are equivalent to the output
s-a-0 fault.
2. Fault Dominance: Fault F_1 dominates F_2 if every test that detects F_2 also detects
F_1. In this case, we only need to test F_2.
○ Example: For an OR gate, the output s-a-1 fault dominates any input s-a-1 fault.
Q3. Describe the D-Algorithm for test pattern generation. (15 Marks)
Answer:
The D-Algorithm is a complete algorithm for finding a test vector for a specific fault.
● Five-Valued Logic: It uses values 0, 1, X (Unknown), D, and D'.
1. D: Logic 1 in a good circuit, 0 in a faulty one.
2. D': Logic 0 in a good circuit, 1 in a faulty one.
● Three Main Steps:
1. Fault Activation: Assign inputs to the faulty gate to produce a 'D' (discrepancy)
at the fault site.
2. D-Drive (Propagation): Move the 'D' through successive gates until it reaches a
Primary Output.
3. Consistency (Justification): Assign values to the remaining primary inputs to
ensure all internal gate assignments are logically consistent.
4. Explain the PODEM Algorithm. Why is it preferred over the
Q
D-Algorithm? (12 Marks)
Answer:
● P ODEM (Path-Oriented Decision Making): An algorithm that only assigns values to
Primary Inputs (PI) to avoid the complex "consistency checks" of the D-algorithm.
● Process:
1. Select an objective (e.g., set a specific line to 0).
2. Backtrace from that line to a Primary Input to find which input can satisfy the
objective.
3. Assign a value to that PI and check the Implications (how it affects the whole
circuit).
● Advantage: It is much faster for circuits with "Error Correction" logic (like XOR trees)
where the D-algorithm often fails due to excessive backtracking.
5. Write short notes on: (a) Path Sensitization, (b) Boolean Difference
Q
Method. (10 Marks)
Answer:
● P ath Sensitization: A technique where you select a "sensitized path" from the fault site
to the output. All "side inputs" of gates along this path must be set to non-controlling
values (e.g., '1' for AND/NAND, '0' for OR/NOR) so the fault signal can pass through.
● Boolean Difference Method: A mathematical way to find a test. If F is the circuit
function and x is the faulty line, the test is found by solving: $ \frac{dF}{dx} = F(x=0)
\oplus F(x=1) = 1$.
○ This equation identifies the input conditions under which a change in x will cause
a change in the output F.
Q6. Explain Signature Analysis and Transition Count Testing. (10 Marks)
Answer:
● S ignature Analysis: Used in data compression for testing. The output bitstream is
passed through a Linear Feedback Shift Register (LFSR) to create a unique
"Signature." If the signature of the manufactured chip matches the gold standard, it
passes.
● Transition Count Testing: Instead of checking every bit, you simply count the number
of times the output changes from 0 to 1 or 1 to 0. If the count is wrong, a fault is
detected.
Q4. List out the properties of the Boolean difference method. (6 Marks)
Answer:
The Boolean difference (\frac{df}{dx}) is used to find test vectors for faults. Its properties include:
● \frac{df}{dx} = f(x=0) \oplus f(x=1).
● \frac{d\bar{f}}{dx} = \frac{df}{dx} (The difference of a function is equal to the difference of
its complement).
● \frac{d}{dx}[\frac{df}{dy}] = \frac{d}{dy}[\frac{df}{dx}] (Commutative property).
● If f is independent of x, then \frac{df}{dx} = 0.
5. Describe briefly the various DFT (Design for Testability) schemes used in digital
Q
systems. (6 Marks)
Answer:
DFT techniques are added to circuits to make them easier to test.
● A d-hoc Techniques: Adding test points (probes) or using extra gates to improve
controllability and observability.
● Scan-based Design: Connecting internal flip-flops into a shift register (scan chain)
during test mode so internal states can be shifted in and out.
● BIST (Built-In Self-Test): Internal hardware (like LFSRs) generates test patterns and
analyzes responses automatically.
● Boundary Scan: Using a specialized test architecture (JTAG) to test interconnects
between chips on a board.