MODERN COMPUTER

ARCHITECTURE
25ITC01
Unit-3
Fundamentals
PROCESSOR DESIGN AND PIPELINING
• Computer architecture defines how a computer’s components
communicate through electronic signals to perform input,
processing, and output operations.
• It covers the design and organization of the CPU, memory,
storage, and input/output devices.
• Describes how these components interact through buses,
control signals, and data pathways.
• It directly influences the overall speed, functionality, and
reliability of a computer system.
• Basic Computer Structure
• This section introduces the fundamentals of computer organisation and
architecture, explaining system components, design issues, and different
architectural models.
• What is Computer?
• Issues in Computer Design
• Von Neumann Architecture
• Harvard Architecture
• Flynn's Taxonomy
• Number System and Data Representation
• Covers how data, numbers, and characters are represented inside a computer,
along with techniques to ensure accuracy and reliability in storage and
communication.
• Number Systems
• Base Conversions
• Character Representation
• Error Detection and Correction Codes
• Fixed & Floating-Point Formats
• Representing numbers in digital systems using fixed-point and floating-point formats for precision and
range.
• Fixed Point Representation
• Floating Point Representation
• Digital Logic & Circuits
• Designing digital systems using logic gates, Boolean algebra, and combinational/sequential circuits.
• Digital Electronic and Logic Gate
• Boolean Algebra
• Combinational Circuits and Sequential Circuits
• Register Transfer & Micro-Operations
• Managing data movement and operations in registers using bus/memory transfers, arithmetic, and shift
micro-operations.
• Register Transfer Language
• Data Transfers (Bus/Memory)
• Arithmetic Micro-Operations
• Shift Micro-Operations
• Instruction Set Architecture (ISA) & Control Flow
• Defining the set of instructions, formats, and addressing modes for processor communication.
• Instruction Format
• Addressing Modes
• Microarchitecture and Instruction Set Architecture
• Timing and Control
• RISC vs CISC Architectures
• Computer Arithmetic
• Explore all the concepts of computer arithmetic, including ALU operations, number complements,
division algorithms, Booth’s method, overflow handling, and negative number representation.
• ALU and Data Path
• Difference between 1’s complement and 2’s complement
• Restoring Division Algorithm
• Non-Restoring Division
• Booth’s Algorithm
• Overflow in Arithmetic Addition
• Memory Organization
• This section explains memory organization, covering types of
memory, storage hierarchy, addressing methods, virtual memory
techniques, and key architectural differences.
• Memory & Memory Units
• Paging
• Segmentation
• Virtual Memory
• Page Replacement Algorithms
• Translation Lookaside Buffer
• NUMA vs UMA Architectures
• Memory Interleaving
• Byte Addressable & Word Addressable Memory
• Simultaneous vs Hierarchical Access Memory
• Input/Output Organization
• This section covers input/output organization, including interfaces,
interrupts, DMA, peripheral devices, synchronization methods, bus
systems, and processor communication.
• Introduction to I/O Interface
• I/O Interface (Interrupt and DMA Mode)
• Memory mapped I/O and Isolated I/O
• Interrupts
• DMA
• Modes of DMA Transfer
• DMA controller 8257/8237
• Programmable peripheral interface 8255
• Pipelining & Hazards
• This section explains pipelining and parallel processing,
covering ILP, execution stages, hazards, VLIW, branch
prediction, and Amdahl’s law.
• Pipelining Set 1 (Execution, Stages and Throughput)

• Pipelining Set 2 (Dependencies and Data Hazard)

• Instruction Level Parallelism
• Very Long Instruction Word (VLIW) Architecture
• Types and Stalling
• Dependencies and Data Hazard
• Branch Prediction in Pentium
• Amdahl's law and its Proof
MODERN COMPUTER
ARCHITECTURE
25ITC01
Unit-3
Execution of a complete instruction
 Execution of a complete instruction
• The execution of a complete instruction in computer
architecture follows the Fetch-Decode-Execute Cycle, where
the CPU fetches an instruction from memory using the Program
Counter (PC), decodes it to understand the operation, and then
executes it by performing actions like ALU operations, data
transfers (fetching/storing operands), and updating registers, all
orchestrated by the Control Unit to move data between
registers, memory, and the ALU.
 Fetch Phase
• Fetch Phase:The address in the Program Counter (PC) is sent
to the Memory Address Register (MAR).
• A read signal is sent to memory.
• The instruction from that memory location is loaded into
the Memory Data Register (MDR).
• The instruction is then transferred to the Instruction
Register (IR).
• The PC is incremented to point to the next instruction (unless
it's a branch/jump)
 Decode Phase:
• Decode Phase:
• The Control Unit (CU) analyzes the instruction in the IR to determine
the operation (e.g., ADD, MOVE) and the operands involved.
• Execute Phase:
• Operand Fetch (if needed): The CU fetches data (operands) from
registers or memory as specified by the instruction.
• Data Operation: The Arithmetic Logic Unit (ALU) performs the required
operation (e.g., addition, subtraction, logical AND) on the operands.
• Store Result: The result from the ALU is written back to a destination
register or memory location.
• Interrupt Check: An optional check for pending interrupts.
• 3. Operand Fetch
• If the instruction involves external data, the processor fetches the
necessary operands from memory or registers. This step is optional
depending on the instruction type.
• 4. Execute Cycle
• The processor carries out the action specified by the decoded
instruction.
• Data Processing: For arithmetic or logical tasks, the Arithmetic Logic
Unit (ALU) performs the computation (e.g., addition, subtraction,
AND, OR).
• Control/Branching: If the instruction is a jump or branch, the PC is
modified to a new non-sequential address.
• Memory Access: Data may be transferred between the CPU registers
and memory (Load/Store operations).
• 5. Store/Write Back
• The result of the execution phase is saved.
• Register Storage: Most often, the result is stored back into a
CPU register (like the Accumulator).
• Memory Storage: If specified, the result is written back to a
specific memory address.
Key Components Involved
• Component Function
• Control Unit (CU) Directs the flow of data and generates
timing/control signals.
• Arithmetic Logic Unit (ALU) Performs all mathematical and
logical operations.
• Program Counter (PC) Tracks the address of the instruction
being processed.
MODERN COMPUTER
ARCHITECTURE
25ITC01
Unit-3
Single bus organization
 Single bus organization
• In computer architecture, a single bus organization is a design
where all primary components—the CPU, memory, and I/O
devices—communicate through one shared communication
pathway.
System Architecture

• The single bus, often called the system bus, consists of three
functional groups of lines:
• Data Bus: Carries actual data bits bi-directionally between
components.
• Address Bus: A unidirectional bus used by the CPU to specify
memory locations or I/O device addresses.
• Control Bus: Carries synchronization and timing signals, such
as Read/Write commands and interrupts
Internal Processor Organization
• Within the CPU itself, a single internal bus typically connects the
registers, the ALU, and the instruction decoder.
• Sequential Access: Only one component can output data onto
the internal bus at any given clock cycle.
• Register Interface: Temporary registers (like Y and Z) and
multiplexers are used to manage data flow to the ALU, as it
cannot receive two operands simultaneously from a single bus.
• PC Incrementing: To fetch the next instruction, a constant value
(usually 4) is often multiplexed into the ALU to increment the
Program Counter (PC).
Operations and Characteristics
• Bus Arbitration: Since only one transaction can occur at a time,
a bus arbiter is required to manage access when multiple
devices request the bus simultaneously.
• Efficiency: This model is cost-effective and simple to implement,
making it ideal for microcontrollers and embedded systems in
2026.
• Bottlenecks: Because all data, instructions, and addresses
share one path, it creates a performance bottleneck in
high-speed systems.
1. Control Sequence for Memory Read

• Because a single bus can only carry one piece of information at a time, a memory
read operation must be serialized into strict steps:
• Address Placement: The contents of the Program Counter (PC) or a General
Purpose Register (GPR) are gated onto the bus and loaded into the Memory
Address Register (MAR).
• Read Command: The Control Unit (CU) asserts the Read signal on the control
bus.
• Synchronization (WMFC): The CPU enters a Wait for Memory Function Complete
(WMFC) state. This is critical because memory response times are typically slower
than the CPU clock.
• Data Retrieval: Once the memory asserts the MFC signal, the data is placed on
the external data bus and loaded into the Memory Data Register (MDR).
• Internal Transfer: The data is then gated from the MDR onto the internal bus to its
final destination (e.g., Instruction Register or a GPR)
2. Gating Logic and Bus Interfacing
• Components interface with the single bus using specific
electronic "valves" to prevent data collisions:
• Tri-state Buffers: These are used for all register outputs. They
have three states: 0, 1, and High-Impedance (Hi-Z). In the Hi-Z
state, the component is effectively disconnected from the bus,
allowing another component to drive the line without a short
circuit.
• Multiplexers (MUX): While tri-state buffers are standard for long,
shared lines, internal "mux-based" buses are common in 2026
SoC (System on Chip) designs because they are easier to verify
and consume less power than tri-state logic.
3. Bus Arbitration Techniques
• When multiple "masters" (like the CPU and a DMA controller) want to
use the single bus, an arbitration scheme determines who gets
access:
• Daisy Chaining: A simple, low-cost method where a "Bus Grant"
signal is passed serially from one device to the next. The device
closest to the arbiter has the highest priority.
• Polling: The bus controller sends a sequence of device addresses
over the bus. When a requesting device recognizes its address, it
takes control of the bus. This allows for flexible,
software-programmable priorities.
• Independent Request: Each device has its own dedicated "Bus
Request" and "Bus Grant" lines to the controller. This is the fastest
method but requires the most physical wiring
4. Hardware "Constants"

• In single bus organizations, the ALU often needs to perform

common tasks like incrementing the PC (PC + 4). To save bus
cycles, a constant value 4 is often hardwired into one input of a
multiplexer that feeds the ALU. This allows the PC to be
incremented during the same cycle that the current instruction is
being fetched, without needing to fetch the number "4" from
memory.
Course : 25ITC01 – Modern Computer Architecture
Module 3: Processing Unit
Topic : Hardwired control – Micro and Nano
programmed control
CPU
• The control unit is the part of the CPU responsible
for directing operations. It manages the flow of
instructions and data within the processor,
ensuring that tasks are carried out in the correct
order.
There are two main types: hardwired and
microprogrammed.
• Hardwired units: Fast but less flexible (because
they rely on fixed circuits).
• Microprogrammed units: Flexible but slower
(because they use microcode stored in memory).
Hardwired control Unit
• A hardwired control is a method of generating
control signals with the help of Finite State
Machines (FSM). The control signals that are
necessary for instruction execution control in the
• Hardwired Control Unit are generated by specially
built hardware logical circuits, and we can’t change
the signal production mechanism without
physically changing the circuit structure.
Hardwired control Unit
• Fixed logic circuits that correspond directly to the
Boolean expressions are used to generate the
control signals.
• Hardwired control is faster than microprogrammed
control.
• A controller that uses this approach can operate at
high speed.
• RISC architecture is based on the hardwired control
unit
Hardwired control Unit
Micro programmed control
• A control unit whose binary control variables are stored
in memory is known as a microprogrammed control
unit.
• In Microprogrammed Control, the control information
is stored in the control memory and is programmed to
initiate the required sequence of micro-operations.
• By creating a definite collection of signals at each
system clock beat, a controller generates the
instructions to be executed. Each of these output
signals causes a single micro-operation, such as register
transfer. As a result, defined micro-operations that can
be preserved in memory are formed from the sets of
control signals.
Micro programmed control
• Each bit in the microinstruction is connected to a
single control signal. The control signal is active
when its bit is set. The control signal becomes
inactive when it is cleared. The internal control
memory can store a sequence of these
microinstructions.
Micro programmed control
Micro programmed control
Microprogrammed control performs
1.) It can execute any instruction. It should be divided into a sequence of
consecutive operations by the CPU. This set of operations is called
microinstruction. The control signals are required for the sequential
micro-operations to complete.
2.) Control signals saved in the ROM are created to execute the
instructions on the data direction. These control signals can be used to
control the micro-operations associated with a microinstruction at any
time step.
3.) The following microinstruction address is generated.
4.) The last two steps are repeated till all of the microinstructions
associated with the instruction in the set are executed.
The micro counter register generates the address supported by the
control ROM. The micro counter obtains its inputs from a multiplexer
that selects the output of an address ROM, a current address
incrementer, and an address saved in the next address field of the
current microinstruction.
Nano programmed control
• Nano-programmed control is an advanced control unit
design in which microinstructions are further broken down
into nano-instructions for efficient control signal
generation.
• Two-Level Control Memory
It uses two levels of control storage:
• Microprogram Memory – stores microinstructions
• Nanoprogram Memory – stores nano-instructions (actual
control signals)
• The main goal is to reduce the width of microinstructions,
thereby lowering control memory size and hardware cost.
• Nano-programmed control uses a secondary control
memory.
• A microinstruction is in primary control-store memory, it
then has the control signals generated for each
microinstruction using a secondary control store memory
• The output word from the secondary memory is called nano
instruction
Two levels Microprogrammed and
Nano programmed control Units
organisation
Course : 25ITC01 – Modern Computer Architecture
Module 3: Processing Unit
Topic : Pipelining: Basic concepts - Data hazards –
Instruction Hazards
Basic concepts
• Pipelining is a mechanism used to improve system
performance in which tasks are executed in an
overlapping manner. In this technique, the problem
is divided into subproblems & assigned to the
pipes, then the pipes operate under the same
clock.
Basic concepts
• Pipelining is the process of arranging hardware
elements of a CPU such that its overall performance is
increased.
• Simultaneous execution of more than one instruction
takes place in a pipelined processor.
• In pipelining, multiple instructions are overlapped in
execution.
• Accepting new input before the previously accepted
input appears as an output at the other end.
Pipeline Stages

• Instruction Fetch (IF): Retrieves the next

instruction from memory.
• Instruction Decode (ID): Decodes the instruction to
determine required operations.
• Execute (EX): Performs arithmetic or logical
operations.
• Memory Access (MEM): Reads or writes data
from/to memory.
• Writeback (WB): Writes the result back to the
register file.
Pipeline Stages
Pipeline Hazards
• A pipeline hazard is any condition that causes a
pipeline to stall or operate inefficiently, disrupting
the smooth flow of instruction execution. Hazards
reduce overall performance by introducing extra
clock cycles, called 'stalls' or 'bubbles', into the
pipeline.
What is Instruction Pipelining?
• Technique to increase instruction throughput
• Divides instruction execution into stages
• Multiple instructions executed simultaneously

Example: Fetch, Decode, Execute, Memory, Write

Back
What are Instruction Hazards?
• Situations that prevent next instruction from
executing in correct cycle
• Cause pipeline stalls or incorrect execution
• Three main types of hazards
Types of Instruction Hazards
1. Structural Hazards
2. Data Hazards
3. Control Hazards

These affect pipeline efficiency and performance

Structural Hazards
• Occur due to resource conflicts
• Multiple instructions need same hardware
• Example: Single memory for instruction & data

• Solution: Duplicate resources or pipeline scheduling

Data hazards
• A data hazard occurs when instructions exhibit data
dependencies such that one instruction depends on
the result of a previous instruction that has not yet
completed in the pipeline.
• Data hazards occur when instructions in a pipeline
depend on the results of previous instructions. To
ensure smooth execution, various hazard-handling
techniques like forwarding and stalling are
used. provides an in-depth exploration of these
techniques.
Data hazards
Types of data dependencies:
• True Dependency (Read After Write - RAW): A
later instruction needs a value that an earlier
instruction writes.
• Anti-dependency (Write After Read - WAR): A later
instruction writes to a location that an earlier
instruction is reading.
• Output Dependency (Write After Write -
WAW): Two instructions write to the same
destination register or memory location.
Handling Data Hazards
• Forwarding (Data Bypassing): Transfers results
directly from one pipeline stage to another before
they are written to registers.
• Pipeline Interlocks: Detection hardware
automatically inserts stalls until data becomes
available.
• Instruction Scheduling: Compiler rearranges
instructions to reduce dependencies.
Control Hazards
• Occur due to branch or jump instructions
• Next instruction address not known immediately
• Causes wrong instruction fetch

• Solution: Branch prediction, delayed branching

Summary
• Pipelining increases CPU performance
• Instruction hazards reduce efficiency
• Three types: Structural, Data, Control
• Proper handling improves pipeline utilization
MODERN COMPUTER
ARCHITECTURE
25ITC01
Unit-3
Influence on Instruction Sets
Influence on Instruction Sets – Data Path and
Control Considerations
• An Instruction Set Architecture (ISA) acts as an interface
between software and hardware. The design of an instruction
set is strongly influenced by the datapath organization and
control unit design of the processor. Datapath determines how
data moves and is processed, while control determines how and
when operations occur. Efficient ISA design must balance
performance, hardware complexity, and ease of control.
• 1. Influence of Datapath on Instruction Set Design
• 1.1 Register Organization
• Number of registers affects instruction format and execution speed.
• Large register sets (RISC) reduce memory access.
• Small register sets (CISC) increase memory-based instructions.
• Example:
• Load–store architecture restricts ALU operations to registers.
•

• 1.2 Datapath Complexity

• Simple datapath → simple instructions
• Complex datapath → complex instructions
• Influence:
• Single-cycle datapath favors simple instructions
• Multi-cycle datapath allows complex operations
• 1.4 Data Types Supported
• Datapath must support data sizes:
• Integer
• Floating point
• Characters
• Supporting complex data types increases hardware complexity.
•
1.5 Addressing Modes
• Datapath decides how effective address is calculated.
• More addressing modes → complex datapath.
• Examples:
• Immediate
• Direct
• Indirect
• Indexed
• Base + Offset
• 2. Influence of Control Unit on Instruction Set Design
• 2.1 Control Complexity
• Each instruction requires control signals.
• More instruction formats → more control logic.
• Impact:
• Simple instruction sets simplify control logic.
• Complex instructions increase control signal generation.
•

• 2.2 Instruction Encoding

• Fixed-length instructions simplify decoding (RISC).
• Variable-length instructions complicate control (CISC).
• Combined Influence of Datapath and Control on ISA
• Datapath and control together determine:
• Instruction format
• Execution speed
• Hardware cost
• RISC philosophy emphasizes:
• Simple datapath
• Hardwired control
• Load–store instruction sets
• CISC philosophy emphasizes:
• Complex datapath
• Microprogrammed control
• Rich instruction sets
• 2.4 Pipelining Considerations
• Instruction sets must avoid pipeline hazards.
• Regular instruction formats improve pipelining.
• Influence:
• Simple operations per instruction
• Uniform execution stages
• 2.5 Exception and Interrupt Handling
• Instruction set must support:
• Precise interrupts
• Status registers
• Control unit complexity increases with advanced interrupt
handling.
• 5. Advantages of Proper ISA Design
• Improves performance
• Reduces hardware complexity
• Enhances pipelining and parallelism
• Simplifies compiler design
MODERN COMPUTER
ARCHITECTURE
25ITC01
Unit-3
Datapath and control unit
• Introduction
• In computer architecture, the datapath and control unit are the
two fundamental components of the CPU. The datapath
performs data processing operations, while the control unit
directs these operations by generating appropriate control
signals. Effective datapath and control design is essential for
achieving high performance, simplicity, and efficient instruction
execution
• 1.1 Components of the Datapath
• The datapath includes:
• Register file
• Arithmetic Logic Unit (ALU)
• Shifters and multipliers
• Buses and multiplexers
• Memory interface
• The choice and arrangement of these components determine
instruction capabilities.
• 1.2 Register File Design
• Number of registers:
• More registers reduce memory access.
• Fewer registers increase load/store instructions.
• Register access ports:
• Multiple read/write ports enable parallel access.
• Increases datapath complexity and silicon area.
• Example:
RISC processors typically have 32 or more registers to simplify
datapath operations
• 1.3 Datapath Organization
• (a) Single-Bus Datapath
• Only one data transfer at a time
• Low cost, simple design
• Slower execution
• (b) Multi-Bus Datapath
• Parallel data transfers possible
• Higher speed
• Increased hardware complexity
• 1.4 Addressing and Effective Address Computation
• Datapath must support addressing modes such as:
• Immediate
• Direct
• Indirect
• Indexed
• Base + offset
• Complex addressing requires additional ALU operations and
multiplexers.
• 1. Datapath Considerations
• The datapath consists of functional units, registers, buses, and
interconnections that process data.
• 1.1 Functional Units
• Includes ALU, shifters, multipliers, and floating-point units.
• The type and number of functional units influence:
• Instruction execution time
• Parallelism
• Hardware cost
• 1.2 Register File Design
• Number of registers affects instruction count and memory
access.
• Multiple read/write ports improve performance but increase
complexity.
• Large register files are common in RISC architectures.
• 1.3 Datapath Organization
• Single-bus datapath: simple, low cost, slower.
• Multi-bus datapath: faster, supports parallel operations, higher
cost.
• Affects instruction execution and control signal generation.
• 1.4 Operand Flow and Data Movement
• Determines how operands move between registers, memory, and ALU.
• Load–store datapaths restrict memory access to specific instructions,
simplifying control.

• 1.5 Addressing and Memory Access

• Datapath must support effective address calculation.
• Additional hardware required for indexed, base-offset, and indirect
addressing.

• 1.6 Pipelining Support

• Datapath should allow:
• Instruction overlap
• Hazard detection
• Regular datapath stages improve pipeline efficiency.
• 2. Control Considerations
• The control unit generates signals to coordinate datapath
operations.
• 2.1 Control Signal Generation
• Control signals select:
• ALU operation
• Register read/write
• Memory access
• More control signals increase complexity.
• 2.3 Instruction Decoding
• Fixed-length instructions simplify decoding.
• Variable-length instructions require complex decoding logic.

• 2.4 Timing and Sequencing

• Control unit ensures correct sequencing of operations.
• Multi-cycle execution reduces hardware but increases control
complexity.
•
2.5 Interrupt and Exception Handling
• Control unit must:
• Save processor state
• Transfer control to service routines
• Requires precise control signals.
• 2.6 Pipeline Control
• Control logic manages:
• Data hazards
• Control hazards
• Structural hazards
• Forwarding and stalling mechanisms increase complexity.

• 3. Interaction Between Datapath and Control

• Datapath provides capabilities.
• Control unit decides how and when to use them.
• Efficient CPU design requires balance between datapath
simplicity and control flexibility.
MODERN COMPUTER
ARCHITECTURE
25ITC01
Unit-3
Superscalar processor
• Introduction
• A superscalar processor is a CPU architecture that can fetch,
decode, issue, and execute more than one instruction per
clock cycle by exploiting Instruction Level Parallelism (ILP).
Unlike scalar processors that execute only one instruction per
cycle, superscalar processors improve performance by
executing multiple independent instructions simultaneously
using multiple functional units.
• 1. Basic Concept of Superscalar Operation
• Superscalar processors have multiple execution units such
as:
• Integer ALUs
• Floating-point units
• Load/Store units
• Branch units
• The processor dynamically determines which instructions can
be executed in parallel.
• Instructions are issued in parallel within a single CPU core
• Superscalar Processor Architecture (Description)
• A typical superscalar processor includes:
• Instruction Fetch Unit – Fetches multiple instructions per cycle
• Instruction Decode Unit – Decodes instructions in parallel
• Instruction Issue Unit – Selects independent instructions
• Multiple Execution Units – Execute instructions
simultaneously
• Reorder Buffer (ROB) – Ensures correct program order
• Register Renaming Unit – Removes false dependencies
• 4. Instruction Level Parallelism (ILP)
• Superscalar operation relies on ILP, which means:
• Executing independent instructions concurrently
• Limited by data and control dependencies
• Types of Dependencies:
• True dependency (RAW) – Data dependency
• Anti-dependency (WAR)
• Output dependency (WAW)
• Superscalar processors use advanced techniques to overcome
these.
• 5. Instruction Issue Techniques
• 5.1 In-Order Issue Superscalar
• Instructions issued in program order
• Simpler control logic
• Lower performance due to stalls
• 5.2 Out-of-Order Issue Superscalar
• Instructions issued as soon as operands are available
• Higher performance
• Complex control hardware
• 6. Register Renaming
• Eliminates WAR and WAW dependencies
• Uses physical registers instead of architectural registers
• Enables greater parallelism
• Example:
• R1 = R2 + R3
• R1 = R4 + R5
• 7. Dynamic Scheduling
• Instructions are scheduled at runtime
• Uses structures like:
• Reservation stations
• Issue queues
• Improves execution efficiency
• 8. Speculative Execution and Branch Prediction
• 8.1 Branch Prediction
• Predicts the outcome of branch instructions
• Keeps pipeline full
• 8.2 Speculative Execution
• Executes instructions before branch outcome is known
• If prediction is wrong, results are discarded
• 9. Completion and Commit (Reorder Buffer)
• Instructions may complete out of order
• Results are committed in program order
• Ensures precise exceptions
• 10. Performance Factors Affecting Superscalar Operation
• Number of execution units
• Instruction window size
• Accuracy of branch prediction
• Availability of independent instructions
• Compiler optimization
• 11. Advantages of Superscalar Processors
• High instruction throughput
• Better utilization of hardware resources
• Improved performance without increasing clock speed
• Transparent to programmers
• 13. Examples of Superscalar Processors
• Intel Pentium series
• Intel Core processors
• AMD Ryzen processors
• ARM Cortex-A series
MODERN COMPUTER
ARCHITECTURE
25ITC01
Unit-3
Performance Considerations
• Performance Considerations in Computer Architecture
• Performance in computer architecture refers to how efficiently
a computer system executes programs. It is a key design goal
and is influenced by processor design, memory system,
instruction set, and software. Performance considerations
involve analyzing and optimizing execution time, throughput,
and resource utilization while balancing cost and power.
•
•
• 4. Clock Rate Considerations
• Higher clock rate → shorter clock cycle time.
• Limited by:
• Power consumption
• Heat dissipation
• Circuit delays
• Increasing clock rate alone is no longer sufficient for
performance improvement.
• 6. Pipelining and Parallelism
• 6.1 Pipelining
• Divides instruction execution into stages.
• Increases instruction throughput.
• Pipeline hazards:
• Structural hazards
• Data hazards
• Control hazards
• 6.2 Instruction Level Parallelism (ILP)
• Executing multiple instructions simultaneously.
• Achieved using:
• Superscalar processors
• Out-of-order execution
•
• 7.2 Main Memory and Virtual Memory
• Memory latency can dominate execution time.
• Page faults significantly degrade performance.
• 8. Branch Prediction and Speculation
• Branch mispredictions cause pipeline flushes.
• Accurate branch prediction improves:
• CPI
• Pipeline efficiency
• Speculative execution keeps pipelines busy.
•
• 11. Compiler and Software Optimization
• Loop unrolling
• Instruction scheduling
• Register allocation
• Reduces stalls and improves ILP
• Hardware and software must work together for optimal performance.
• 12. Power and Thermal Constraints
• Higher performance often increases power consumption.
• Modern systems balance:
• Performance
• Power efficiency
• Thermal limits
• 13. Cost-Performance Trade-off
• Higher performance increases:
• Hardware cost
• Design complexity
• Designers aim for optimal performance within cost constraints.