11.1 Introduction «A microprocessor is a semiconductor chip that implements the central processor of a computer. The microprocessor works as a brain of a computer. It consists of an arithmetic and logic unit (ALU) and a control unit. «The microprocessors are usually characterised by speed, word length, architecture and instruction set. ie id ie «This central Procesing unit bil ne eG archtoctare of INTE In this chapter we will study features of 8086, detailed architecture of INTEL'S 8086 microprocessor and pin configuration. 11.1.1 ‘Comparison of 8085 and 8086 Q. _ Give Comparison between 8085 and 8086. Size It is an 8 bit Mii ‘Address Bus _ | Its address bus is of 16 bits Tts address bus is of 20 bits Memory Tt can access upto 2'6 = Tt can’ access upto 2° = , 65,536 bytes ie. 64 Kbytes | 1,048,576 bytes ie. 1 MB of of memory memory 4. | Instruction Tt does not have an e has a 6 byte instruction Queue instruction queue. queue | Pipelining | It does not support Tt supports 2 stage pipelined pipelined architecture architecture. 6. Multiprocessor | It does not have Tt supports multiprocessing. Support multiprocessing support. It has compatibility with | ’ further processors like Intel . 80386, 80486 and Pentium. 7. Y/0s It can address 2° = 256 Y/Os. | It can address 28 = 65,536 WOs. 3. | Coprocessor | It does not have coprocessor | It has coprocessor interface. Interface interface. Coprocessor 8087 can be interfaced with 8086. @ | Arithmetic | It only supports integer and | It supports integer, decimal support decimal arithmetic. and ASCH arithmetic.tecture”, Microprocessors & Interfacing (MDU) 14-2 8086 Archit ation | i supports instructions that compute the multiplication and division operation. ee eee 8 MHz 11. | Check speed | It operates on 3 MHz, 5 Tt operates on 5 MHz, MHz or 6 MHz. ie. it or 10 MHz. ie. it operates on operates on low clock speed. | high clock speed. | 12. | Extemal Tt requires less external __| It requires more external \. Hardware _| hardware. hardware. in A Ina a 5 rts two different 13. | Operating tepstts single operating | It veer sles : masz mode and minimum mode. | 14. | Addressing | It supports 5 addressing | It supports the addressing \ modes modes. modes supported by | : microprocessor 8085. It also supports some additional | an addressing modes. 15. [Cost Its cost is low. Its cost is high. | 16. | Multiplexed | It has very fow nmltiplexed - | Tt has number of multiplexed pins pins. pins than 8085. >| 17. | Memory The memory spaces not ‘The memory space is Segmentation | segmented. _| segmented. 18. | Interrupts "| 8085 provides 8 software | 8086 has 256 software vectored interrupts and five | vectored interrupts and 2 hardware interrupts. hardware interrupts. }__[ Aairmemierpts _| hardware interrupts, | 11.2 Features of 8086 ‘The features of a processor can be divided inte es fontures, special features and miscellaneous festure, ""”‘"T®? bread groupe viz. basic 11.2.1 Basic Features of 8086 (1) Ibis a 16-bit processor. This implios that (@) It has a 16-bit ALU that can perform 16-bit operati a (b) Ithas 16-bit registers and intemal data buy” *™Ultancously, | © hae 16 arora data bsing (MOU) & interac? pased on the basis of frequency Of operation, versions 0 eeu = it lines to access memo hence it can acces, + 8096 has 2b 2 = 1MB memory locations e q i W/O devices, hence it can access Ws 6sit address lines nar 2m 64x1K=64 ; — * KWO beating | 11.2.2 Special Features Q Explain how throughput of 8086’ microprocessor is increased. 8086%s pipelined processor +» 8086 can operate in Dama + Sus memory banks + 8086 uses memory semana 1) 8086 is a pipelined processor . : ©» It uses a two stage pipelining ie. Fetch stage that pre-fetches upto yy, — ‘instructions stores them in the queue and Execute stage that exenteg instructions. - ° Pipelining improves the performance of the processor Le. the operatinss faster. 2) 8086 can operate in 2 modes F Minimum mode - A system with only 1 processor ie. 8086. i Maximum mode > A system with 8086 and other processors like 8087. Co-processor), 8089-10 Processor) or multiple 8086 Processors 8086 uses, ‘memory banks ° The 8086 uses a memory banking system ie.’ the entire data is uti! sequentially in a si is divided it banks of ake memory of 1 MB but the memory is divid an ood Lower bank (or even bank, because it stores be! °, 2,4...) & Higher Bank (or odd bank, be \ ions ie. 1, 3, 5...). sot ip cart Pit data can be accessed in a single 0° i ny "P can store only [Link] at a location a 4) 808g Uses ‘ator 00 nr 2 16-bit address in.a register cM wy has 20 address lines. This is malty tion that divides the memory Here the memory: é "Y is divided ona” 7 ONS Coa Sate Dundes 5 aasg nertacng (MDUD 14 8a ae seetianeous Features Ah 23 He FataerU PIS r —t Registers snstruction § -__* _ Datasize for ALU 256 ‘vectored interrupts : There are also non. : ; a hee gre routed to one of ese interrupts. }0 non-vectored interrupts in a 9 es 14, 16-bit registers. a powerful instruction set, that supports multi a . ie ors were not possible in the processors Be de coma als @ rform operations on bit, byte (bit), word (16-bit ora strin data) types of data. ; 1g (block 14.3 8086 Internal Architecture q_Drow ‘ond explain the architecture of 8086. ‘about programming, we need to discuss the special features atu + Before talking internal architecture of Intel 8086. Fig. 11.3.1 shows the block schematic of th internal structure of Intel 8086.| : 115 006 Architecture | a5 Me + Asshown in Fj q | e Fig. 11.3.1, the 8086 CPU is divided into two units viz (a) e! ‘The bus interfacing unit (BI) + The execution unit (BU). : Bee ‘re unis ary ‘completely independent of each other and they share the work : Such a work divisi , Tie isco oa eee ETD Os veg nnd reduces the procesing tim, ‘The work orboes ch is divided between BIU and EU in the following manner. : Sess0rs & Interfacing (MOU) 8086 CPU Bus Interfacing Unit (BIU) Execution Unit (EU) Tasks of BIU are: Tasks of EU are © ‘It-sends out addresses. ‘It tells the BIU, from where to fetch the + Te fetches instructions from memory instruction or data. + Itreads data from memory and ports. «It decodes the fetched instructions. + It also writes data from memory and » It executes the decoded instructions. i ports. : ' * “So BIU takes care of all the address + EU takes care of performing operations and data transfers on the buses. on the data «Hence it is called the extemal world « EU is called as the execution heart of interface of the processor the processor. = Tt works in synchronous with machine + It works in synchronous with T-states cycles 41.4 The Execution Unit (EU) COisin function of EU is decoding and execution of the [Link] order to carry out its tasks it has the following units A ‘Arithmetic Logic Unit (ALU) + Flag Register. + General Purpose Registers. + Control Unit * Decoder Pointer and Index Registers 11.4.1 Arithmetic Logic Unit (ALU) ‘The ALU in the EU is a 16 bit unit ie. it cam perform 16-bit operation } simultaneously. « It is capable of performing, a variety of arithmetic and logic operations such as add, subtract, AND, OR, NOT, EX-OR, increment, decrement, shift ete._—"" 0@0@€0€¢+~0.~+~0~+~0©+~@«..:~—— Microprocessors & Interfacing (MDU) 116 8086 Architecture “41.4.2 Flag Register | Q ain the flag register of 8086 \2- Flag register is a part of EU. It is'a 16-bit register with each bit corresponding to a flipflop. A flag is a flipflop. It indicates some condition produced by the execution of an instruction. For example the zero flag (ZF) will set if the result of execution of an instruction is zero. * Aflag can control certain operations of EU. , Fig. 11.4.1 shows the details of the 16 bit flag register of 8086 CPU. As shown, it f consists of nine active flags out of sixteen | ‘The remaining seven flags marked “U” are undefined flags. 8085 compatible flags BIS 14 13 12 11 10 9 tls sas 10 Cany flag ~ sot by cany out of MSB Partty flag - set if result has even parity | Q-ReRve ‘Aundliary carry flag for BCD os) Zoro flag ~ set it result = 0 > nnder® ‘Sign flag = MSB of result | Trap fag for single stop Interrupt enable flag Direction fag for sting instauction Overtiow flag Fig, 11.4.1 : 8086 flag register format Active flags ‘There are nine active flags out of 16, in the 8086 flag register. The remainin undefined flags. a a“ Control flags ¢ Out of the nine active flags, six are conditi (status) and the remaini | thre ar clad asthe coil a, bets Uny ee wa to contol eertaie& Interfacing (MOU) 1, The trap flag (TF) i Sean reer into single step rang stepping, microprocessor executes a i Used by del for single s tion, B= Trap on, TF = '0'- Trap off 2 The interrupt flag (IF) (i) Clearing IF disables these interrupts. Gii) IF has no effect on either will Le. i i to low addresses, or from right né Gi) DF = 0, the string instruction will automatically increment the par ie. Process string from low addresses to high addresses or from leh ore Conditional (status) fags E * SEcfegs out ofthese nine ‘active fag indicate status ofthe reel pot!” exefution of an instruction Bach fags are called asthe conditional a Fee gtmes of the conditional flage indians wicr condita so Bor example the carry flag (CF) ie eet to ne ii po carry output. ¥ = segntl OF Some of the 8086 i i f the conditions! ° instructions check the status o ‘The six conditional flags are: * The overflow flag (OF)er) be pat ee set when the result has even parity, @ 7 ity is odd, PF is resetted. ci) per is normally used to check for data transmission errors 52 Jo byte has an even numberof Ibits, PF'='0'- low byte has odd parity Z zero flag (ZF) si a is flags set when the result of operation is zero, else it is reset, Oe y -zeroresult, ZF ='0’- non-zero result ‘Tho sign fag SP . {This flag is set, when MSB (most significant bit) of the result is 1. Gi) Inother words it copies the MSB of the result (i) Since negative binary numbers are represented (in the.8086 CPU) using standard two's complement notation, the MSB (copied in sign flag) indicates the number is positive or negative, 4 Gv) SF indicates sign of the result only in case of signed operation (v) Incase of unsigned operation, sign bit has no significance. SF="1’-msb is 1 (negative), SF = 0'- msb is 0 (positive) 4 The auxiliary carry flag (AF) () It is acarry from lower digit to upper digit i) This flag is set, whenever there has been a carry out of the low nibble into the high nibble or a borrow from high nibble into the low nibble of an 8 bit, an even number of 1 bits, & - carry out from bit 3 on addition or borrow into bit 3 on addition = 0’ - no carry out from bit 3 on addition nor borrow into bit 3 on addition The carry flag (CF) i @ Tecan also be called as a final i) This flag is set whenever there has been a carry out of, or a borrow into, the _.. MSB of the result (8 or 16 bit). Ci) The flag is used by the instructions that add and subtract multibyte numbers. om Rotate instructions can also isolate a bit in memory or a register by placing it m the carry flag. ' + there is a carry out from the most significant bit (MSB), & om, ‘0’- no carry out from mab Lg Netflow flag (OF) +Jadicates an overflow from the magnitude to the sign bit of result \Si-Tror is set, an arithmetic overflow has occurred; that is, a significant bit has ee because the size of the result exceeded the capacity of its destination “ G , 7 : 8086 interrupt on overflow instruction is available that will generate an Op TUPt in this situation. Ifresult is not out of range, OF remains reset.peroprocessors & Interfacing (MOU) 11-8 2086 Architecture | fndicated in the table F rence we can say for the following bit structure of data, the flags will be affected as, Dis Du Diy Da Dix Dw Dy Dy Dr Da Ds Ds Ds Ds Di KC) LI ‘Ausiliary carry | Carry from Ds to D, | Carry from D3 to Dy Carry Carry from D; to Ds | Carry from Dis to Dis Overflow Carry from D, to D; | Carry from Dy, to Dis Sign Copy of D; Copy of Dis. 1.4.3 General Purpose Registers plain the. dedicate use of GPR. As shown in Fig. 11.4.1, the execution unit (EU) has four general purpose 16-bit | registers. “ ‘Each one of them can be used for temporary storage of 8 bit data, 16-bit data or | 32-bit data. i] 8-bit Registers - AH, AL, BH, BL, CH, CL, DH, DL. Any of these registers can be used as an 8-bit operand. 16-bit Registers - AX, BX, CX, DX, SI, DI, SP, BP. Any of these registers can be used as a 16-bit operand. 32-bit Registers - DX : AX together can be used for 32-bit operand. ~ ‘These registers can be used for general purpose computing when their other | specialized functions do not interfere. | Can we store 16 bit data words in the general purpose registers 7 | «The answer is yes. We can use certain pairs of the general purpose registers to store 16 bit data words. © Such register pairs are AH and AL, BH and BL, CH and CL, DH and DL. * ‘The above mentioned register pairs are referred to as follows. Jn short, the four general-purpose 16-bit data registers : AX, BX, CX, and DX, each of these is a combination of two 8-bit registers which are separately accessible as AL, BL} CL, DL (the "low" bytes) and AH, BH, CH, and DH (the “high” bytes).086 Architecture’ Microprocessors & Interfacing (MDU) 11-10 eo k— 8 bits —*— 8 bits — " (1byte) °C byte) Seed For example, if AX contains the 16-bit number 1234H, then AL contains ‘AB contains 12H. ie eagle the data re are ly Fi Soe ae be taslon a ringle 16it register or as two S-it registers. ‘Special functions of general purpose registers . seal) alled as "gens Alth the first four registers AX, BX, CX, and DX are : ’ juipae coeh af tee ln doclgned to play a particular role in common use: 1. Register AX Ace: ing special functions eu “4 i) of the operations, such as Multiplication and Division, require that one ¢ ° Cre ee ie vomit ie stored in oi Some other operations, uch as Addition and Subtraction, may be applied to any J of the registers (that is, any of the eight general- and special-purpose registers) ) but are more efficient when working with the accumulator. Gi) It works as a via register for ie_a data is routed through ‘Schuler ths coursed of a For OUT instruction the data in accunmlator (AL for 8-bit data and AX for 16-bit data) can only be given to the output device j For IN instruction the data taken from the input device can be taken only ia | j accumulator (AL for Bit data and AK for 16-bit data) oe (i) ale works as avi register fo sting instructions. Whenever‘ data i it memory or gi " is to be routed through accumulator only "OY ™ €88e of string operation, 8 it is 2 Register BX . ae ister, is the only general-purpose regi which may be used 3. Register CX @ The looping instruction, "number ofiterations —» COOP. LOore,_ <4 yr DU) 0G interfacing jeropr009s80. if fixes REP, REPE, ‘ico aginst with the pre! and Rey, \ wo Te ofthe ating bn “i ‘ aa register ord-size MUL and the "date ith AX for the word-size and DIy used together With tne register AK ie. operand is § size is greater " wt 3 number for the IN and OUT instructiy. : te 0 po only DX can be used as apm hy i ‘of Implicit use of General Purpose Registers DXxis ‘summary Lt die te VO, esting ad deinal/ASCT a ‘Store address information + BX CX. Counter for String operations and |r] Counter for Variable shift and rotate Dx | Word multiply, word divide, Indirect YO 11.4.4. Control Circuitry } ‘The control cireuit is a part of EU. It is used for directing the internal operat | 114.5 A Decoder A 2% “The process of translation from instructions into action is known as decoding +A decoder in the execution unit (SU) is used for translating the instructions from the memory into a series of actions. + The EU will actually carry out these actions. 11.4.6 Pointer and Index Register | * The execution unit also contains the following 16 bit registers. + Base Pointer (BP) register + Stack Pointer (SP) register * Source Index (SD register Destination Index (DI) register : eye ‘These registers can be used as general purpose TG-bit registers. But mst ‘ohold the 16 bit offset of data word in one of the ta as given tn? Base Pointer (BP) register j ‘This is a 16 bit register i evo segment See tho BU. It holds the 16 bit oft relative a But BP 4 fk has a specific use. BP is used wheniaver we pass # parame J The BP regi ogo base addressing moda, 7 ed tf a offset register in the saarossing ————8086 Architecture . wo ?) re utet in the EU. It holds the 16-bit offset address relative to 16-bit 18 # yee at (SS) reBister- f stack segment. i rego rawr i ; st . ,_ SNE, points t0 te 12? tions like PUSH, POP, CALL, RETURN ete. is s * awn ote? ; ot posed for boing the ofet ofa data word in the data segment 5) apt ‘ wares of a oeation in the data segment can be generated ty adding a the ph on to the segment base (16 bit) held by the data segment (DS) register vsti ding the offset in the STregistor toi _ sitios) Regier — > «(2 [0070] 0 + Hardwindo / sosraindex SD riser (ofse0) > + |[1[Fl2/3 mvitohysical address inD.S. > = [2] 1] F213 testnation Index (D1) register Uy Toa rogier ia ned for holding the 16 bit offset ofa data word in the extra segment 5S). ‘The source index (SI) register and destination index (DD register are used for the string related * Forexample if we want to move.a block of data from memory to memory, then source index (SI) : Sammy aye ae to_poit. to_ the sauree — : netiory_address_ani ination _i ig ° = point ——— 16 bits ———> Fig. 11.4.2: Pointer register of EU 11s = The Bus Interfacing Unit (BIU) \ The bus interface uni ‘te flowing, we mk performs all the activities related to Bus. Specifically BIU tenn thE (Pending) from primary memory. (performed over the RW of dat ita * ug)” Perand from/to primary memory. (performed over the system ce oa data fronvto per} to peripheral ports. (performed over the svatem bus) ae : . for memory reference Teuing in an instruction queue.: Microprocessors & Interfacing (MDU) 11-13 In order to carry out its functions BIU has the following modules : | [> Instruction queue. Segment registers ‘An instruction pointer register (IP). + Address generation and bus control. 11.5.1 The Instruction Queue a + The-execution unit is supposed to decode or execute an instruction. Decoding does not require the use of buses, __— jen EU is busy in decoding and executing an instruction, the BIU fetches upto six instruction bytes for the next instructions. ese bytes are called as the prefotched bytes and they are stored in a first-in-first- ' out (FIFO) register set, which is called as a “queue.” 11.5.1(A) Significance of Queue ~ « - To understand the significance of the queue, refer Fig. 11.5.1. Fig: 11.5.1: Significance of queve * As shown in Fig. 115.1, while the EU is busy in decoding the instruction corresponding to memory location 100F0, the BIU fetches the next six instruction bytes from locations 100F 1 to 100F6 numbered as 1 to 6. . ‘These instruction bytes are stored in the 6 byte Queue on the first-in-first-out (FIFO) basis. +" When EU completes the execution of the existing instruction, and becomes ready for the next instruction, it simply reads the instruction bytes in the sequence 1, 2, .... from the Queue. * Thus the Queue will always hold the instruction bytes of the next instructions to be executed by the EU.— , 8086 Architecture. muroprocesors & intertacing (MDW) _tt@________ 11.5.1(B) Pipelining Explain the concept of pipelining in 8086 architecture. ‘The process of fetching the next instruction, when the present instruction is being executed is called as pipelining. * Pipelining has become possible due to the use of queue. TU fills in the queue, until the entire queue $3 full. BIU restarts filling in the queue when atleast two locations of queue are vaocant. 11.5.1(C) Advantage of Pipelining Q. _ What are the advantages of pipelining ? : foe BU always reads the next instruction byte from the queue i BIU. ‘This is much faster than sending out an address to the memory and waiting for the next truction byte to come. In short pipelining eliminates the waiting time of EU and speeds up the processing. ‘The 8086 BIU will not initiate a fetch unless and until there are two empty bytes in its queue. 8086 BIU no: ins two instruction bytes per fetch. Behaviour of queue in JMP and CALL instructions’ If a Jump (IMP) or CALL instruction appears in the main program, then all the existing instruction bytes in the Queue are flushed out and Queue is made empty. a” ‘Then it is reloaded with the new instruction bytes which correspond to the new locations mentioned in the JMP or CALL instructions. A. The refilling of the quoue then continues from the new locations corresponding to the in main program. 3 iy Sethe Bape Peng tea ee bite ene? Because the longest instruction, in the instruction set of 8086 is six byte lon, th ig. Hence Fee ae’ lone queue itis possible to prefetch even the longest instruction in ¢ The queue of 8088 is however 4 byte long. _ 11.5.2 Segment Registers * The code segment (CS) register * ‘The stack segment ¢ The extra segment (ES) register and « (SS) register ‘The data segment (DS) register follows :- All these are 16 bit registers. eT ‘The purpose of using these segment registers and Segmentation can be explained asline in 8086 is 20. the 8086 pry ‘The mumber of dren on of the 1,048,576 or 1 nie maemo is, aarp ntaresting to note thatthe 8086 doos not work he wit But it a memory at any given time, ever it works with b Lo, CUM be ments within the whole 1 Mbyte mena, mi ME, Ce registers actually hold (contain) the Upper 1g Pl ® Shoo othe for masacy segments of 64 k byte each wy; th wy working at that instant of time. i Whig, A word is any two consecutive bytes in memory, Word are stored in mst significant byte at the higher memo me ry address, Tory. sequentially from byte 0000H to byte FFFFH. They bytes “ Pre eee ee 88 A rou of segments defined by thy Dad gn aude op or MT BU A Esch segment is made up of contiguous memory locations. Ip is", separately addressable unit Note that these starting addresses will always be ning They ag Fe een atb leary understood by refering to Fig 1152, wn pe aes mle woe to peton the four 64k ye Postale ne of 8086. There is n: ‘ct p these segments in the memory. ° restriction on the lea They i : "e182: One way Of positioning four 64k byte scent within the 1M bre memory space ofan 808611-16 8086 Architecture or , tayo Ong address or base address of the data nogment is 20000H. The ,__ Noe tat thie, 2000 are londed into the data segment register (DS). pet 16 Rer 16 hts of the starting addresses of the other segments ar stared Sai ding segment registers. into the comeMerlapping usually takes place for small programs which do not need k bytes in each segment. he Oe ancent dijon, partially overlapping or fll overlapping Pe 1159 shows another way of positioning segments within 1 MB memory space of Disjoint segments: Fig 11.53 + Inthe users program there can be many segments. But 8086 can deal with only four of them at any given time, because it has only four segment registers. + Whenever the segment orientation is to be changed, we have to change the base addresses and load the upper 16 bits into the corresponding segment registers. * Each time the CPU needs to generate a memory address, one of the segment _Tegisters is automatically chosen and its contents added to a logical address. v~ Tor an instruction fetch, the code segment register is automatically added to the : logical address to compute the value of the instruction address. ~~ For stack refrencing operations, either data or extra segment register is chosen as the base, The logical address may be made up of different types of values: it can be Simply the immediate data value and a base register plus an index register. 3 the selection of DS or ES register is automatically done, though provisions LZ stag eae eraeon "Thus, any memory location can be addressed without . g the value of the segment base register. {2stem that use 64K or fewer bytes of memory for each memory area (code, stack. the and extra) the segment registers can be initialized to zero at the beginning of Program and then ignored, since zero plus a 16 bit offset yields a 16 bit address.Microprocessor & Interfacing (MOU) 41417 8088 Architectiny | all segments equal and have fully overlapping segments. , . Segment registers are very usofil for Programming tasks that ire isolation of program code from the data cone a fron 9 isolation of module data from the stack | information ete. . csr a of reaan 2 lad sn prpans. ay Caaws the tak of relocating a program (relocation manne ts abling ‘ani the same Program in several different areas of memory without changing addresses in the Program itself. Simply requires moving the program code and then adjusting the code segment register to point to the base of the now code tree . eae ms can be written for the 8086/8088 in which all branches and jumps are relative to the instruction Pointer, it branches and jumps are relative to the ‘struction pointer, it does not matter what value is Kept in the code segment sn th age ht tw ° Every application will defce and use segment diferenty. ‘The curreatys addressable segment override prefix rovides a generous workspace, 64KB bytes for code, 64 Kbytes stack and 1: H 11.5.3 Memory Segmentation * Memory can be thought of as a vast collection of bytes. These bytes need to be organized in some efficient manner in order to be of any use. 11.5.4 Advantages of Segmentation Q_Expldin the advantages of segmentation. The principle of segmentation discussed now has certain benefits. Some of them are as follows : 7” Segmentation provides a powerful memory management mechanism. 2. ‘The segmented structure of 8086 memory space supports discourages huge monolithic programs. ie. Among other things, programmers to partition their programs into modules that operate independently one another. . | . 3. Segments provide a way to easily implement object-oriented programs. _ -— Segments allow two processes to easil . 5 cuss yous eo holier hy oft rene mgnatin low he vuse of 16-bit registers to give an addressing capability rat segmentation, we would require 20-bit registers. In the case se, segmentation let Intel's designers extend the maximum addressable memory 64K to - 6 Segmentation makes it possible to separate the memory areas for stack, code fhe, ts ak 7. Teis possible to or stack y allotting more than one segment for each area. — indent 8. aes makes it possible to write Hon or dynami :Microprocessors & Interfacing (MDU) 11-18 8086 Architecture 11.5.5 Code Segment (CS) uw Code segment (CS) is the part of memory from which the BIU fetches the instruction code bytes. 3 Qt / Tee upper 16 bits of the starting address of code segment are held by the code segment (CS) register. + But the memory address for the base of code segment is 20 bit long. So what about the lower 4-bits ? The answer is that the BIU always inserts zeros for the lowest bits. : wy So if the CS register contents are 3428 H then after adding zeros, the physical starting address of code segment becomes $4280 H. ; * Therefore a segment will always start at an address with zeros ee i stored in 11.5.6 Stack * In Fig. 115.3 we have defined the stack segment from the memory location 50000 H to SFFFF H. 7 The stack is a section of memory which is reserved to store the addresses and data while executing a subroutine program. ee stack segment ( register holds the upper 16 bits of the starting address of stack area. 11.5.7 Instruction Pointer (IP) Register Top of code segment code bytes This location contai | ~ code byla 10 be fetches_ 11-19 £ D soap smn » Miso Ta] 0 -— Marre zero os 2-74] P Bene 20 bit phystoal address roms (3181 Soro be fetched. Fig. 11.53 (b) + ‘Computation ial purpose register in the BIU is the instruction pointer (7p) . * mea earlier the code segment (CS) register holds the upper 1g . so bi atartiag address of the code segment. And code segment is the a “hich the BIJ is currently fetching the instruction code bytes. ister holds the 16 bit address or offset of / ¥ ‘ ion pointer, (IP) regis ee thinthe code segment. This is illustrated in Fig. 11.5.(a). Rules of segmentation £)\ If non-overlapping, there can be 16 segment in all, each of 64RB (, IMB / 64KB = 16) Segments can overlap each other ‘Asegment can begin at any location that is a multiple of 10H | At any given time a maximum of 4 segments and hence 256KB can be accessed ‘The memory of 8086 is a wrap around memory. This means that once the aii | generated crosses the 1MB limit, it accesses the location at the top OOQWH! | eg. if CS = FFFF and IP = 0010. Physical address = CS*10H + IP = 100000H 1 | | om op address lines in 8086 are only 20, so the MSB ‘I’ is discarded and the location _/, secessed is 00000H. atiaife % In an instruction only the offset address in mentioned. The segment registeris* | . oa of the pointer registers. Default segment register adsignments *' | BK Ds SI Ds | SP 58 a are KP ___|ss eee ee Pe ee ee wy t overric i Assiguments "4° PFelix, one can change the above default S66”The . 1@ 8086 ang #086 Miopcesos a | ee but can be \ ES=CS=DS=sS er “ oi ECON 2ERE EE neuen tG ete mgmen a Pe a ald edicor og aaa OOOH PETE 0200 base address D2 offsetaddress 2FAA2 physical address : cite physical address is the address that ie actually sent on the address bus (that is it sot ide). The offset or logic address is the offset from the location zero of a segment, ol js the location pointed ky the base address or the segment: register. ‘Tw consiaer the following examphy: Forextrasegment. c2220H base address ES 2323H BP i C4543H dhysical address forStack segment BF3DOH badgaddress SS 5173H C4s43H Now here we observed that two different logical ad Peint to the same memory address. Asis due to the overlapping of two segments and shod be avoided as here the program (ataand stack data val * lues can be caused to be overwrittenton each other resulting in wrong te. : SS ADVANTAGE OF MEMORY SEGMENTATION vigit 304 may at this find memory segmentation to be slightly complex but as you ihdaae se it 6t section you shall find out about ts advantages. However, here we Sinasiathan sevantages only superficially. The first advantage that memory segmenta- ale agg CTY IG bit registers are required both to the store segment base address a8 well “Ath 20 bite neces Bakes the internal circuitry easier to build as it removes the require- Te cond adh net i case the linear addressing method is used. «Vantage is relocatability. Je in a [Link] system time » ares inteeds ase ility. For example in ing i i f time for programs ‘Werg, ig involves allocating a fixed amount of : i P°erany rer, memory segmentation ie a boon for time shared eee eat bana lodded into memory /'The 8086 can then be made to work on ig ading the segment address of each of these rs. Thus segmentation allows the program to separately \ oe ; physic address . | \ \ \oo simafsang OU) 41-20 8086 Archi pysical Address Generation ect 8 sm understand the generation of 20 bit physical eet which contains the next code byte. ios she soe * _ aiaddress Generation sil : - Gayl THe CS register contains the upper 16 bits of the starting address of the code 8 of the location in nce of operation is as follows. [A ] Segment base ‘The BIU will automatically insert zeros for the lowest four bits of the segment Step 2: i pase address to get the 20 bit physical address for the starting of code segment. : “ Starting address of code segment: [3 |4 |8 | A |0 Jy tL pradas : this zero Step3: The LP. register contains the offset or distance from this address. The offset here is 4214H. «. [Link] : [4 [2 [1 |4 Siep4: Add the starting address of code segment (20 bit) to the ofiet to get the sic addres of the location containing the next code byte as follows : address of code segment > [3]4|8 A]0 « Hardwired Offset in the LP. Register > + 2[1/4 Physical address of the location > [3[8[A[BI# Containing the next code byte Thin physical addrome fe hn sont out by the BU to fetch ee next cole te i Stored at this location. ‘emative way to represent the physical address is as follows ‘ Altemative way of representing a 20 bit physical adaress 7” Segment base | : [ Offset 5s 948A: 4214. * example the 20 bit physical address in the above example is 9484 :Microprocessors & interfacing (MOU) 14.24 9086 Architecture” | What does an offset tell us? | 4 * The offset is a 16 bit hex number contained by the instruction pointer (LP.) register 4 and it tells BIU the location in the code segment, from which the next instruction i byte is to be fetched. 11.6 Pin Diagram of 8086 3 | Supply pins (3 pins) | 7 GND 2.' | Clock related pins (3 pins) CLK 3.__ | Address and Data pins (21 pins) ADo~ ADis 4. | Interrupt pins (2 pins) [me 5. | Other control (3 pins) | TT Mode multiplexed signals 6 Pins) | Horn _ RQ, /@Ty 6 (MIN mode - MAX mode signals) HLDA-RQ, /GT, WR -LOCK_: Meroprocessors Rintefecing(MDU) saz __ 00s Architecture, |. Supply pins (3 pins) 7 - © Used for power supply i.e, +5V on Voo w.r.t. GND, § * Two separate GND pins for two layors of 8086 | chip, improves the noise, ‘ejection. . U, Clock related pins (3 pins) [CLK [ RESET [READY | CLK ‘This pin provides the basic timing for the processor, * 8086 does not has an on-chip clock generator hence ain external clock generator_ * — Itis asymmetric with 38% duty cycle, TTL clock signal. RES} ee causes the processor to immediatel ly terminate its present activity. The 8284 clock generator provides this signal, = + Aris signal nmast bo active high for atloast 4 clock eyeleg 7“t clears all the flag register, the Instruction Queue, the DS, SS, ES and IP registers and sets the bits of CS register. : . [ines the reset: vector addross of 8086 ie FFFFUH (as CS = FFFFH and TP = 0000). (a) Pin configuration14-23 £006, c ' micrprones 1 addressed memo: : yoni scorn ym forslow devices,” UO tha, ‘ canplt te A Toy input batween T2 and 73 of a MC eyela \ wP Pe oR, vP inert wasc-ataonbotwoon T2 and Tg, , / foomes HIGH. Ry b. dsr and data pin (24 pins) mw. oie aie “Apis ADe ‘AiwSs ... Ais/Se | BHEVS; ADw-ADo LA These are time multiplexed data address lines ie. for some time 4, address and for some time data "bay Tt gives the address Avs ~ Ao during T1 of an Machine Cycle. (When ALE. yn fives the data Dis De ater TL of an MIC Cyclo (Machine cycle), i ‘AS... ASe 2 These lines work as Address bus (Ais... Ais) during Tl of every MIC Cycls “y7Meeasas these nes work Status signals So... Se. ves the status of the memory segment currently accessed. 5 the uatasof the Interrupt Enable Flag updated every clock cycle: Se gsi ‘when 8086 controls the shared system bus. S|. Ss| _ Segment accessed 0| 0 | Extra Segment YL 0 | 1] Stack Segment 1]. 0 | Code Segment or None 1] 1 |. Data Segment Bes, Py High wile ** ‘This line carries the BHE signal during T1. THRE and Ao are used together to access a word/byte from the mem?" shown in the banking in section 11.8. me Status line & is reserved for “further development”. 'V. Interrupt pins (2 pins) ¥ ‘This is a non-maskable, i inter iecelvtng an 6 , edge triggered that causes type 2 17" asst Teasiving an interrupt on NMI line, the uP executes INT d ‘o location 2 * 4 =00008H in the Interrupt Vector Table41-24 8086 Architecture is address to get values for IP and CS of the ISR interfacing (MOU) starting from th Je internally by software. ion from LOW to HIGH on this pin, causes the interrupt atthe end of t instruction INTR J . . Thisisa non-vectored, maskable, level triggered interrupt sampled during last for the interrupt the following procedure is followed INTR line, the pP executes 2 INTA pulses. srst INTA pulse > the interrupting device is indicated for its interrupt being « Kirst ered while the device calculates the vectar number. levice sends the vector number to the lock. ‘To get the vector number On receiving an interrupt on Second INTA pulse > the interrupting d microprocessor on the data lines. . Control shifts to location pointed by IP and CS which are loaded from IVT’ at Vector No * 4. V. Other control (3 pins) pm (2 Ibis an active low input line dedicated for 8087 Co-proceseor. In minimum mode it is connected to GND. In Maximum Mode whenever the Co-processor is busy it makes this pin HIGH. TEST input is examined by the WAIT instruction. (If the TEST pin is high, the uP enters idle state; ie, 8087 is free. till TEST pin becomes low N/K . "Rien np ign 8 tat indict he prc a wa SD 27 kin HIGH, 8086 in Mini node Ln. Se prs’ TEEN this signal is LOW, 8086 is in Maximum mode i.e. Multiprocessor system. BD Y Itis an active ‘ YM § low output signal, When it is low 8086 reads from memory oF aMi croprocessors & , ci Interfacing (MDU) tos ao Mi Mode muttipiexed signats HOLD — RQ/GT, * Tn Minimum Mode this line carries the HOLD input signal from another master Tequesting a local bus. : sre DMA Controller ipues the HOLD signal io requestor the eatom bs, “esponee 8086 completes the current bus cycle and releases the system bus, : oe Mode it carries the bi-directional RQo/GT (Request/Grant) * The extemal bus mester (8089 or 8087) sends an activ low pulse to request for the control over the system bus. ‘ i » * 1m response the 8086 completes the current bus eyele, releases the eystem bus and sends an active low Grant pulse on the same line to the external bus controller. , + 8086 gots back the eystem bus only after external bus master sends an active low release pulse on the same line. HLDA—RQJ/GT, + In Minirmm Mode, this line carries the HLDA signal, + This signal is issued by 8086 after releasing the system bus. + In Maximum Mode it functions as RQi/GT: which is the same as"RQ,/GTo; but is of lower priority : WR —~ LOCK + In Mininmm Mode this line carries the WR signal indicates a write operation when this pin is Low. + It is used with M/IO to write to Memory or IO Device. + In Maximum mode it functions as the LOCK output line. 7~When 8086 executes an instruction with the LOCK prefix this signal is active (Le. low) remains active till next instruction, indicating the external bus master cannot take contrvl of the system bus. i aaa = adc” Microprocessors & Interfacing (MDU) 8086 Architecture DEN --- 5, * In Minimum Mode it carries the DEN signal and is usod to enable the Data, transceivers (bidirectional buffer IC 8286), | * In Maximum Mode it carrios th S) signal, Sia a status signal given to 8288. | In Maximum Mode, Bus Controller (IC 8288) gonorates the DEN signal for 8286, | DT/R --- 3; 4 f | * In Minimum Mode it carries the DI/R signal indicating Dita Transmit or Receive. \.2~ This signal goes low for a read operation and high for a write operation. Tn Maximum Mode it carries the 8, signal. 5; is a status signal,given to 8288. . Tn Maximum Mode, Bus controller issues the DT/R signal to 8286.. MIO --- 5; . aad taut Mode it caries the MO signal, to datinguish between Memory and IO access. 1 Mazimim Mode it carriee the 5; signal. 5; is a status signal given to 8288, df rs . | * In Maximum Mode §,, S; and Sp are used to Benorate the appropriate control i signal. . | fe Read 1/0 Port Write 1/0 PortALE In Maximum Mode, Bus Controller 8288 issues the ALE Signa, . . . ty INTA-Q8, sine wony 1127 7 Microprocessors . ey Gs ae oN . it carries the ALE signal, which ; In Minimum Mode it carries is address data line by latching the address. Used ty deny In Maximum Mode it carries the QSp signal, W eae, . i Ibis used with QS; to indicate the Instruction Queue Status } IC- 8282) . j In Minimum Mode it carries the INTA signal. Iti issued in response to an interrupt on the INTR line. Tt is used to read the vector number form the interrupting device, In Maximum Mode it carries the QS, signal. In Maximum Mode, Bus Controller issues the INTA signal. (to 8086) “QS: |'Q8.| Queue Status 0 0 | No Operation wt 0 1 _| First byte of Opcode from queue 1 0 _| Empty the Queue 1 1 _| Subsequent byte from queue Intel 8088 Microprocessor js sec similar to 8086 in many aspects. In this architecture and features of 8088. ilar to that of 8086 but the &!(DU) 11-30 & Interfacing ae 8088 Architecture gn = ve Bt02 and 39 for (086 were ADs to AD\ ‘The Pris is because in BONS there are only 8 d 16 somal in 34 for 8086 was BHE /S, and for g| 8 it is SSy, ‘ for these two changes all\the other ping : sehr ope tions are also the same. 175 Comparison of 8086 and 8088 14.74 ‘The points of differences between 8086 and 8088 are as follows : ' Table 11.7.1 : Comparison of 8086 and 8088 aa whereas for 8 a brs nee, se Pina ae 6 byte 4 byte External data bus 16 bit Shit Function of pin 34 BEE /s, | SS Function of pins 8 to2 and 39 [AD to ADs | Asto Aw 118 Even and Odd Memory Banks for 8086 Q__Exploin organisation of memory in an 8086 system. ’ * We know that the 8086 has a 20-bit address bus, so it can address 2” or 1,048, 576 addresses. Ateach address we can store an 8-bit data (1 byte). Hence the total memory capacity of 8086 is 1M byte. However the data bus of 8086 is 16 bit and the processor is capable of processing 1€ bit data ie. words. The question is how to write a word (16 bit data) into a memory which is segmented ‘0 store the data in the byte form. | The anewer is that a word is written into two consecutive memory addresses. t means the lower is written into the specified memory address say 437A H and the higher rei written into the next higher address as illustrated in Rg 1 81 ae address ? Fig. 11.8.1 : How is a word stored in the 8086 memory *F ‘ ‘8086 Architecture Microprocessors & Interfacing (MDU) 11:31 i i ith one machine cycle, the . order to make it possible to read or write a word wi c wore of 8088 is divided into two “banks” of upto 524, 288 bytes i.e. 500 K bytes each, as shown in Fig. 11.8.2. Upper bank odd Lower bank even addressed byte Fig, 11.8.2 : 8086 memory banks block diagram. + | The two memory banks are known as : 1. Theeven addressed memory bank 2. ‘Theodd addressed memory bank + Theeven addressed memory bank contains all the bytes which have even addresses such 2s 00000, 00002, 00004, ... ete. : ‘The odd addressed memory bank containé all the bytes which have odd addresses such as 00001. 00003, 00005 ete. ee + Theeven addressed bank also called as lower bank and the data lines of this Betti’ are connected to the | ~4: eight data lines ie Dp to D; of 8086 as show Fig. 118.2. : ‘The odd addressed ban‘: is also calved as the upper bek and the data lines off bank are connected to the upper eight data lines i.e. to Dye of 8086 as Fig. 11.8.2. i . ‘The address line Avis used to enable the lower memory bank because Apis connécted, to the CS input of the lower bank. ere Address lines A, through Arp are used for selecting the desired memory devite'ii the bank and to address the desired byte in that device. «tes The address line A, through Arp are also used to select a desired memory device in the upper bank and [Link] address the desired byte in the selected device._—_ Microprocessors & Interfacing (MDU) 14-32 8086 Architecture +. The bus high enable (BHE) is used for ensbling the memory in the upper bank. + BHE is multiplexed out on a single line from 8086 at the same time when an address is sent out. +. The ALE signal is used to strobe in the address into the external latch. The same latch stores the BHE signal as well and holds it stable for the remaining machine cycle. . Table 11.8.1 given below gives the logic levels on the BHE and Ay lines for different types of memory accesses. Table 11.8.1: Signals for the byte and Word operations 0000 | Byte he 1 ‘One [0000 | Wora 0 One = [0001 | Byte 0 [1|_ One Di-Ds : 0001 | Word oO [1] Fret Do- Dy . { + 1 [07 Second —Dis | Case I: Accessing even addressed byte : Fig. 1.8.3(a) shows the process involved in accessizig an even addressed byte. Disabled Fig, 11.8.3(a) : Accessing an even addressed byte * The 8086 forces Ayline LOW and BRE HIGH. * This will enable the lower me: sable the higher me * The 8086 outputs the address of the desired mory bank. address lines A, to Avy. oven, me Mory leation ea the ° ‘The data stored (byte) at the addressed . - Do-Dras shown by the hatched linen Fg ary gestioning the odd 7 , ‘ase II : Access! : involved in accessing an odd ca ig 11.8 sows te poses 209 “eset fe Disat Byte from the addressed odd location Fig, 11.8.3(b) : Accessing an odd byte © The 8086 forces Ap= 1(HIGH) and BHE = 0 (LOW). + This will disable the lower (even) memory bank and enable the ‘upper memory tai ; * The 8086 will output the address of desired odd memory location on A, to Aw aii lines. * The data byte on the addressed odd location appears on the data lines Dy-Ds.« shown in Fig. 11.8.3(b). Case III: Accessing an even addressed word : +. Here the 8086 wants to read a 16 bit word. * As stated earlier, the lower byte of this word is stored first and the higher rt! stored at the next higher. 3 * — Thisis illustrated in Fig. 11.8.9(c). The lower byte of the word has been store! even memory location A and the higher byte of the same word has been store! next location (odd memory location A + 1), 6 Both the memory banks are enabled because 8086 will force Ao as well # low. wt” = a The address on the lines Ap = A, will poi locations A shes ty 19 ~ A; will point towards the——_— I cing (MDU) 134 1 ntertes 2086 ve k ‘ Hag stored * hy a en a Pend a at ” Fig, 11.8.3(¢) : Accessing an even addressed word (uelV: Accessing an odd addressed word : + In this case the 8086 wants to re: ad a word, the lower address. (say A+1) and the uy byte is stored at an odd per byte of the wi ord is at even address Ge. at Bimmediately next to A +1). + Now refer Fig. 11.8.3(d) and notice that the locations (A + 1) and B are not at the same level. ‘Therefore the 8086 cannot use the same address for both these locations, (A+ 1) and B ‘Therefore it is not possible for 8086 Shits of the w to output a single’address and read all the ord simultaneously. ODD BANK EVEN BANK Note: (A+ 1) and B are not at the same level Fig, 11:8.3(4) : Accessing an odd addressed word le is the 808g 16 bit word. One bus cre Rau needs two bus cycles, to read the the contents 0 Taint That the contents of location (A + 1) and other 10 rt ane’ below “MS sequence of operations in theso two bussors & Interfacing (MDU) 11-95 8086 Architecture irst bus cycle : In the first bus cycle, the 8086 forces Ap = 1 (HIGH) and BHE = 0 (LOW) so as to enable the odd bank. It then outputs the address on A, — Avs lines to point at the location (A + 1). The contents of location “ + te will appear on the Dy lata lines Ds to Djs, as shown ‘The lower byte at in Fig. 11.8.3(e). (At thappeare on Dy Ds Fig. 11.8.3(¢) : First bus cycle nd bus cycle : DISABLED ENABLED In the second bus cycle the 8086 forces Ao = 0 (LOW) and BHE = 1 (HIGH) 50 as to enable the lower (even) bank. ° It then' outputs the new address on the A; — Ais lines to point at location B. ‘The contents of location B will appear on Dy ~ D; as LH shown ini Fig. 118.309. ‘The upper byte at B appears on Dp ~ Dy Fig. 11.8.3(0) : Second bus cycle Conclusion : oR ze PS ig Se 2 ‘This can be achieved by using the assembler directive EVEN. ‘The directive EVEN stands for align on even memory address. EVEN : EVEN is an assembler directive which informs the assembler to align the word variables at the even address boundaries 8086 can work in either of the two modes : ' 1, Minimum mode : In this mode 8086 is the only processor in the system. It is also called as uniprocessor mode. 2. Maximum mode : In this mode, multiple processors can be present in the system.Micros sors & Interfacing (MDU) 11-36 8086 Architecture ‘Some common components of 808 1. 8282: Octal latch 3. 8286 : Octal bus transceiver Let us discuss these chips one by one. 11.10 8: 284 : Clock Generator and Driver —— * Before discussing the clock Benerator let us understand the requirements of 4 as far ashe clock input is concerned, L 6/8088 system arg : 8284 : Clock generator and driver 2. 4. 8288: Bus controller Clock” * ° Fig. 1110.1 shows the) durations and voltage le lock signal required by 8086 with all the standard time ls, Fig. 11.10.1 : Clock signal req\ required by 8086 should satis Specifications of clock signal * 7P gommmmcsers Addressing Modes and Instruction Set 42.1 Programmer's Model of 8086 model of 8086 microprocessor. The 8086 programmer's model isa picture of the processor as available to the rogrammer. ‘These ‘are the registers used to hold numbers and addresses, as well as te status and act as . Data Registers (16 bits each for AX, BX, CX and DX) aa pe 7ion Set Microprocessors & Interfacing (MDU) 12.2 ‘Addressing Modes and Instruction © - For 16-bit data registers can be accessed by names AX, BX, CX and DX, ak «Individual bytes of these registers can be accessed hy name, AH, AL, BH, BL, CH, DH and DL. . Address Registers (note : you need both a segment and, an offset to specify an address) a , ini i Jr «The segment register are CS, DS, ES and SS and offset is stored in instruction = = TP or stack pointer SP or base registers BX or BP, or one of the index registers DL \ + The CSIP pair gives the address of the next ingtruction to be executed in the program ‘sequence. { « The SS:SP pair gives the address of the of the stack, a temporary sto! ares often automatically used by the computer. SP is uséd for sequential access of the [time Seimig Mb as stack. ‘The SS:BP pair is used as a pointer into the stack. BP is used for random access of the PER ee Me ener ees stack. r * The DS:SI pair is used as a source pointer and ES : DI pair is used as destination pointer for string instructions. For all other instructions DI register is used with DS segment register. . © The DS:SI and ES:DI regi used as general inters i data processi ——__ . The dotted lines below show common default couplings. . These defaults can be overridden by a notation such as DS:(BPI, where DS will be used in place of default SS. Map soearithe The BX data register not shown is also used as a pointer in th mas ae e data segmenticroproodssors & Interfacing (MOU) = Addressing P Medes ang, Flag Register iad +" ’ pepe [eeded ele ded + ey] MSB of flag register LSB of flag register Fig, 12.1.3: Flag register of 8086 | CF = Carry Out U = Itcanbe Lor [Link] PF = Parity of last operation AF = Auxiliary carry (used iy arithmetic) a ZF = Zero result SF = Sign bit from last operatin TF = Trap Flag- do single instruction IF = Interrupt Enable Flag Direction flag OF = Overflow (error for signed nu oS % " 12.2 Addressing Modes Q. What do you understand by addressirig mode ? Explain different odtress modes with suitable examples for 8086 microprocessor. ‘This will be our first step towards programming. Before we study the insts set, it is necessary to know how 8086 accesses data operands in different ways «+ When 8086 executes an instruction, it performs specifi fanetion on dats T normally referred as operands. Operands may be contained in registers, i instruction itself, in memory or in /O ports. + To access these different types of operands, 8086 has to address mena address of memory and Js can be calculated in several diferent “ie referred as Addressing modes. These addressing modes greatly extend and convenience of the instruction set. it + Gddressing mares (methods) refer to the different methods of a the operands”, ° * We can categorize addressing modes of 8086 as follows : <= + Register addressing mode. Trmmodiate address * Memory addressing modes. © String addressing * VO addressing modes is124 Addressing Modes and Instruction Set ‘String Implied 10 immediate addressing addressing addressi Register sccroeera mode ‘mode mode ae Fig, 12.2.1 : Addressing modes of 8086 12.2.1 Register Addressing Mode + In this mode of addressing, ata i i the miter, and instruction specifies the particular register as shown in Fig. 12.2.2. + This addressing mode is normally preferred because the instructions are compact and 4 fastest executing of all instruction reason why it is fastest executing is just because, all the registers reside on chip, therefore data transfer is within the chip and external bus is not at all required. «Mites Fig, 12.2.2: Register addressing Fema be used as sourve operands, destination 0 eg t may be 8/16 bit. MOV ax, Bx Thi aay 's instruction copies the contents of BX register to AX register. immedi eae ‘ate Operand Addressing Mode ay operand? Rothing but constant data contained in an instMicroprocessors & Interfacing (MOU) 125 Addressing Modes and Instruction Set immediate addressing mode. Fig. 12.2.3 shows format of instruction encoded with immediate operand. Fig. 12.23: Instruction encoded with an immediate operand ‘The immediate data may be 8 bits (byte) or 16 bits (word) in k . + Immediate operand can acceied GUELIF betatse they a’ walable directly in instruction queue, like a register operand. H , there is no need of external bus and bus cycles to obtain the data. . Limitation with immediate operands are, can only be used as source operands and that they are constant values. oo) . Let's take one example : Uv eg. MOV CL,02H MOV CL, 2 Bl —_— tw ‘This instruction copies the immediate number 2H in the CL register. Ey 12.2.3 Memory Addressing Modes +, In previous addressing modes, Execution Unit (EU) was having direct access to register and immediate data (operands). But in this addressing mode, memory operands must be transferred to or from the CPU over the BUS. Whenever EU needs to read or write a memory operand, it must pass an offset value to the BIU. ‘The BIU adds offset to the shifted contents of segment register, which produces 20 bit physical address and after that it executes the bus cycle(s) needed to access the operand, Effective Address * The offeet for a memory operand is called the operand's effective address or EA. « + , It is an unsigned 16 bit number that expresses the operand's distance in bytes from the beginning of the segment in which it resides. In 8086 we have base registers and Index registers. So EU calculates the EA by summing a displacement, the content of base register and the content of index register.LS gw ev Microprocessors & Interfacing (MDU) 126 Addressing Modes and Instruction Set * The fact is that, any combination of these three components may be present in a given instruction gives rise to the variety of 8086/8088 memory addressing me lacement is an 8 or 16 bit number that is contained in the instruction. * The displacement generally is derived from the position of the operand name (variable or label) in the program. It is also possible for a programmer to modify this value or to specify the displacement explicitly. . . + A programmer may specify that either BX or BP is to be used as a base register whose content is to be used in the EA computation. . Similarly either SI or DI may be specified as an index register whereas displacement value is constant. * The contents of base and index registers may change during execution. This makes it Possible for one instruction to access different memory locations as determined by the current values in the base and/or index registers. Tt takes time for EU to calculate a memory operand’s EA. In general the more elements in the calculations, the longer it takes : Finally, once we get EA we can calculate PA (physical address) as, ‘The different memory addressing nodes available are : Register indirect addressing mode. Register relative addressing mode, Based indexed addressing mode. Relative based indexed addressing mode. 12.2.3(A) Direct Memory Addressing Mode In this mode, the 16-bit effective field of the instruction. The physical address ie foe ee segment register * 10 H as shown in the Fig, 12.9. ° e address EA ‘ig 4, ‘The displacement may be 8/16 bit it is stored i sp Seales * in the location which follows theae a/16 bit displacement BE 4 = segment: pe gh = oo eg MOV (10281, AL ‘The contents of AL are 3 3 12.2.3(B) Register Indirect Addressing Mode + In this addressing mode the effective address of the: Memory may by directly from one of the base register or index register, specified by inane This address is added with the segment register * 10 H to genera, physical address as shown in Fig. 12.2.5. . ES) (DL Fig. 12.2.5; Register indirect addressing ™ e pis was SEDI BK then DS is by default segment register Tn this adgntt S88 as by default segment register. aon" that, ssing mode, again programmer can use segment over" é MOVE, (dice eon 138, in gy "'* FAL register are copied to memory location whose ’ crores ale ia te of atneing node is, one instr! Indes register fs ittere™t memory locations if the value # "Hsterie updated apiropreneg interfacing (MDU) 12-8 fe) pased Indexed Addressing Mode pas this addressing mode, the EA is sum of a base rep 7 ’ 7 ter, both of which are specified by the instruction, The ean eae register © 10H to give effective address ax shown in Figo Fig, 12.2.6 : Based indexed addressing mode : BA = {Base register} + (Index register} = {ep} ¥ { ool rae \(BP)) * WN, PA = Segment register : EA = 5 {onl {ool S. Let's see one example, to clear the concept. ‘MOV [BX] [SI], AL _ Copy contents of AL register (byte) to memory location offset is in (BX] [SI ie BX +80), 12.2.3(D) Register Relative Addressing Mode In this addressing mode the effective address is sum of an 8 or 16 bit displacement and the contents of base register or an index register are aide This sum is added with the segment register *10H to generate of addresss as shown in Fig. 12.2.7. Bx 8 bit displacement ga - {BP ,2 ign extended) o 16 bit displacement PA = Sogment: EA CS) (BX) | ' Es| |@P)| |s/6bit = \ps[* | (sb [ * | offset ss) lon .12.2.3(E) Fig, 12.2.7 : Register relative addressing mode e.g. MOV [BX + 1100], AL Copy contents of AL register to a memory locaticn, hose offset is given by BX plu s displacement, from the user, 23140H 1023H 1100H 25263H Contents of DS Offset of BX Offset Physical address + + beginning of the current segment selectd by the The contents of Reg. AL will be transferred at the location whose address is given by 25263 H. Relative Based Indexed Addressing This addressing mode generates an effective register, an index register and a displacement. This is sum is added addrese that is the sum of a base i register *10H to generate effective address as shown in Fig. 12.2.8. ace . 8 bit displacement FA = (Bare reise + Undex register + ee (a) {amen : | remem, EiFig. 12.28 : Let's take one example : : MOV CX, [BX + SI+ 0400) ‘ Move the contents of the memory location offiet by the [Link] EA, in SI plus BX plus displacement from the beginning of the current segment selected by user, to the CX register. «In this case, word is moved not only a byte. Generation of EA Generation of PA 1000H + [BxI 23140H + Ds] The contents of location + 1100H [sp + 2500H + EA | 25640H willbe ° ———— inl transferred to the CL + __0400H_ - Displacement| . 25640H + PA ‘achtee and tea eontanis 2500H + EA of location 25641H will be transferred to the CH reoister. Ex. 12.2.1; IF (6X) = 0158H Displacement = 1B57H (Ol) = 10ASH s) = 2100H and DS is used as segment register, then calculate EA and PA Produced for all various addressing modes. Soin. : 1) Register addressing mode : No EA (data specified in register) 2) Immediate addressing mode : No EA (data specified in i 3) Direct addressing mode EA = Displacement = 1B57H. ++. PA = Segment: offset = DA: EA =DS : displacement = 2100H : 1B57H = 21000H + 1857H = 228578 4) _ Register indirect, assuming BX EA =.(BX) = 0158H ‘ “PAs Segment : offset = PA: BA = DS : (BX) = 2100H : 0158H = 21000H + 0158H = 211598 instruction).12-11 Addressing Modes y ang seca sri NO) 1 MiGtOe i assuming Dl indirect 9 Remeet pA = DD= 10ABH PA = Segment : offset = PA: EA= DS: (D}) = 2100H : 10A5H = 21000H + 10A5H = 22045 i BX eter relative, assuming on EA = (BX) + displacement = 0158H + 1B57H = 1 PA = Segment : offset = PA: BA=DS: (BX)' dg = 2100H : ICAFH = 21000H + 1CAFH = 29 lec Register rélative, assuming ol EA = (DD + displacement = 10A5H + 1B57H = 237¢, PA. = Segment: offset = PA: EA = ES: (DI) + display, = 2100H : 2BFCH = 21000H + 2BFCH = 238FCH 4) Based indexed, assuming register BX and DI EA = (D1) +(BX) = 10A5H + 0158H = 11FDH PA = Segment : offset = PA: EA = DS: [(DD + (BX)) = 2100H:: 11FDH = 21000H + 11FDH = 221FDH 9) Relative based indexed addressing, assuming BX and DI EA = (DI) + (BX) + displacement = 10A5H + 0158H + 1B57H = 2D54H PA = Segment : offset = PA: EA = DS: {D1 + (BX) + displacement] = 2100H : 254 = 21000H + 2D54H = 23D54H 12.24 String Addressing Mode * ing instructions donot use the normal memory addressing mate © ** Trae ite instruction is executed] SI is assured to pont tothe fot orn tins and by default, DS is ascumed segment register. s will point othe fst byte or word ofthe sian acl pie bmn destination string 479 a repeated 9 4 ing operat “ ao rent ya ron, the CPU automaticly adjust he 1 The automatic adj : n O16 £04 achioed by Noe done with the help of DF (Direction Flas) * and RAM bits in instruction format.12-12 Addressing Modes and Instruction Set. ane in 8086 scaly va0d for 108. Under 10 mapping weave: yo We : VO mapped 10. ony mapped v0 , een yo port memory mal mapped, any [Link] memory operand addressing ; Be 10 vod to acoes ne Pe sates ple, 8 ‘a group als can be accessed as an array. String , For s also cal p of tet to tranafor data to memory mapped UO ports ie roi os aro interface. purrs rvs ae mapped 1O mop VO, ten 8086 supports bwo diferent 1 dressing modes + 1) Direct port addressing. Indirect port addressing. Indirect port addressing, the —— is an 8 bit im id. ‘This allows fixed access to numbered 0-255. «Indirect port addressing is similar to register indirect addressing of memory operands. The port number is taken ‘and can range from 0000H to to )-By previously adjusting the contents of — ‘one instruction can access any port in the IO space. jle software loop that . Zp of djacnt ports can be accessed ‘using a simp! adjusts the value in DX. 112.6 Implied Addressing Mode ‘The instructions which do not have operant ee Ca m= eT ieee pak ae Te a instructions do not have operands. 23 y ty instruction Encoding Format 8086, fan 2" have variety in instructions, therefore all instructions will not be c_ ‘ "he instructions pei nituctions vary from 1 to 6 bytes in length. question is, what these bytes till contain & on what perme Aopen ge OF the ini irc Oe peat upon struction bytes is decided ? we oe otis Bate on *r relative Upon addressing mode used by P) _ yea ins » based indexed, oe wd oe PEO) oe bytes will contain information of: fjMicroprocessors & Interfacing (MOU) 12:43 ‘Addressing Modes and Instruction Set 2) Addressing mode designations : a) 2 byte Effective Address. b) or 2 byte displacement. ©) Lor 2 byte immediate operand. ‘To understand more clearly, let's observe Fig. 12.3.1 carefully. 1) Normally first byte is OPCODE byte. 2) 2m! byte normally specifies addressing mode. (Remember MOD and R/M). Sometime it may also contain OPCODE part. 3) After OPCODE and addressing mode bytes, we have following different cases : a) No additional bytes (Figs. 12.3.1(a), (b), (c) and (d)). b) A2 byte BA (for direct addressing mode (Fig. 12.3.1(6)). ©) A Lor2 byte immediate operand (Fig. 12.8.1(f). 4) A 1 or 2 byte displacement followed by 1 or 2 byte immediate operand Fig. 12.3.1). 7 (One - byte instruction — implied operand(s) . ‘ near ‘Repiter to/from memory with no displacement © Bezod| oor Register to/ trom memory with cleplacement [oof neo Geen] no (tt 16-bH caplacemert ie used) Immediato operand to rogletor 0 RH RoE” Ea ay ® (16-0 data are used) Immediate opetand to memory with 18-bi daplacement. ((110-bi data aro used) Fig. 12.3.1: Summary of 8086 instruction format 4) Ifa displacement or immediate operand is 2 bytes long, the low order byte always appears first, this is Intel standard (same was followed by 8085 also). * . To remember these formats, I will give you only a single format, from that we get these different formats refer Fig. 12.3.2.—- Microprocessors & Interfacing (MDU) BYTE1 BYTE2 Register operand / register to 30 In EA calculation Register operand / extension of OPCODE Register mode / memory mode with displacement length Word / byte operation Direction’s to register / direction 's from rogister Operation ( irstruction ) code Fig. 12.3.2 : Instruction format i * As shown in Fig. 12.3.2, the first six bits of a multibyte instruction contains an opcode that identifies the basic instruction type ie. ADD, XOR etc. The following bit, called the D field, generally specifies the direction of the operation. a De 1 means instruction source is specified in REG field. D = 0 means instruction destination is specified in REG field. The next following bit is W. This bit identifies between byte and word operation. * _W = 0 Instruction operates on byte data. = 1 Instruction operates on word data. : ree single bit fields, S, Vand 2. bit . By ating aor pena umber canbe extended to a 16 bit complemant number by letting all ofthe bits in high order byte equal the Mor’ onter isis | referred to as sign extension. “slow onder byte, This i ° § bit is used in conjunction with W to indicate si tan si : arithmetic instructions. SP extension of Immediate fields in | S = ONosign extension = 1 Sign extended 8 bit immediate d its i ‘Therefore for 8 bit operation : $ = W = 0 ne data to Sits if W = 1 15 bit operation with a 16 bit immodiate operand : § « 0 Wel 16 bit operation with a sign extended 8 bit late Gtiereacy ¢ oe operand: $= W = 1 * Used by shift and rotate, to determine single and variable. shifts V = Oshift/rotate count Heit shits and rotate, i is one = 1 shift/rotate count is Specified in CL register,_ -— . -15 processors & Interfacing (MOU) 12. Addressin : Modes ang, Micro et, 4 it with zero flag in conditi 2 ys bit is used as a compare bit wi =e nena Pat ay instructions. Z = 0 Repeat/oop while zero flag is clear, “4, = 1 Repeat/loop while zero flag is set, refer Table 12.91, it summarizes al § bits used in OPCODE fgig Table 12.3.1 : 5 bits used in OPCODE field 7 Ss No sign extensic Sign extend 8-bit immediate data to 16 bita ifw . 1 Ww Instruction operates on byte data Instruction operates on word data Instruction source is specified in REG field Instruction destination is specified in REG field. Shift/rotate count is one Shift/rotate count is specified in CL register Repeat/loop while zero flag is clear Repeat/loop while zero flag is set «Now concentrate on MOD, FM and REG field in 2 byte of instruction format I second byte of the instruction usually identifies the instruction's operands. MOD oo rolrolHolHolno * The mode (MOD) field indicates whether one of the operands is in memory on vii both operands are register. Table 12.3.2 shows MOD field encoding, this fel isds 2 bits. Table 12.3.2 : MOD field ENCODING “| EXPLANATION ~ ie Memory mode, no displacement follows * Memory mode, 8 bit displacement follows Memory mode, 16 bit displacement follows Li Register mode (No displacement) * * Except when WM = 1 =a (oD » 10, then 16 bit displ follows. As seen Mi a / Placement follo we neemed with displacement ie 8bit or 18 biter we displacement. 00 se" © The Reo; . 7 ot, Ee oe field identifies a regiater that is one of the instal? gs” ing upon W bit TW Dit: Table 12.33 shows the select?Addressing Modes and Instruction Set cL 001 010| DL 01i| BL 100| AH | SP 101| CH BP 110| DH sl 111| BH DI all 8 bit registers are selected, whereas for W = 1 all 16 bit registers are - ‘Thus in & number of instructions and mainly in immediate to memory ted. TG is used as an extension of the OPCODE to identify the type of operation ebe or 16 bit. / UM: Register or memory : This field is of 8 bits. ‘The meaning of R/M bits changes Aepending upon mode (MOD) field. : ‘At this stage we have general clear idea about these three fields, now, we will take when W =O, +: Register to register transfer: + In this operation, data movement is ‘within the register either 8 bit or. 16 bit. As aoa erin this operation REG field identifies ONE of the instruction operands What ubout another instruction operand It is specified by F/M, W and MOD bits. Refer Table 12.3.4. Table 12.3.4 : R/M field encoding when MOD = 11 (binary) [MOD < 11 (binary) | RM | W=0|W=l 000| AL AX 001} CL cx 010|-DL DX 011) BL BK 100| AH sp 101| CH BP 110| DH si Yeu wil nd wy 111] Ba { DI an select, ‘at Table 12.3.3 matches with Table 12.3.4. Secondly when W=0, you ONLY 8 bi ONLY 16 bit 8 bit source and destination operand. When W = 1, you can select ‘Source and destination operand.Microprocessors & Interfacing (MOU) 12.47 Addressing Modes and Instruction Set + Following are the example instructions those are not correct or valid : @ MOV AH,CX ; Moving 16 bit to 8 bit (wrong) MOV DX, BL ‘ Moving 8 bit to 16 bit (wrong) Thus any such combination with other register(s) is INVALID: Case II: Memory MODE (8 bit/16 bit or No displacement). « When MOD selects memory mode (MOD = 00 or 01 or 10), then data transfer is register to/from memory. In that case R/M field indicates how the effective address of the memory operand is to be calculated. Now refer Table 12.3.5, it depict EA calculation. [Mob = 10 AX (BX) + (SI) + D8 | (BX) + (SD + D16 x }@x+an+de | 6x) +n +Di6 010 | DL DX | 010 ! (BP) + (SD (GBP) + (SI) + D8 | (BP) + (Sl) +D16 011 BL. BX oul GP) + MD GP) + DI) + D8 | (BP) + DN +D16 100.| AH SP | 100 | (SD (SD + D8 (SD+D1e * “|: 101 | CH BP 101 | OD @1+Ds | @D +Dié 110 | DH sr 110 | DIRECT ADDRESS | (BP) + D8 (BP) +D16 in| sa | pr | 11} @x @XH+D38 | @X)+ Dis. D8=8bit displacement 16 = 16 bit displacement REG field in this case, as,usual identify the register that is one of the instruction operand. 12.4 Segment Override Prefix * Normally for each offset, segment is fixed. But using segment override prefix one can change segment registers.