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Unit 5 Microprocessor

The document discusses Programmable Logic Devices (PLDs) and their advantages over Fixed Logic Devices (FLDs), emphasizing the flexibility and reprogrammability of PLDs. It covers various types of PLDs, including ROM, PLA, PAL, and FPGA, and details their structures and applications in digital logic design. Additionally, it highlights the benefits of using PLDs, such as reduced design cycles, cost efficiency, and the ability to adapt to changing specifications.

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3 views30 pages

Unit 5 Microprocessor

The document discusses Programmable Logic Devices (PLDs) and their advantages over Fixed Logic Devices (FLDs), emphasizing the flexibility and reprogrammability of PLDs. It covers various types of PLDs, including ROM, PLA, PAL, and FPGA, and details their structures and applications in digital logic design. Additionally, it highlights the benefits of using PLDs, such as reduced design cycles, cost efficiency, and the ability to adapt to changing specifications.

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parshant1985bansal
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© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF or read online on Scribd
PROGRAMMABLE LOGIC DEVICES 14, 1061C DEVICES rages are the circuite which perform [I This Chapter, oI si functions. Logic dovices can be Ooo ‘ssified into WO broad categories i.e., "( Fixed logic devices |i Programmable logic devices used Logic Devices (FLD) Devices in which circuits are permanent! fxed. These devices perform one function or Be functionsConce these devices are qufactured, there function cannot be changed) programmable Logic Devices (PLD) (Qevices in which circuits are not permanent and can be changed at any time tnperform any number of functions. ‘Thiscan tedone by using programming Logic Devices ‘Why to go for PLD ‘Structure for PLD Read Only Memory (ROM) ‘Application of ROM 7 Designing of ROM PLA (Programming Logic Array), PAL (Programmable Array Logic) FPGA (Field Programmable \ Gate Array) ‘Complex Programmable Logic Devices (CPLDs) RAM (Random Access Memory) 12. WHY TO GO FOR PLD Incase of fixed logic devices the time required to go from Design © prototype 78 inal manufac: turing run can take from several months to tore than one year and if device doesnot Work properly or if the requirement changes | then a new design must be developed. This Mublem is solved in PLDs. In case of PLD, if a user/customet ‘Biss a mistake im decignideficiency leftout Certain design. Or ‘ 473 474 =~ Digital Logic ang | Ifspecification requirements for a project changes. | recifics Or 1 Ifa user wants to go for another application a user wa Or may be the reason, then user need to erase the Whatever may be the function of y,, PLD and represent a new function. ¢ the reasons why to go for PLDs. Thats why we use PLDs fy aii of combination logic circuits PLDs allow designers mot ppaieg expetinioat 9th Aang (As these ICs can be reprogram” po and this helps in cost reduction also) Definition of PLD CBEDs are ICs with a large number of gates and flip flops that can be configured/Programmed through software to perform a specific logic functie PLD as a Black box a It is shown below: N M Inputs Logic gate 7 apa I i and t gic functions) eee! Programmable switches Fig. 7.1. ne We can implement any combinational logic cireuit with PLD in SOP form which is AND-OR implementation, 7.3. GENERAL STRUCTURE OF PLD (FOR GATE LEVEL DESIGN) As shown in the PLD black box, it has Ninput variables and M output functions In general structure of PLD, ‘NV input variables are represented by input bulfers ‘nverters and ‘Mf output functions are represented by OR array. 'M functions: output lines, 7.4. COMF _——_— Itis repres A py We, able Logic Devices ets ‘Ds consists of three important parts (a) Input buffers and inverter () AND array (@) OR array ySaput Buffers and Inverters Block They are used to provide the true values of the inputs as well as the onpiemented values of the inputs. For ‘NV input variables i. 2, ~ yy this omg will produce 2 N output lines ic, twice of input variables. AND Array Ittakes 2N input variables from input buffers and inverters block and provide product terms of input variables (in both true and complemented formYAND Peay can provide maximum 2 product terms (where Vis the number of input terms) AND array is followed by OR array () OR array COR gates present in the OR array logically sum these product terms and thereby generate an SOP expression\ PLD asa part of a logic circuit resides with other chips on a PCB (ie, printed circuit board). PLD has to be removed from PCB for programming purpose. By placing a socket on PCB makes the removal possible, PLCC (Plastic leaded chip carrier) is most commonly used package. Instead of using a programming unit, it would be easier if a chip could be programmed an PCB itself. This type of programming is known as In system programming. 7.4, COMPACT/SHORTHAND GRAPH APPROACH IN PLD Itis represented as: A A = This indicate true input and is provided by buffer >° J = This indicate inverted input and is provided by inverter Fig. 7.3. => True input = Inverted input, Fig. 7.4. Let us take an example to show compact/shorthand graph approach in PLDs. ! Multiinput AND gate — For this if the output is represent y= ABC DE The shorthand graph approach is given as ie, ar a eb a erm ee a [ok iii Eg — | eS C o | Fig. | | ADVANTAG! | 2 Fig. 7.5. resented as | ’ oat | Here, ‘x’ indicate the fused link and dots indicate permanent fu pppsare those are not Fusible. ctions mg | Sreshe ee Marking ‘x’ on a PLD diagram is a nice way to visualize which fuse (Ose 8 Willy \@) Res ‘ blown on left intact. D erign This function can also be realized by another way. Its shown belay, o Compac i y= ABC DE @ Short d i A B c D E | @ Low de | |@) Low pr | | (8) High 5 7.6. COMBIN | Bo THEIR II | Following tec | Fig. 7.6. (1) ROM (Re | It is prest | Multiinput OR gate | Shorthand representation for multiinput OR gate is shown as below ings | = A+B | a A B A B i It store cannot be | or _ ‘Ttsa St } x 7 y Itis basicall | | Inthis case | Fig. 7.7, | @rrxa a So for fabricating the PLDs, some of A Itis sk i] \e fuses are programmed B fe A509 | achieve the desi to blow out to lesired output from the gate, © —Thputs . For example, if desired ie i 4 output of the gate isCD then fuses A and Bare to be nea Fig. 7.8. Before programm" = 7 ——s 477 “tay ; i A own iD figure. Therefore, with the blowing of f 7, yo ame gate caM SErats several Boolean fuses with proper functions. PP ang Devices De, pie LO ot Sit a B a cob 7 oe ZS reco \¥ ly li i 6 9 TFT > rig. 7.9. After programming (Fuses A & B are blown out) D~, AGES OF PLDS 15 ADVAN - re those devices 19 which large circuit is designed on single chip} Followi neti pee 1008 Which, w Pre advantages: fui seth Reduced space requirements $08 willbe {gj Reduced power requirements bek (@) Design security = (4) Compact circuitry (6) Short desian cycle (6) low development cost \qn Low production cost for large quantity production |(g) High switching speed | 16 COMBINATIONAL CIRCUITS AND |ENTATION. TECHNOLOGIES ual THEIR IMPLEM! .g combinational circuit + Following technologies are used for implementiny (1) ROM (Read only memory) Tt is presented as pao iE below | Fixed AND Inputs——>} Array (decoder) a Fig. 7.10 information. Read only signifies information __Ttstores permanent binary 3 ‘annot be altered. ‘| i itsa SOP logic device with a fixed AN } steizaly combinational zeta sease information is specified by designer and , DP Programmable Logic ArF#y) 1D array and Progra be used toimpleme physically ins It pao? is shown below pag Porammatie | ming Connections hh, —_— Sie SOP logic device with a programmable AND aay array. : = (Programmable Array Logic) 2 tis represented as: progammatie [ proganmabe |__| Frog ND Arr OR an trp Connections | AND Array ll ae Fig. 7.12. Itis a SOP logic device with a programmable AND ey ana i int ir a OLDs can be programmed according to the Boolean functions, The. fol SI table shows the programmable array for various devices, iy Devices Type And Array OR Array Fixed logic Fixed Fixed devices (Not programmable) ROM Fixed Programmable PLDs } PAL Programmable Fixed a PLA Programmable Programmable ‘The adv READ ONLY MEMORY (ROM) fq) Es is @ De tis _eml in. (8) It ction pattern. ROM contains special intern \@ c or broken. Once a pattern is established for a ROM it remainé ifthe an Pomer supply to the circuit is switched off and then sfiehed on again. Puen 5 * prod funetions >> en the functic : rn — i “a Programmable[ Tw This re buffer ; or ~ for a funct inverters i ‘ammay: = functions | —_] Le allel from theix ome Fig. 7.13. Block diagram of ROM, ; minte input variables, calen ne and m output lines. Each bit combination 0 77.1. Des anal ei © input variable. Fach e number of input variables are given as (2") = @2) = @)*. ‘The input is jen av 6 line: i er cone Fie. 14 the block consisting of AND array with buffers/inverters is mat to a decoder. ThE conoder basically is a combinational eizeuit which ‘yr number of minterms fromm ieamnber of input lines, 2" or p numbers revnterms 2° vealized from ” numbers of input variables with help of ‘bers of buffers, 7 numbers of inverters and 9" numbers of AND gates. Each ‘ ug is applied 10 the impute of ™ number of OR gates through sale links. The lorie ‘diagram for ROM is given aS to . decoder moutput lines Fig. 7.14. ‘The advantages of using ROM as a programmable logic device are: (1) Base of design since no simplification or minimization of logic fupetion is required. \ (@) Design can be changed, modified rapidly. WW () Itis usually faster than discrete SSI/MSI circuit. (4) Cost is reduced. Demierit of ROM ‘The ROM implementation of function may become quite expensive for functions with a large number of, ‘variables because all potential ene of the functions are implemented whether or nott they are needed. Ttis removed by using ‘PLA which requires that only the minterms fequired for a function can be implemented and ‘allows the implementations 0} several functions simultaneously. ‘Moreover the functions can be implemented directly from their minterms forms (although st is often possible to eliminate) some of thersinterme, further deoreasing the cost of the PLA). 17.1. Designing of Circuit Using ROM EXAMPLE 7.1. Design the following function using ROM F, (A,B, = Es 158.6 nD F, (A,B, ©) =¥ (1s 5» 8) | Sélution: In order to design these function’ by using ROM, we need to decide the type of Decoder. ROM is @ ‘combination of Decoder ‘and OR gates. Two functions are present and hence we med two OR gates. Only three inputs A, B, — od Digital Logic ang Dey mnce decoder needed is 3: 8. . Hen of ROM is 8 x 2 which means “2 OR gates ang i i nd 3 input variables. 480 =— Cis present ‘The representat means 8 address lines a! and het ‘The designing is given ** follows : ee % | a, A L — 8 * 2 i \ aM? | golutio The dec Fy Fe froth ta Fig. 7.15. EXAMPLE 7.2. Design the square of three bits numbers using ROM. Solution: The three bit number has range from 0 to 7 and hence maximum square value is 49 which is represented by 6 bits and hence the output consists of 5-OR gate (as ‘e’ donot require any 1 at output ). The decoder used is 3 to 8. ‘The truth table representation is given as follows [Decimal | Input variable Decimal Output variables | No. No. | 1 Ee No. obec de f| : 0 0 0 0 0 0 0 0 0 0 i cosine oe 1 0 0 0001 : aries 4 0 0 0 1 0 2| i Dt lene 9 De ose ste 0-4 o 0 16 O-t 0" Oo 0 5 1 0 1 | 6 1 4 a 25 o 1 10 0 1} 7 hey 36 1 00100 49 1 10 001 j Output for a, b, c,d, e, fis given as : a= Em 6,7) b=Em (4,5, 7) c= Em (3, 5) Whe d=Em (2,6) bs ee eee sto toa Deviens ies ll i = No minterm feEm (1, 3,5,7) aD rae d @ (GND) Fig. 7.16. (PLE 7.3. Design the circuit for Half Adder using ROM. Solution: For Half Adder, two outputs °° present, two OR gates are required. e decoder used in 2:4 which states that it has two inputs i.e. Aand B. The Th ih table for Half-Adder is given 88 = Input Varible A B ‘The designing of the given cireuit is by using 4% 2ROM ‘S= Em (1, 2) C=Em 3) |__ Mo M, - 24 s Decoder Mz Ms s c \ ‘Fig. 7.17. i where § denote sum output and C denotes carry output. 2421 Code using ROM. EXAMPLE 7.4. Design a BCD to _——ie men aby 10x 4 ROM whi Peto tion: It is represented by 10 where 10 is thy Solutis Tt can be designed by 4 : 16 decoder ang art N ‘OR tas js the output lines. le is given as follows : truth tabl Decimal BCD Code 2a Baie es 1 Caap ee ae c D P 9 a Pity AND i = . a > ; ee | with array if ; 1 0 0 0 1 0 oo ateaed v0 For 2 0 0 1 0 0 ° Hn neirammona 3 0 0 i 1 0 9 ue pe 4 0 1 0 0 0 1 1% 3 0 1 0 1 1 one 6 0 1 1 0 taleog Let | 1 0 1 1 1 2 Bie |etm = gota got, . to feds 8] tos 9 1 0 0 1 wt a at | ae ‘The output expression for P, Q, R, Sis given as . P=5m (5,6, 7,8, 9) Q= Em (4, 6, 7, 8, 9) ‘ R=Im (2, 3,5,8,9) a al S= Em (1, 3, 5, 7,9) terms and * The designing is given as follows : mumber of | n denot ee rt p denot 1d m deno pe my Acomp Lb ~ in number My implement A i, i are than 48 pr M of 48 prod: " ROM is ne y —_ there is a a] Sdeae M T reducing - Decoder Mg a uncomple: al M, Broviding ae eth Tae), Soe us _ Folloy welt] {_——— f Qa | fe Ma [ | ex My { ( / @)I a7 INT OI peunaepehee | =e a a 1 (pROGRAMMING LOGIC ARRAY) 9 proere jexible device in the family of PLDs. The Le ace reform thet of the ROM, The decoder of the ROMs ion of ‘array that perform product terms of the input wavibles: The followed by an OR array which OR’s together the product terms fom output functions, Both the AND and OR arrays = 9 jected 1 ie giving a lot of flexibility for implementing logic design, a Programmable AND and OR gate 1 ° 1 : AND oR Output : Array Array lines 0 1 . —+ Product terms Fig, 7.19. Logic diagram of PLA. The size of a PLA is specified by the number of inputs, the number of product terms and the number of outputs. ‘The number of sum terms is equal to the umber of outputs. It is denoted as n X p Xm PLA where | n denotes number of inputs p denotes number of product terms m denotes the number of output terms. ‘Acomparison between ROM and PLA can be made to show how reduction in number of gates is possible in PLA. Consider a typical example of implementation of a combinational circuit of 16 inputs, 8 outputs and no more than 48 product terms. ‘A 16x 48x 8 PLA can serve the purpose which consists of 48 product terms. To implement the same ‘combinational circuit, a 21° x 8 ROM is needed which consists of 21° = 65536 minterms oF product terms. So there is a drastic reduction in number of AND gates with in the chip, thus reducing the fabrication time and cost. In PLA both complemented and. " ie., 2" number of inputs appear at each ‘AND gates ty in product term generation. uncomplemented inp providing maximum Advantage of PLA Following are the advantages of PLA: f (1) As both AND and OR array are programmable. It | for implementing logic design. | @) Efficient in terms of area needed for implem: | @<2%. (8) It is included as a part of larger chips such as microprocessors. (4) Power requirement is less than ROM (as less product terms P< 2). (6) Fabrication time decreases as number OfAND gates drastically reduces (as compared to ROM). (6) Cost is also less (as hardware reduces as compart Bag gives as lotof flexibility entation on a IC chip e to ROM) 434.8 PLA jsadvantage of t In ROM based design, since all minterms are generated, He, ca cat boolean function isbased on minterms, Tis not neggqan® Srpressions prior to realization with ROM, my tone | Yot in PLA based design product terms generated arengt ng | minterms. There is always & specific limit on use of AND gates ang Peat miptain a set of reduced expression in a way that number of cant doesnot exceed the number of AND gates in PLA. Hence, simplinct tog poolean function is needed. fication sl | 7.8.1. Designing Using PLA In case of ROM based design, since all the minterms are | ROM, the realization of a set of Boolean functions is based on minted a expressions. Itis never necessary to minimize the expressions prior the realization with a ROM. On the other hand, in case of PLA, a iting terms generated are not necessarily the minterms, as these projet depend upon the how the fuses are programmed. As a consequence _ using PLA is based on the SOP expressions. It is necessary te Cee mn supers expressions in such a way that number of product terms does not exces number of AND gates in the PLA. Therefore, simplificati the ate lification of Boolean fun, EXAMPLE 7.5. Design the following function using PLA. F, (A,B, C)=Em (1, 4) \ F, (A, B, C) = Em (0, 2, 5) Solution: i lution: In order to realize the output functions F, and F, solve the Kup n Solution: For Fy For F mnable Logic Devices ae ar ee Tl —— ——* 485 LT Af Foo Fe Fig. 7.20. 7.6. Solve the given functions using PLA Fy= Em (0,1, 4,6) F, = &m (2, 3, 4, 6, 7) | Fy = Em (2,8, 5,67) solution: Solve the K-map for the Foy Fy, Fy Fs For Fy? a Cae beer bia ND Digita, Loge Se oy, For F,: ‘ For F;: B F,=AC+B In order to design these function 5 AND and 4 OR gates are required, in A B Cc / HAR yp ++—[) yyy Fo Fy Fe Fa Fig. 7.21. ing PLA. EXAMPLE 7.7. Design the circuit of Half Subtractor using P Solution: The truth table for half subtractor is given as : a B D (Difference) B, (Borrow) iM 0 0 ° 1 1 1 : 0 1 0 é i 0 0 D=AB+AB Losic | e ert in eae ive’ qe From. AND arra of AND ga moutput Advanta | \ @ It 2) It | Disaays —tis Bates ay EXamy Sotutic 8nd the sei DEES B,= AB ae equations required tw severed ct © AND gate an oer = gate and 2 OR gates Fig. 7.22. 19 PBE{EROGRAMMABLE ARRAY LOGIC) | ee apecial case of PLA which has a programmable AND arra may. Ibis chea) compared to PLA as only the AND array is ae " omiyo easy t0 program a PAL compared to PLA as only AND must be *Jgamped- on the other hand, Since the OR array is fixed, it is less flexible | than PLA device. equired, , r eae ‘AND : Array : on progarmabl ; aray 2 juct ? yutput ee {| mau terms tines. } A input lines Fig. 7.23. Block diagram of PAL. «sn input lines which are passed through ducing'P’ product terms. Outputs From the block diagram, it has js fixed connection and producing AND array which is programmable array Pr

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