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Unit 3 Microprocessor

The document provides an overview of 80x86 assembly language programming, detailing the structure of assembly instructions, including labels, mnemonics, operands, and comments. It describes various data transfer instructions and their formats, emphasizing the ease of assembly language compared to machine language. Additionally, it outlines the instruction set of the 8086/8088 processors, categorizing instructions into groups based on their functionality.

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2 views65 pages

Unit 3 Microprocessor

The document provides an overview of 80x86 assembly language programming, detailing the structure of assembly instructions, including labels, mnemonics, operands, and comments. It describes various data transfer instructions and their formats, emphasizing the ease of assembly language compared to machine language. Additionally, it outlines the instruction set of the 8086/8088 processors, categorizing instructions into groups based on their functionality.

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parshant1985bansal
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© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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80x86 INSTRUCTIONS 3.4 INTRODUCTION © ‘The machine language program code isthe only code that can be executed by the processor. The assembly language code fone ofthe most primitive forms, in which program can be coded. The assembly language code ‘has to be processed by the assembler to generate machine language code. There are two types of statements in ~ assembly language. First, the instructions, which are translated to the machine code by the assembler, and “Fecond, the directives, which direet the assembler during the assembly process for which no machine code is generated, . Assembly language programming is much easier than mischine language programming, An instruction in the assembly language is represented by character strings called mnemonics (eg. ADD, SUB, JMP, ete.). The ‘80x86 processor provides an exhaustive set of instructions to support assembly language programming to perform input, pevessing, and output operations known as the Instruction Set. \ Te sect of x6 procera ced no he twigs nena romps, Instructions 3.2. ASSEMBLER INSTRUCTION FORMAT ‘The general format of an assembly language instruction Is : Label: Mnemonic Operand, Operand + Comment: ‘where each part of the instruction is separated by space(s) and every instruction stati on a new line. A label followed by a colon (: )is an identifier that is assigned the address of the first byte of the instruction at the point of occurrence. The use of a label with the instruction is optional. If it is present, the Iubel name can be used in 1s branch instruction to branch to the labeled instruction. If label is not present, then colon (: ) should not to be used, Mnemonic indicates the operation to be performed on the specified operands, The number of operands ‘that can be specified in an instruction depends on the type of instruction. Instructions can operate on an implicit (Zero), one, two, oF three operands. If there are two or more operands, they should be separated by ‘comma (,). The comment field i for commenting the program which generally describes the logical operations performed by the instruction. A comment must start with the character semicolon ( ;)..The comment field is oe ‘optional and is completely ignored by the assembler. as Example: Erm 200 AX, AMOUNT 1 Add MOOT to the regiater AX 1 write code aa required by the program 46 Microprocessor x86 Programming In the above statements, the symbol NEXTNUM isa label, AMOUNT: isa vasiable;end-eymbols ADD and LooP are mnemonics of he instructions. All the information followed by the character aemicolon() ar the comments. Assembler generates machine code for only ADD and LOOP instructions including the instructions within the Toop. ‘ Following are the conventions used in describing the instructions. Convention Meaning sre source dest ‘destination reg register thm ‘egister or a memory location - rial 6 16 bit register or a word memory location icumed 16 ‘aumediate 16 bit umber, addr address of a memory location. a reg ‘Poitregisier ¥ regl6 U6-bie register sre8 source of type 8-bit \ srel6 source of type 16-bit Fa meml6 16-bit memory location ‘ MoD ‘modulus of a remainder © logical NOT operation & logical AND operation . 1 logical OR operation « logical EX-OR (exclusive OR) operation € assignment operation * ‘not equal . é al 3.3. DATA TRANSFER INSTRUCTIONS Ve) ‘The 40x46 processor supports 1 variety of instructions for transfer of data immediate value, or addresses } int registers, memory location, or ports. The manner ia which the operand are desigaated inthe data move, ment instruction, depends onthe addressing modes and canbe in any one of the following forma, a an be a register or a memory tie Gaye een oe emery on lh sane smut Data transfer instructions do not affect the CPU flags. The XCHG, PUSH, POP, IN, OUT , etc, are described inte lo et er asrons such s MOY, Examples: Mov AX, Cx # copy contents of cx to AX Wov AH, AL ov wov wov Mov mov sopy contents of AL to AH Ds, ax i Copy contents of aX to DS AX, 1008 copy immediate value 100H to ax + Copy 16-bit-data from the 3 ax, (S30BK) 3 memory location s20sy 1 to BX register _ i DL, (ax) of memory location pointes itored in BX,to DL BP, 5S i Copy Contents of $5 to BP Exchange thé contents of the source and destination “dest €> “sre ‘Note:The symbol AMOUNT. used in the explanation of the following examples in this chapter is considered. 35 m2 uray of type word with size 100 as follows. AMOUNT DM 100 dup(o) Examples: . XCHG AX, Cx XeKG Ay, aor (Bx) XGH AX, awouNT Bx) XCHG BL, AK X61 smopHORE, ox 4 exchange SEMAPHORE vith BX ER fi ae register is always used as the segment D oe the next instruction to be executed. 6" “Hn computing the > for stack Pol el the segment register. 4 ition ES is by default ) Forstring by segrrent register eP dstnaton oer ‘he instruction set of 8086/8088 is divided into number of groups, of functionall instructions. , “a pent groupe ATe + Bitmanipulation group. String instruction group. « Program transfer instruction group. Process control instruction group. Graphical presentation of different groups is as shown. Arithmetic vse ont ‘dditon Subtraction oe Division] ee esto instructions Logical ae | Rotate Iteration eee Unconditional Conditonal Mer — Input ‘so atin ot Now reenter fom he Penk ‘higg ot e Wil start with instruction set, The informa Frraton gen: ’ nr the assembly language programmer. THe 3 Abortion (Syntax of the instruction) 4 Perat Baamplen of the instruction i F - | Metoprocessors g Intertacing (Mou) 1219 Addressing Modes and Instruction Set YOU above informers ‘ bels are used. I feel SMP oul ow tm ap oe TE ace ae and meaning of those labels. : 12.6 Data Transfer Group ‘The 14 data ‘ransfer instructions are listed as follows : i : ay Exchange byte or word Translate byte are flag contents and for loading one subgroup and study each instruction one Oo . ie OV a ee — Destination = Source OF wt ing mod node Register addressing mode P - cqae MOV instruction copies, © word or a byte of data from a Fxed/specified destination. operon * xed/specified source toa samples ‘ov St, AL ‘This instruction copies MW eyo 3, AL memory location whose offset is stored in SI register. The contents of memory location ‘Temp_result will be the IP will NOVAK, ‘Temp Result transferred/copied to the AL register. Tien f location after AMOVAK, BK register. The LSB of BX ie. BL is copied 4MOV COUNT (DN,2DH This instruction copies 1 ie MOVCOUNT [DI,2DH required memory Treation. EA of the memory location yo the sum of displacement COUNT and the contents of DI Following table contains valid souree and destination operands ‘Addressing Modes and Instruction Set sation, Source Flags No flags are affected. the contents of the AL register to and contents 0) copied to the AH register. the contents of BX register to AX ied to AL and MSB increment by 1 ‘Temp_Result will be ‘This instruction copies OFBX ie. BH is copied to AH. immediate number 2DH to the (BA=COUNT+ DD Gr. No. | Destination Source L Memory ‘Accumulator: 2. | Accumulator | Memory. 3. ‘Register ‘Register 4. __| Register ‘Memory 5. Memory, Register. 6.__| Register Immediate 7] Memory __| tamediate 3 | Seg Reg _| Reg = 36 9. | Seg—Reg__ | Mem— 16 10, | Reg— 16 Seg - Reg T. [Memory | See= B88 — r : : | Microproces icroprocessors & Interfacing (MOU) 42-24 Addressing Modes and Instruction Set Vg Following rules are observed while executing the instruction (@ oe ‘The Source & Destination MOV [1100], (1200) | , sence wT — root | scan Location? || ' The Destination in MOV 592FH, BX | an Instruction CANNOT | Immediate Nur ie] umber | . ‘The Destination in MOV 592FH, CS mn instuoton CANHCIT be Incorrect t Segment Register CS => em | j sss ef ‘The Source & Destination must both be of BL eat aN yy met tt Svch acta anetr ie not posto because BLie# Bt ates an | I CANNOT copy value of one segment : MOV DS, CS fi Register to another segment Register incorrect fen j (One should copy to general register rst => am cate MOV CS, 5487H i Inoomect t 4 It CANNOT copy Immediate value to INCANNOT sat the value of CS & IP Registers | | Fig. 12.6.1 Mnemonic PUSH Source Algorithm SP=SP-2 | SS : [SP] (Top of the Stack) = Operand | j Addr. Mode Register addressing mode : Operation SP-+SP-2 SS -+ data from specified source ' «This instruction decrements the stack pointer by 2 and copies a word froma | specified source to the location in the stack segment where stack pointer points. | The source of operand (16 bit data to be stored on stack) can be a general purpose | register, flag register, segment register or memory. | Microprocessors & Interfacing (MDU) 12-22 Addressing Modes dnd Instruction Set * The stack segment register and stack pointer must be initialised before using this instruction. . crearyatn be used to save data on the stack so that it will not be destroyed by a execution of successive instructions. Example PUSH AK Now we will see detailed analysis of what exactly happens when instruction PUSH AK executes. . PUSH AK SP+sSP-2 SS -+ Copy word from AX register to location in Stack segment (SS) where SP points, Mnemonic POP Destination OR POP Operand Flags No flags are affected Algorithm . Operand = SS: [SP] (top of stack) SP=SP+2 Addr. Mode Register Addressing mode Operation SS — Data copied to destination oroperand .._ SS SS: [SP + 2] | * This instruction copies a word (two successive memory location contents) from stack . Segment in' memory to a destination specified in the instruction. * The destination can be a general purpose register, flag register, a segment register or a memory location. * The data in the stack pointer is not changed. * After the word is copied to specified destination the stack pointer is automatically incremented by 2 to point to next word on stack. Example = POP AX This instruction copies a word (two successive memory’ location contents) from stack segment in memory to the AX register. 7 Mnemonic XCHG destination, source. Flags No flags are affected Algorithm destination = source Addr. Mode. ‘Implied addressing niode Operation _ destination, ¢+ source This instruction exchanges the contents of.a register with contents of gnother ” register or the contents of a register with contents of memory location, “The nigister can be 8/16 Bites = : “e~ KCHG cannot directly exchange the tntents of two memory locations, +, Seg XCHG 5068) ; This franetaci not pet Dass 48 6 eguiree jind destination ‘maasp b be wouds or th must be bytes. eee {CHG AX; BK, PAKS BX, eect te : at « me ay ee wee Ph gGe wat oo Z Microprocessors & Interfacing (MDU) 12-23 is i ion will in AX register with the wo +. > + This instruction will exchange the word in Wording * - Contents of AL «> Contents of BL, Contents Of AH <> Contents of ‘BE Rng, ey, i XLAT/XLATB 1B indicates | Flags No fi, Mnemonic operation) (meaning of XLAT snd “8? are XLATB is same, either XLAT XLATB can be written) AL=Ds: (BX + unsigned AL] Addr. Mode Implied Addressing mode Operation AL «pg: (BX + AL} ‘This instruction replaces a byte in AL the memory. ie. it copies the value of AU tothe AL register. Algorithm register with a byte from a look rey hr etn De Pa Here contents of AL before execution acts as index to the desired location in lookap table. This instruction is used to translate a byte from one code to another code, © Most sis oon is used to convert BCD to mene EDCBIC code con: Segment code or Wversion ‘Sat 12.6.2 Input/Output Mnemonic IN accumulator, port address, Flags No flags are affecte Algorithm © _ Addr. Mode Direct port addressing mode Operation Ax « Contents of port. or AL « contents of port. ‘This instruction will copy data from a port whose address is given in the instruction AX register or AL regisine ‘The data i Addressing Modes and Instruction Set address is specified directly in the instruction. The port ite. 8 bit address is directly specified. Thus addressing rt, the port to FF Ly addressing The above example is an example of direct port ~ % § 3 aah 3 a ins ye port IN instruction, the port address is loaded into the DX register pre Vaiale Pov. Since DX i 016 bit register, the por address can be any ce IN ist nd FFFPHL Therefore its possible to address up to 65, 596 patsin is mode a : DX/OFFOH ; Initialize DX to point to port. IN Al, DX; Input an 8 bit data from port OFFO to AL ie. contents of port OFFO are tied othe AL register. The addressing mode is Indirect port addressing mode . or wordt 8 port Mnemonic OUT port address, Accumulator. Flags No flags are affected Aigorithm = — ‘Addr. Mode Indirect port addressing mode € Operation Contents of AK -> Port address / Contents of AL -» port address. Tislnsiruction copies a byte from AL or a word from AX to the specified port. Example © MOV DX, FFF8H OUTDX, AL load desired port address in DX. Cries contents of AL to given port address in register DX . * Ithas two possible forms. ware port + Variable port wanted port form, the B bit port address is specified directly in the instruction oe cua any one of 256 possible ports can be addressed. dre 3B H, AL ; copies the contents of AL. to port $B H. * Inthe arr ‘mode is Direct port addressing mode. Areas inl port form th ontnt of AL AX wl OP rt ne suisined in DK. The DK register should be loaded with the desired port above example in table is an example of indirect port addressing. - Microprocessors & Interfacing (MDU) - 42:25 ‘Addressing Modes and Instruction Set 12.6.3 Address Object (6 \ ‘These instructions manipulate the addresses of the variables, rathe + than the contents or values of the variables. These are mainly used for list processing, based variables and string operation. Mnemonic LEA register , source. Flags _ No flags are affected Algorithm — REG = Address of memory (offset) Addr. Mode ' Register Direct Addressing Operation REG « source. : + This instruction determines the offset of variables or memory location named as source and puts the offset in the indicated 16 bit register. + Generally this instruction is replaced by MOV when assembling is possible. + Normally the offset is loaded into index register or base pointer registers such as SI, DI, BX, BP. ‘ Example | LEAAX,COUNT This instruction loads AX with the offset of COUNT in DS. (Load Register and DS with words from memory) Mnemonic LDS register , source. Flags No flags are affected Algorithm REG = First word,’ DS = Second word [Link] — Register Direct Addressing. Operation REG «Source, DS « (Source +2) * The source is always a_memory location. DS is used as a segment register for memory. - . This instruction is a2 byte instruction. It copies a word from two memory locations into register specified in the instruction. ‘fe then copios a work Enm the next two memory locations into the DS register. _—— Microprocessors & Interfacing (MDU) 3 Less bad pe (Load register and ES with words from the memory) Mnemonic LES register , source. Flags _No flags are affected Algorithm REG = First word, ES = Second word Addr. Mode Register Direct Addressing Operation © REG« Source, ES ¢ (source + 2) + The source is always a memory location. L . Thin a2 bye intron Tapes word fom twa memory lstions in specified in the instruction. If then copies a word from next-two-memary locations ings the ES regen 12.6.4 Flag Instructions (Flag Transfer) ‘These instructions are related to movement of flag register to/from a register and memory. (Copy lower byte of flag register to AH) ' Mnemonic LAHF Flags No flags are affected Algorithm AH = flag register’s lower byte Addr, Mode Implied Addressing mode tion AH ¢ Lower byte of flag register ‘The lower byte of 8086 flag register i copied tothe AE regs ita = ~ ij ‘ (Copy content: _ Mnemonic SAHF contents of AH to lower byte of flag registir) All . » Fl Mgorithm AH = fag register gs All the flags are changed. Microprocessors & Interfacing (MOU) Addr. Mode Implied Addressing mode Operation AH > Lower byte of flag register + This instruction copies the contents of AH regi + Ttiincluded for 8085 compatibility * The OF, DF, IF and TP are not affected, Mnemonic PUSH i Flags No Algorithm: SP. gp_ mre SS: ISP| (top of stack) = operand Addr. Mode Register Addressing mode Operation SP sp_2 " SS data from flag Tegister, 77 his instruction decrements the stack po; : ‘ulster to the memory location Dotted by stack pga PS word % © The stack Segment register ig Rot affected. ; Mnemonic opp Addr. Mode Register Addressing tinode Operation sig, Copy data to fag register SP=SP42 ‘Addressing Modes and Instruction Set oss 0) ‘Table 12.7.1: Arithmetic instructions Te Multiplicat MUL | Multiply byte or word unsigned MUL | Multiply byte or word signed AAM_ | Integer multiply byte or word ASCII adjust for multiply is Division DIV _ | Divide byte or word unsigned pte or word with borrow | | IDIV | Integer divide byte or word gc | Decrement byte or word by 1 AAD | ASCII adjust for division NEG Negate byte or word CBW | Convert byte to word (@'s complement) CWD. | Convert word to doubleword CoP | Compare byte or word 3 AAS | ASCII adjust for subtraction DAS | Decimal adjust for subtraction We will study the subgroups one by one. 127.4 Addition or word p> a gworwerd A TT 06 Frerement byte or word EY 1 B ‘Subtract byte or word 8 | Subtract + ADD destination, source * destination = destination + source - ee Gestination) + (source) Ti srt ae number fom eu t number fom destination 7 specified destination. ing Modes and Instruction Set @ 12-29 Addressit Both the operands lt soil > ADL Ai), Source and a Mnemonic —_ ADC destination, source. Flags All flags are affected. Algorithm destination = destination + source + CY Addr. Mode Register Immediate addressing mode: Operation _ destination « destination + source +'CY * This instructions adds destination operand contents, source operand contents and carry flag and answer is stored back to destination operand. ‘The source and destination can be 8/16 bit register or memory location . The source and destination can also be a 8/16 bit register or memory location and immediate . data. . «The segment registers cannot be used . The memory uses DS as segment register . ‘The addition of two memory locations along with carry is not possible . Itis easy to perform multiple- precision arithmetic by using ADC instruction. Examples 1, ADC AL, BL_ © This instruction adds the contents of AL register with ie. AL« AL+BL+CY BL register and contents of CY. . AL +BL+ CY __ 2. ADD BL, CL © This instruction adds the data in register CL and BL. BL+ BL+CL ‘The result is stored in BL register. It can be 8 bit/ 16 bit ~ instruction 3. ADD AX ,'[2048) © This instruction adds the data at memory locations ie AX AX 4 contents of Whose offset in DS are (2048) and (2049 with data in AK memoryless register. The result is stored in the AK register. Microprocessors & Interfacing (MDU) 12:30 Addressing Modes and Instruction Set 4. ADD [2048], AX + This instruction adds the data at memory locations = . whose offset in DS are [2048] and (2049) with data in AL. register and AH register. 5. ADD AL, 74H * This instruction adds the immediate number 74 H with “Ye AL AL +74 the contents of AL register . The result is stored in AL; Mnemonic INC Destination Flags ~All the flags except carry flag are affected. Algorithm destination = destination + 1 Addr. Mode Implied addressing mode Operation destination « destination + 1 * This instruction adds 1 to the destination operand. * The operand may be a byte or word and is treated as an unsigned binary number. * The destination operand may be a register or meinory location. Example = INCCX Add 1 to contents of CK INCAL Ad 1 to contents of AL register. Mnemonic AAA Flags AF and CF flags are changed, while OF PF, SF, ZF are left Lome, Algorithm — Iflowernibble of AL >9orAF=1 then: AL = AL46 AH=AH+1 AF=1 CFe1 else: AF=0,CF=0 ; In both cases, clear the higher nibble of AL, Addr. Mode Implied addressing mode Operation + Numerical data coming into a computer from a terminal thro Keyboard is usually in ASCU code. ‘The numbers 0 tod ae represented by ASCII codes 30 H to H. The 8086 allows to add the ASCII codes for two decimal digits without masking off “3” in the by itruction ii make sure that the result is the correct: ‘unpacked BCD. eel * The AAA instruction works only on AL register. © Ifthe lower nibble of AL register after addition is greater Stet and increment AH by 1 The aur carry fag and care fe are set. Microprocessors & Interfacing (MOU) i281 Addressing Modes 204 ing ; tg le Assume . AL=00110101. ASCHS BL=00111001 ASCH9 ‘ ADD AL, BL + oo nloo ren ofe 1 1 = 1 oo os Result of 0 addition Ww ttltg AAA 0000 0100 a Clear higher’ nibble ° mw rlon 0 0 1 1 orlno (04H) > Result in AL valid Bop, (01 H) - Result in AH. Th stored in AH register ° cay i Mnemonic DAA Flags It changes AF, CF, PF, ZF and SF. Algorithm — If lower nibble of AL > 9 or AF = 1 then, AL= AL +06H, AF=1 IfAL > 9F Hor CF =1 then, AL= AL+60H,CF=1 Addr. Mode Implied addressing mode Operation AL + Sumin adjusted to packed BCD format * This instruction is used to make Sure that the result of adding two packed BCD ‘numbers is adjusted to be a valid BCD number. It operates only on AL register. * TFaumber in the lower nibble of AL register after addition is greater than 9r ifthe auxiliary carry flag is set add 6, Tf'the lower nibble of AL. is greater than or if the carry flag is set then add 60. 12-32 i tac (MOU) Addressing Modes and |nstructig n 59 Hvalid BOD, BL=34H valid pop ADDALBL 0 101 a wpAb= loo, +0014 109 1000 119, UY 8 D AL=8DH invalid BCD after addition’ of AL and BL 1101 +0000 0110 +0000 110 DAA ooh 0 0 10 1001 0011 ST fe 3 3 + AL = 93H BCD 127.2 Subtraction truction Set Microprocessors & Interfacing (MOU) 12:33 Addressing Modes and inst : Ean affected are AF, CF, iad Mnemonic SUB destination, source feos On Pn Sr and ZF. Algorithm destination = destination — source Addr. Mode — Operation , destination « destination - source ‘nation and : * This instruction subtracts a number from souree with number from destination an Puts result in destination location : * Both the operands ice. source and destination, cannot be memory locations. Examples ‘ 1. SUB BL, CL ‘This instruction subtracts the contents of CL register from ‘ BL+ BL-CL BL and result is stored in BL 2. SUB AX, [2048] AX « AX ~ contents of memory location. * This instruction subtracts the data-at memory locations Hs whose offset in DS are (2048) and [2049] with data in AX register. + The result is stored in the AX register. 4 3. SUB (2048), AX (2048) <- (2048) - AL, [2049] « [2049] - AH * This instruction subtracts the data at memory locations whose offset in DS are [2048] and [2049] with data in AL register and AH register. * The result is stored at memory locations whose offset in DS are (2048) and [2049] i.e. (25188 H and 25189 H). 4. SUB COST, 14H. + ‘This instruction will subtract the immediate Data 14 H COST«COST-14H with contents of memory location COST whose offect is (Cost : is a memory given in the instruction [ie. memory location 28354 F] location] + Result of subtraction is stored at COST. 5. SUBAL, 24H * This instruction subtracts the immediate number 24 H AL «© AL - 24 Jish the contents of AL register. The result is stored in ‘The type of both the operands should match i byte or word. Register | Register “Register Memory Memory Register ‘Accumulator | Immediate Register | Immediate ‘Memory | Immediate ——- Microprocessors & Interfacing (MDU) 12:34 Addressing Modes and Instruction Set Mnemonic —_SBB destination, source Flags SF flag is not affected. Algorithm —_ Destination = destination — source - CY [Link] Register addressing mode. Operation —_ Destination ~ source - CY + This instruction subtracts source and carry flag (i.e. Borrow) from destination. * The source and destination can be 8/16 bit register or memory location . The source and destination can also be a 8/16 bit register or memory location and immediate data. ‘The segment registers cannot be used . The memory uses DS as segment register . ‘The result is stored in destination. : Both the source and destination may be words or bytes. ‘They can be signed or unsigned binary numbers. It can be used to write routines that subtract the numbers longer than 16 bits ie. double words quad words etc. Example ‘SBB AL, BL AL «+ AL-BL-CY * This instruction subtracts contents of BL and CY from AL, © The result is stored in AL. “Mnemonic DEC destination Flags Algorithm destination = destination - 1 Addr. Mode Register Addressing mode Operation destination <- destination - 1 * This instruction subtracts 1 from the destination word or hyte. * The destination can be a register or a memory location. * This instruction cannot be used to decrement the Contents of segment registers, Example DECAL AL=AL-1 © This instruction subtracts 1 from the contents of CL CF is not affected and result is stored in CL, Mnemonic. AAS It updates AF, CF but OF PF SF ond ZF are left undefined,” Algorithm Tf lower nibble of AL > 9 or AF = 1 then; 7 AL=AL-O6H = AH=AH-1 0 AFe1 ply else AF=0 CF=0 In both cases clear the high nibble of AL Addr. Mode Implied addressing mode Microprocessors & Imeraang (MUU) fone Tre roan ee Sere PTESERd a8 39. Operation + The 8086 allows us to subtract the cadena digits without masking “3” in UPPEr nibble of each, 7 bm * The AAS instruction is to unpacked BCD form, Te works only on the AL register. Tet BL= 0011 0101 = 35 H = ascH 5 SUP AL BH Result ANS |=] 9 CF=0no Mnemonic ~ Das, Flags The OF is undefnes Algorithm lower nibble of AL> 9 gp AP = 1 then AL=AL~O6H apiy crn, EOF = then AL AL 05 OP =1 Addr. Mode Tmplied Addressing mode Operation « dn ome AL tel pasted 30D tema This instruction re pc tt 0 Sacked BCD venta mie that the result is correct BOD. The result of subtraction mente ‘AS to work correctly, . Tra Rtn wos only on AL regia, . Peon tenn rr ett A en Oe ten SMH i Vithe ih PB i i thay oe “struction wll subtmnet H from the AL register Example AL= 1000 0110 « 86 B AL= 0010 1111 = 2F H, CF=0. rot BH= 0101 0111-57 pop nibble of result is F H, ie Fe AL, 110 t0 8 Bit so DAS aubrcs 0000 Dag AL = 0010 1001-29 H make sure that ‘yy the “ey ay Example Let AL= 0011 1001 = 39H = Ascrtg Flags All flags are affected rand and add 1 to inverted operand ° Je fi 4 ye 9008 resin FS ; an replaces the number is a destination with 2s it on ‘Toi ement 0 ote “a oe t Fastination COP an be a register OF memory location. + The stration rms the 2' complement by subtracting the original : me or byte the indicated 4 destination from zero. 1s ‘efi f0F changing the sign of a signed ed word or byte. . satempt 10 3 te a byte com! ontaining — or a word containing «92, 1 causes no change © to the operand d and sets Overflow flag. pce Bocompl ement of umber in AX. p92 Suppose ou 1010 0011 ot it’s 28 wl 000 10100011 = att 1 1011100 + Y’s complement of 00A3 H + 4 Tait 1111 0101 sist « 2s complement of number = FFB contents of AX after execution 7. CMP = ‘Compare byte ‘or word lunonie CMP destination, source. Flags AF, OF, SF, ZF and PF, CF are updated ‘according to the result Le Destination - source hee Register addressing mode n+ This instruction compares rte from source ¥ ith byteAword from destination. The comp’ jone by seine the source . byte or word from the destination byte or-wol a result is not stored in either of the destination or ed ‘The | . ‘and source remain unchan , only 1e source may be register, location or a a number. P memory loca’ Sou: ce > destination Source - [0] ~do00 0100 - Result of subtraction Cany fag [7] 1111 1011 < 2% complement of the result ie. result of ‘comparison of BH and opetand tn Flags (i) AF, PF, SF, ZF are undefined. Gi) CF and OF will both be 0. ‘When operand is a byte AX = AL * operand When operand is aword (DX: AX) = AX * operand Register addressing mode ‘This instruction. multiplies an unsigned byte from source with an ‘ ‘unsigned byte in the AL register er an unsigned word from source with an unsigned word in AK. ; : © When a byte is multiplied by contents of AL, the result is stored in AX. The MSB of result is stored in AH register and the LSB of result is stored in the AL register. When a word is multiplied by contents of AK, the product can be . double word . The MSB of multiplication is stored in DX and LSB in AX register. : «The source can be a register or memory location. — | Microy | Example MUL CX | Mnemonic | Algorithm Addr. Mode Operation Example IMUL BL processors & Interfacing (MOU) 12-38 Addressing Modes and Instruction Set This instruction cannot be used to multiply immediate data. If we want to multiply immediate data. Then that immediate data has to be stored into some valid register and then multiplied with byte or [Link] AL or AX DX:AX =CX * AX : Result of multiplication MSB will be stored in DX register and the LSB will be stored in AX register. TMUL source Flags AF, PF, SF and ZF are undefined. When operand is a byte -> AX = AL * operand When operand is a word -> (DS : AX) = AX * operand Register Addressing mode Byte operands > AX « AL * source Word operands -» (DS : AX) < AK * source * * This instruction multiplies a signed byte from some source and a signed byte in AL, or a signed word from'some source and a signed word in AK. . ‘The source can be register or memory location. . When a signed byte is multiplied by AL-a signed result will be put in AX. When a signed word is multiplied by AX, the MSB 16-bits are put in DX and LSB 16-bits are put in AK. If the magnitude of product does not require all bits of the destination, the unused bits are filled with copies of the sign bit . To multiply a signed byte by a signed word it is necessary to move signed byte into lower byte of word and fill the upper byte of word with copies of sign bit. This can be done by CBW instruction. If the: upper byte of 16 bit result or upper word of 32 bit result contains only copies of sign bit (all (’s or‘all 1's) then the CF and-OF will both be zeros. + If the upper byte of 16 bit result or upper word of 32 bit resull : It contains part of the product then the CF and OF will both be zeros. Let AL = 69 decimal = 0100 0101 = 45H BL = 14 decimal = 00001110 = 0EH IMUL BL 45H + Contents of AL register x _OEH _ « Contents of BL register O3CEH «Result of multiplication AX = OSCE H MSB = 0, Positive result magnitude in true form. 1 SF=0,CPsOF=1 AAM Flags It updates Pr, gp Mnemonic and OF are left unde The AP oy Algorithm AH = Quotient of AL/10 AL = remainder of AL/I0 Addr. Mode — Implied addressing mode mn + Numerical data coming into a computer from a is Operatio keyboard is usually in ASC code, The mur a ag represented by ASCII codes 30 H to 39 H. * Before multiplying two ASCI digits, the upper nibble bite g hood to be masked. This loaves unpacked BCD i each byte the two unpacked BCD digits are multiply the AAM insta Twente edt of wo unpacked BCD igs Tt works only on register AL. ,. *,_Ttisused after multiplying the two tnpacked BoD Example "Let AL—+ 0000 0101 = unpacked BCD $ BH - 0000 1001 = unpacked BCD 9 MUL BH: AL® BH Result in AX rogieter AX = 00000000 oo161i01 = o02D # AM AK : 0000 0100 0000 0101 = 0405 H Which is unpacked BCD for 45. 12.7.4 Division Instruction Bog numbers Flags All flags are undefined . sal Let AX = 37D7H = 14,296 decimal BH = 97 H = 151 decimal ‘Addressing Modes and instruction Set = remainder (Modulus) Ax=@8: AX) /operand (Quotient) emonie DIV source Agorither ‘When operand is byte: ‘AL = AXJoperand ‘Aut = remainder (modulus) When operand is @ word : DS= remainder (modulus) AX=@X:A0/ operand tz, Mode Register Addressing mode Operation Byte division : (DS : AX)/ source AL « quotient o! Att w vemainder of DS: AX)/ SoU? DX ¢ remainder of DS : AX)/ source This instruction performs two operation : 4 Divide a signed word by a signed byte Nagy, % Det astnt wpe word by iene we oe word divided by # single byte a AK = 03 ABH pL = 00 D3 IV BL Quotient in AL= BCH — Resainder!* ag-27B Microproc nSepronessor& Intertcing (MOU) 1241 ddrensng Modes and Instruction Bet amcor ine Flags (i) The PF, SF and ZF are affected iy AF, CF and OF are undefined after AAD- Algorithm AL = (AH * 10)+AL ae AL©10*(AH)+AL = AH «0 Addr. Mode — Implied Add: ng eibds Operation + It converts two unpacked BCD digits in AH and AL to the equivalent ee tetris adjurtment must bo made bafoe dividing the two unpacked BCD digits in AX, by an unp After the division, AL-— unpacked BCD quotient AH — unpacked BCD remainder Example AX = 0607H unpacked This instruction will perform following BCD for 67 decimal operation. CL = 09 H, now adjust to (AH)* 10 = 06 * 10 = (60)ieimai = SCH Binary using AAD. (AH) #10 + (AL) = (6Oh0+ (Die = 23CH+7H=43H DIVCL oe rat Ob Mnemonic CBW Algorithm IfMSBbitof AL=1 else AH=0 Addr. Mode Implied Addressing mode Operation * ‘This instruction copies the sign bit in AL to all the bits in AH. AH is then said to be a sign extension of AL. «| ‘This operation must be done before a signed byte in AL can be divided by another signed byte with IDIV instruction. AX = 00ACH CBW =—163decimal Convert signed byte in AL to signed word in AX. Result :1111 1111 1010 0011 =~ 163 decimal Example Microprocessors & Interfacing (MDU) 12-42 Addressing Modes and Instruction Set Mnemonic CWD Flags No flags are affected. Algorithm —If MSB bit of AX= 1 . then, DX = 655 35 ( FFFF H) else DX=0 ‘Addr. Mode Implied addressing mode Operation + This instruction copies the sigh bit of word in AX to all the bits of DX 5 register. DX is sign extension of AX then. © It must be done before signed word in AX canbe divided by another signed word with IDIV instruction. 12.8 Bit Manipulation Instructions a 3 12.8 Bit Manipulation Instructions ‘The 8086/8088 provide three groups of instructions, for manipulating bits within both bytes and words. Three groups are listed in Table 12.8.1. i Table 12.84 : Bit manipulation instructions E GICALS == And byte or word. Inclusive or byte or word Exclusive or byte or word Test byte or word : ere a . Shift logical/arithmetic left byte or word Shift logical right byte or word Shift arithmetic right byte or word Soe = ROL Rotate left byte or word ROR Rotate right byte or word RCL Rotate through carry left byte or word Rotate through carry right byte or word r i I Microprocessors & Interfacing (MDU) 12-43 Addressing Modes, 12.8.1 Logical Group Mnemonic NOT destination. Flags No flags are affected. Algorithm If bit is 1 turn it to 0 If bit is 0 turn it to 1 Addr. Mode Register Addressing mode Operation Destination — Destination ¢ This instruction inverts each bit of byte or word at the specified destination ie. it finds I’s complement of the number. ‘The destination can be a register or a memory location. + The destination cannot be immediate data. «The destination cannot be a segment register. Example NOTAX AX+ AK This instruction complements the contents of AX register. Mnemonic AND destination, source i Flags CF and OF are both 0 after the execution of AND instruction. PF, SF and ZF are updated by AND instruction. AF is undefined. Algorithm Destination = destination 0 source Addr. Mode Register addressing mode Operation 1AND1=1 1AND0=0 OAND 1=0 OANDO=0 racing (MOU) ia-44 ‘ 4 Address eo ys 8 Sing Modes ang Instruction Set i ion ANDs each bit in a source byte or w, ord wit $i ison byte or word. The result is stored at eee es Same number bit af vats of specified source do not change, . 1 ne ice con be a register, Memory location or an immediate Dumber. ' sation can be register, or memory location, ha Pes and destination both cannot be memory locations . ‘ goat registers cannot be used as source or destination . U je ANDAL, BL iatruction ANDs each bitin a AL register with the bits in BL register. The remut sarin the AL register. i! °3,OR-~ Inclusive or byte or word nnemonic OR destination, source. ys CF = 0, OF = 0, after OR instruction PF, SF and ZF are affected. AF is undefined. Agorthm destination « destination v source. Mér. Mode Register addressing mode Oration 10R1=1 10R0=1 O0OR1=1 QOR0=0 * This instruction ORs each bit in a source with the corresponding bits in a destination. : ‘The result is stored in the specified destination. Contents of soiree will not change. Sourve can be register, memory location or immediate number. ‘The source and destination both cannot be memory locations. * The segment registers cannot be used as source or destination . * Destination can be a register or Memory location le OR AL, BL untstruction ORs each bit in a AL register with the bits in BL register. The reli ‘nthe AL register, ae ‘nem i Rag, © XOR destination, source. igs CF = 0, OF = 0 after XOR instruction PR, SF and ZF are affected. AF will be undefined. 1XOR1=0 1XOR0=1 0XOR1=1 Register addressing mode oxXOR0=0 Microprocessors & Interfacing (MOU) 12-48 Addressing Modes and Instruction | Operation + This instruction logically XORs each bit of the source byte or word th corresponding bit in the destination and stores the result in the destination. The source may be register, memory location or immediate number. ‘The destination may be register or memory location. + The source and déstination both cannot be memory locations. + The segment registers cannot be used as source or destination. Example XORAL,BL ‘This instruction XORs each bit in a AL register with the bits in BL register. The result is stored in the AL register, | Mnemonic TEST destination, source. Flags CF =0,0F=0 | PF, SF, ZF will be affected to | : show result of ANDing. Algorithm ‘destination « destination source. | Addr. Mode Immediate addressing mode | Operation 1AND1=1 1AND0=0 OAND 1=0 OANDO0=0 . * This instruction ANDs contents of a source byte or word with contents of specified | destination word. ‘The source-can be register, memory location, immediate data. | 5 ‘The source and destination both cannot be memory locations. | ‘Segment registers are not allowed to be used as source or destination. ‘The destination can be a register or memory location. Flags are affected, but neither operand is changed. It is used to set flags before conditional JUMP. Example TEST AL, 75H | Let AL=0111 0101AND Immediate number 75H with AL. PF = 0, SF = 0, ZF = 0, CF=0,OF =0 12.8.2 Shifts Microprocessors & Interfacing (MDU) 12-46 Addressing Modes and Instruction Set | | Mnemonic — SAL/SHL destination, count. Flags All flags are affected. | Algorithm Shift all bits left, the bit that goes off is set to CF. Zero bit is inserted in the right most position. | Addr. Mode Immediate addressing mode Operation CF « MSB« LSB<-0 * SAL/SHL are two mmemonics for the same instruction. This instruction shifts each bit of the Operand specifies destination, some number of bit Positions to the left. As left bit is shifted out of | ™ - the LSB position, 0 is put in the LSB position. ee Ee ‘The MSB will be shifted into CF, ss u * The count can be any immediate number. Fig, 12.8.1 - + In caso of nnultiple bit shifts, CF will contain the bit most recently shifted in from the MSB. Bits shifted into CF previously will be lost. This instruction can be used to multiply an unsigned binary number by a power of 2. ‘The destination can be a memory location or register. ‘The count is specified in the CX register. Nogative shifts are illegal. Example © SHLAX,01 This instruction shift AX by 1 bit to the left. Mnemonic SHR destination, count. Flags’ All the flags are affected. Algorithm Shift all bits right, the bit that goes off is set to CF. Zero bit is ineroased to the right most position. ; Addr. Mode Register addressing mode ‘ Operation 0» MSB-+ LSB CF * This instruction shifts each bit in specified = | destination some number of bit position to ° | the right Bit shifted from LSB, goos to CF. , MSB 1.88 cr | © For Multi bit shift, CF will contain bit most) “——___. recently shifted out from LSB position. Operand Negative shifts are illegal ‘The count is specified in CL = 02H the CX register. * Bits shifted into CF previously will be lost. Mig 12.82 * This instruction is used to divide unsigned binary ‘number by power of 2. * Count is any immediate number. : . = Addressing Modes 2Nd Inst, lo r Microprocessors & Interfacing (MOU) 12-47 Set Example SHR AX, CL ‘This instruction shifts each bit in the accumulator by two times to the right, 3. SAR ~ Shift arithmetic right byte-or word.» | Wnemonie SAR destination, count Flags All Nags are afd [Algorithm Shift all bits right, the bit that goes off is set to CP. Fe The sign bit that is inserted to the leftmost Position has th as before shift, ere vag Addr. Mode Immediate addressing mode Operation MSB + MSB - LSB + CF * This instruction shifts each Ddit is specified destination, same number of bit POsition of the right, Number of bits to be shifted depends u; 1pon count. + As bit is sited out of the sis eg sition, a copy of o MSB putin te Nowe 2S Sa j Position, ie. the sign bit is OQ : i copied into the MSB. LSB is NewNSB=Old mse E moved into CF. Se | + Bits shied into CF Operand previously will be lost. Fig. 1283 . Nogae sian any inmate uber or pc fa the Ck repr * Negative shifts are illegal. 12.8.3 Rotates Mnemonic ROL. destination, source Algorithm Shift all bits eft, the bit goes o ‘@ the right most position, Flags Only CF and Osea fT is sot to CF and the same bit is inse in a specified word or, byte to the left, by some ins gut of MSB is circled back into the LSB. The data bit rotated ypied 10 CF. * afl oe used for rotate instruct sad register Us ‘ ROL AX, 01 rotates the contents of tion when count is greater than 1. . AX register by'1 bit to left. instruction ay is 2: ROR - Ro soem ROR destination, count. Flags - Shift all bits right, the bit that goes off is set to CF and the same bit is met inserted into the left most position Register addressing ‘mode. ar, Mode cr MS8 > LSB Operation | Thisinstruction rotates all the bits of specified destination operand to the right. The simaved out ofthe LSB is rotated around into the MSB. + The data bit moved out of LSB is also copied into CF. + ‘Thedestination may be memory location or register. + Theemunt if greater than 1 should be specified in the CX register. + Negative shifts are illegal: 2: RGL © Rotate through carry left byte of word Mr Iemonic RCL destination, count. lags Only CF and OF are affected: ‘orth Shift al bits left, the bit that goes is set to CF and previous value of CF MM. Mog is inserted to the rightmost position. Sperati 'e Immediate addressing mode ‘on CF + MSB «LSB _— Peis eon rotates all the bits in specified destination by som number of bit the lh The destination ean be register oF remory ication Microprocessors & Interfacing (MOU) 12.49 ‘Addressing Modes and Instruction Set | Nogative shifts are illegal. + CLis default register used for rotate instruction when count is greater than 1. ' 4, RCR - Rotate through carry right byte or wOrd?: Mnemonic —_RCR destination, count. Flags It affects only CF and OF Algorithm Shift all bits right, the bit that goes off is set to CF and previous value of CF is inserted to the left most position Addr, Mode Immediate addressing mode Operation CF + MSB > LSB tf + This instruction rotates all the bits is specified word or byte same number of bit Positions to right. The destination can be register or memory location. + Negative shifts are illegal. + _ CLis default register used for rotate instruction when count is greater than 1. 12.9 Processor Control Instruction 3 "he instructions under this group are listed as fellows Table 12.9.1 : Processor control instructions FLAG OPERATIONS STC _| Set carry flag CLC | Clear carry flag CMC | Complement carry flag Set direction flag Clear direction flag Set interrupt enable flag Clear interrupt enable flag NO OPERATION: .. ; NOP | No operation HLT | Halt until interrupt or reset WAIT alelg le Wait for TEST pin active ESC _| Escape to external co-processor LOCK | Lock bus during next instruction eases ee Mi yeessors & Interfacing (MDU) 12-50 Addressing Modes and Instruction Set lieropro SS i i ions. One group of i structions allow programs to control various CPU functions. > i iran updates flags and another group is used primarily for synchronizing the eves or 8088, with external events. A final instruction causes the CPU to do nothing. Except for the flag operations, none of the processor control instructions affect the flags. 12.9.1 Flag Operations 3 Mnemonic CLC ° Flags © Except carry, no other flags are affected. Algorithm CF=0 Addr. Mode Implied addressing mode : Operation CFO This instructions clears (resets) the carry flag to zero,” | Mnemonic STC Flags Except carry no other flags are affected. Algorithm = CF=1 Addr. Mode Implied addressing mode Operation This instruction sets the carry flag, Mnemonic CMC Flags ‘ = Algorithm — if CF = 0 then CF =1 ifCre Pt carry other flags are Addr, Mode Operation “Mnemonic Algorithm Addr. Mode Operation Mnemonic Algorithm Addr, Mode Operation Mnemonic Algorithm Addr. Mode Operation Mnemonic Algorithm Addr. Mode Operation Implied addressing mode CF= CF This instruction inverts the Value of carry flag [4 CLD ~ cleat rection ap: CLD Flags Except direction flag, no other flags arg fi DF=0 . Implied addressing mode © It resets (DF) direction flag to zero. If the directi direction flag is and 1 or DI will be aulamatially erecta ig aS operations, * When one of the string instructions like Moy: executes it automati; 'S, CMPS 9, cally increments the SI and/or DI Tegiater Scas STD * Flags Except Direction no other flags are affected, DF=1 Implied addressing mode . dewalt Bw tha nd wa decremented by string instructions, ie. CMPsB, MOVss, STOSW ete, CLI Flags Except, ‘interrupt flag, it does not affect any other flag. IF=0 Implied addressing mode * This instruction Tesets the ‘interrupt flag to zero, No other flags are Tf the interrupt, flag is Teset, the 8086 will not Yespond to an interrupt signal on its INTR input, This instruction has Flags Except ‘interrupt flag, it does not affect any other flag. sl * This interrupt se a, he interrupt flag to 1. ‘This enables INTE interrupt of the 8086, operation Flags It does not affect any flag. aoe ve No operation Do noth rosing mode nv jed addressing . . erg lolod tion ofthis instruction causes the CPU to do nothing. — we oxen ction causes the CPU to do nothing. This instruction uses wp? this instr (ycles and increments the instruction pointer to point to ehree . : instruction. : tne pe ued 0 increase the delay of a deley loop. « Ite a nail synchronisation The 93 exte! Mnemonic Halt processing Flags No flags are affected. Operation + The HLT instruction will cause the 8086 to stop fetching and executing instructions. The 8086 enters into a halt state. To come out of the halt state, there are 3 ways given below. . @ Interrupt signal on INTR pin (i) Interrupt signal on NMI pin ii) Reset signal on reset pin. It may be used as an alternative to an endless software loop in situations where a program must wait for an interrupt. - 2. WAIT = Walt for TEST pin active oem aie, WARE Flags No flags are affected. When this instruction executes, tie 8086 enters on idle condition in ‘hich itis doing no processing. . ‘The 8086 will stay in this idle state until 8086 TEST input pin is made low or on interrupt signal is received on the INTR or NMI interrupt pins, i Pn Mnemonic Operation Mnemonic Operation Example 12.10 Microprocessors & Interfacing (MDU) 12-63 ‘Addressing Modes and instruction Set + Ifa valid interrupt occurs while the 8086 is in the idle state, the 8086 will return to idle state after the interrupt service procedure { ‘executes. ve It is used to synchronize the 8086 with extemal hardware. Such as 8087 math processor. ALESC + Escape to exter ESC external ~ opcode, source. This instruction is used to Pass instruction to a coprocessor, such as 8087 math co-processor which shares the address and data bus with on 8086. * ‘The instruction for the Co-processor are represented by a 6 bit code embedded in the escape instruction. : * When the 8086 fetches on ESC instruction, the coprocessor decodes the instruction and carries out the action specified by the 6 bit code specified in the instruction. + In most cases 8086 treats the ESC instruction as a NOP in some cases 8086 will access a data item in memory for co-processor. 4, LOCK Lotk bus’ nt LOCK Many multiprocessor systems contain several microprocessors. Each microprocessor has its own local buses and memory. The individual microproces: sors are connected together by a shared system bus so that. each can access system resources such as disk drives or memory. + Each microprocessor takes control of the system bus. Only when it needs to access some resource. Lock prefix allows a microprocessor to make sure that another processor does not take control of the system bus. While it is in the middle of a critical instruction which uses the system bus when an instruction with lock prefix executes the 8086 will assert. its bus lock signal output. This signal is connected to an external bus controller, which then prevents any other processor from taking over the system bus. LOCK XCHG SEMAPHORE, AL : The XCHG instruction requires two bus accesses. The lock prefix prevents another processor from taking control of system bus between two accesses. : Program Transfer Group 8086/8088 provides you :-, 1) Unconditional CALL 2) IMP -[ Conditional . Unconditional 3) INT (Software interrupt) and many more, microprocessors & Interracing (MOU) 12-54 __._Addressing Modes and instruction Set ‘These instructions are also referred to as Branch instructions. We have four subgroups under this : Conditional transfe: Interrupt relate instructions. | | Instructions under these subgroups are listed as follows in Table 12.10.1. Table 12,10.1 : Program transfer tasiructions | E UNCONDITIONAL TRANSFERS CALL | Call procedure LOOP RET Return from procedure LOOPE/LOOPZ | Loop if equal/zero IMP. Jump LOOPNEMLOOPNZ Loop if not equal/not zero. | . oe GONDMIONAL RROPTS A | [GavnBe | Jump if above / not below or eq Interrupt JAE/JNB | Jump if above or equal / not below Interrupt if overtiow Interrupt return |_| JevNae: | Jump if below / not above nor equal |_| sBEWNA | Jump if below or equal / not above Jc Jump if carry JENZ — | Jump if equal / zero JGIINLE | Jump if greater / not less nor equal JGEJJNL | Jump if greater or equal /not less JLISNGE | Jump if less /,not greater nor equal | JLEAING | Jump if less or equal / not greater Nc | Jump if not carry JNEKINZ | Jump if not equal / not zero | [sno Jump if riot overflow | | uNPHIPO | Jump if not parity / party odd JNS Jump if not sign | vo Jump if overflow | | SPRUE | Jump if party / parity even Js Jump if sign 12.10.1 Unconditional Transfers | ‘The unconditional transfer instructions may transfer control to a target instructi | within the carrent code segment (intrasegment transfer) or to a different code segment (intersegment transfer). The transfer is made unconditionally any time the instruction is | executed. Mnemonic : CALL procedure . Operation : This instruction is used to transfer Program control to a Bul . ’ procedure. There are two basic types of CALLS : NEAR Call and RF, * Near Call: A near calls a call o a procedure which isin the sama on AR Ca has the CALL instruction. Itis also called as Intra segment eal” @™nt, Which Ifthe call tothe subroutine or procedure with a 16-bit signed diaplacome 8086 will decrement the SP by 2 and push the IP contents onte the stack mite adds the signed 16 bit vale of DISP of P. The contents of CS > tat tte Such a call is an intra segment direct call. ‘anged, eg. DISP PROC NEAR: It indicates that DISP is the * hich isin the same code segment. DISP is 16 bit signed daplaegss Pt Addressing mode : Relative addressing mode Gi) Ifthe CALL is to a subroutine is in the same i contents of a 16-bit general register/memory. Then the 8086 by 2 and pushes the contents of IP onto the stack and then the contents of specified 16 bit register/memary location. ‘The registers can be BX, SI or DI to provide the new value of IP. prsanemery location is addressed by contents of 16 bt repatr such as BX, DI into IP. The contents of CS remain unchanged. Such a calls called isan intra segueat 5 indirect call. fF eg. : CALL Reg 16. : * Far Call : A far is a call to a procedure which is in a different segment from that Which contains the CALL instruction. Far calls are also called as intersegment call, @ Ifthe far call to a subroutine or procedure is with a signed displacement, the 8086 decrements SP by 2 and pushes the contents of CS onto the stack and moves the lower 16 bit value of the number like DISP in CALL DISP into CS ‘The SP is again decremented by 2. The contents of IP are pushed onto the stack. The IP is then loaded with the higher 16 bits ie. MSB value of DISP. ‘Thus, as this instruction CALLS a subroutine in another code segment it is 1 intersegment direct call. tents of (i) Ifthe CALL to a subroutine in another segrnent is addressed by the os © @ 16 bit register then the 8086 decrements the SP by 2 and P contents onto the stack. ions addressed by ‘The ‘CS is then loaded with the contents of memory locations {reg 16 + 2} and (reg 16 + 3] in DS, Bis ‘The SP is then again decremented by 2, IP is pushed onto the tak Tg » then loaded with contents of memory locations addressed by (reg 16 + 1) in DS, intend (MoU) es 018 5 rs used 0s reg 16 are BX, SI, DL ee . js called a8 jntersegment indirect call. soot LL WORD, PTR Ireg16] eg Addressing Modes and Instruction Set ic yET optional - PoP ~ value \" on Return from near procedure ue POP from stack : IP Jfimmediate operand is present : sp=SP+ operand « Return from far procedure POP from stack rP cs Jfimmediate operand is present 9p = SP + operand Operation * The RET instruction will return ‘execution from a procedure to the next instruction after CALL instruction: If the procedure is a near procedure (ie. in same code segment as CALL instruction), then the return will be done by replacing the P with a word from the top of stack. ‘This word from the top of stack is the offset of the next instruction after CALL. ‘The SP will be incremented by 2. After rebum address is popped off the stack. If the procedure is a far procedure (in a different code segment), the instruction pointer will be replaced by the word at the top of stack. The SP will be incremented by 2. ‘The CS is then replaced with aword fom new top of stack. After CS wiord is popped the SP will aesin incremented by two. * ARET instruction can be followed by a number. Rrample RET 2, iti rosses afte «+ In this case the SP will be incremented by additional 2 ose a the IP or IP and CS are popped off the stack ‘his form ar be increment the stack pointer UP over parameters passed procedure on the stack. mnaupruuesours o mertacing (MUU) 12:57 ‘Addressing Modes and Instruction Set Cnconditional jump to specified destination) Mnemonic JMP Algorithm Operation Flags No flags are affected. Always jump. + This instruction will cause the 8086 to fetch its next instruction from the location’ specified in the instruction rather than from next location after JMP instruction, ‘There are two basic types of JMPs, near and far. Near JMP is a jump where destination location is in the same code segment only IP is changed to get destination location. It is known as intrasegment JMP. If the destination is in a segment with a different name from the ‘segment containing,the JMP instruction, then both the IP and CS contents will be changed to get the destination location. Such a JMP is far JMP. A far JMP is an Inter segment JMP. The near and far JMPs are further described as either direct or indirect. If the destination address is specified within instruction. It is a direct JMP, if the destination address is‘contained in register or memory location, the JMP is indirect, because 8086 has to access the specified register or memory to get the destination address. Example JMP WORD PTR [BX] | © This instruction will replace IP with a word from memory location pointed by BK in DS. « This is an indirect near JMP. 12.10.2 Conditional Transfers Conditional transfer instructions are also referred as conditional jump instructions. There are total 18 instructions. Refer Table, each test a different combinations of flags, for a condition. If condition is true, then control is transferred to the target specified in the instruction. If the condition is false, then control passes to the instruction that follows the conditional jump.-Very important point regarding these instructions is, all conditional jumps are SHORT, that is, the target must be within the current code segment and within ~ 128 to + 127 bytes of the first byte of the next instruction. Since the jump is made by adding the relative displacement of the target to the instruction pointer, all conditional jumps are self relative and are appropriate for position independent routines. These instructions does not affect any flag. @) Microprocessors & interracing (MUU) 1e-00 Puuiwoniny myues au mewwvsivil ve | Jc JUMP if carry Jore1 | INC _| JUMP ifnot carry CF=0 | J2JE__| JUMP if zero (or equal) ZF =1 \aeeane JUMP if not zero (or not equal) 2F=1 | SPASPE _| JUMP if parity (or even parity) PF=1 | INP/IPO | JUMP if not parity (or odd parity) | JOxZ | Ke OF =1 | INO OF=0 | JS JUMP if sign ve) S=1 | _ [ans [SUMP if not sign @ ve) [s=0 . | JLAINGE | JUMP ifless (ie, either greater nor equal) — | SF @OF = 1 | INLIGE | JUMP if not lees (i.e. either greater or equal) | SF ® OF = 0. | JLE/ING | JUMP if less or equal (ie. not greater) (GF @ OF) +ZF=1 JINLEG | JUMP ifn ither ke qual (i.e. greater) “| (SF ® OF) +2ZF que ier less nor equal (i.e. greater) ‘| ( F) + = “ES nsigned Operationg |S | JB/INAE | JUMP if below (Le. neither above nor equal) | INB/JAE | JUMP ifnot below (.e. either above or equal) | JBE/INA | JUMP if below or equal (i.e. not above) CFOZF=1 | INBEWA | JUMP ifneither below nor equal (,e. above) | CFO ZF 50 | 12.10.3 Iteration Control Instructions The Instructions in this group are used to regulate the repetition of software loops. Like conditional transfers the iteration control instructions are self relative and may only transfer to targets that are within -128 to +127 bytes of themsolves, ie. they are short | transfers. Microprocessors & Interfacing (MOU) Mnemonic Algorithm Operation Mnemonic Algorithm Mnemonic Operation 12:59 Addressing Modes and AStrUctog Sq | f 1 LOOP short_label LOOP : Jump to specified lable if ~ CX £0 after auto decrement CX =CX-1 IfCX <> 0 then jump else no jump, continue This instruction is used to repeat a series of instructions some ny mb times. The number of times the instruction sequence is to be Tepeated of loaded into CX. Each time loop executes CX is decremented by 1, is + IfCX+0 execution will jump to destination specified by label + IfCK = Oexecution will go to the next instruction after loop, Flags No flags are Affected Loop while CX # 0 and 2F = 1 LOOPE short-labeV/LOOP2 ‘short-label. CK=CK-1 1f(CX <> 0) and ZF = 1 then jump else no jump, continue. * This instruction is used to repeat a group of instructions some nunber of times or until zero flag becomes zero. + Number of times of repetition is loaded in CX. Flags No flags are affecteg Loop while CX # 0 and ZF = 0 LOOPNZ short-label or LOOPNE short-label * CX=CX-1 * if (CK <>0)and ZF = 0 then jump Flags No flags are affected. else no jump, continue is i ‘ion ij ir This instruction is used to repeat a group of instructions some numb Cf times oF until zero flag becomes 1 * Number of times of repetition is loaded in GK it interfacing (MOU) 12-60 Addressing Modes and Instruction Set interrupts y yor instructions allow. interrupt service routines to be acti Pg erat fy eeral hardware deve, The oft of svar eee & is 5 Gware-initiated interrupts. pts is 0 om Hemonic INT interrupt — type Flags ‘IF =Oand TF=0 No other flags are affected Ayorthm * Push to stack «flag register « cS ©) ae + IF=0,TF=0 ‘Transfer control to interrupt procedure. ‘ Operation This instruction causes 8086 to call a far procedure. The term ‘type refers number between 0 to 255 which identifies the interrupt. When an 8086 executes an INT instruction, it will Decrement SP by 2 and push flag register on stack. Gi) » Decrement SP by 2 and push CS contents on stack. Decrement SP by 2 and push the IP after INT on stack (iv) Care ete for IP from 2 memary adress of 4 times the vee specified in instruction. 7 l e.g. For INT 8, the new IP will be ee oe OE aa ") Get new CS from memory address of 4 times Te 7 . instruction plus 2. e.g. For INT 8, new value of CS will be read from eg INT 35: New IP from 008C H ‘ New CS from: (vi) Reset IF and TF Memon ic INTO r= Oand TF =0 No other flag is fected Microprocessors & Interfacing (MOU) 12-61 Addressing Modes: and Instruction Set Operation . Ifthe overflow flag is set, this instruction will cause the 8086 to doan indirect far eall to a procedure you write to handle overflow condition. To do this call the 8086 will read a new value for IP from address 0010 H and CS from 0012 H. Mnemonic IRET Algorithm © POP fromstack Flag register Operation ‘The IRET instruction is used at the end of interrupt service routine to ‘return execution to the interrupted program. ‘The 8086 copies retumn address from stack into IP, and CS registers and stored value of flags back to flag register. "fags rom the stack back tothe flag register 12.11 String Instructions Group Q, Explain with example string instructions of 8086 microprocessor. ‘Table 12,11.1 : String instructions ——$—_4 REP Repeat REPE/REPZ __| Repeat while equal/zero REPNEMREPNZ_| Repeat while not equalinot 22r0 MOVSBIMOVSW | Move byte or word string CMPSB/CMPSW | Compare byte or word string | SCASB/CMPSW_| Scan byte or word string LODSB/LODSW ‘| Load byte or word string STOSB/STOSW | Store byte or word string | Microprocessors & Interfacing (MOU) Mnemonic Algorithm 12-62 Addressing Modes and Instruction Set , MOVS/MOVSB/MOVSW :'Move string byte or string word MOVSB/MOVSW Flags No flags are affected. Tn case of byte : ‘ + ES: (Dl =DS: (SI) « IfDF=0then SI=Sl+1 DI=DI+1 else SI=SI-1 DI=DI-1 In case of word : « ES: (Dl =DS: (S0 « IfDF =0 then, SI =SI+2 DI=DI+2 Else SI=SI-2 DI=DI-2 Addr. Mode String addressing mode © This instruction copies a byte or a word from a location in the data Operation segment to a location in the extra segment. ©. The offset of the source byte/word in the DS must be SI register. The offset of the destination in ES must be in DI register. After byte or word is moved, SI and DI are automatically adjusted to point to the next source and next destination. LEA SI, SOURCE_STRING ; SI points to start of source string. Example LEA DI, DEST_STRING 3 DI points to start of destination string. CLD 3 Clear direction flag to use incrementing MOVSB + MOV(D « (SD, byte transfer Mnemonic CMPSB/CMPSW Flags All flags are affected. Two alternate mnemonics for the same instruction CMPB, (compare string byte) CMPW, (compare string word) Algorithm For byte operation DS: [SI] - ES: DN) Set flags according to result -» OF, SF, ZF, AF, PF, CF. IfDF=0 then SI=SI+1 DI=DI+1 else SI=SI-1 Di=DI-1 1 &£ | picroprocessors & Interfacing (MDU) 1263 Addressing Mod, des anit Instruction Set des anid instruction Set Leo For word operation word] DS: (SUES: (Dll Set flags, according to result ~ OF, SF, ZF, AF, PF, CP. . IfDF=0 then SI=SI+2 Di=D affected. else SI=sI-2 Dieor! : Addr. Mode String addressing mode Operation + This instruction is used to compare a byte in one string with aby; nother string or to compare a word in one string with snotiey byte in * Sls used to hold the offset of a byte or word in the Source s{ Dlis used to held the offset of byte or word is another string 8d * Comparison is done by subtracting the byte or: ‘word pointed byte or word pointed by SI. *y Di om * After comparison SI and DI will be automatically incre; acromented according to direction flag to point to next elements.” é string. Example LEA §I,'‘SRC + SI points to start of source string labeled SRC. LEADI,DEST ; DI Points to start of destination’ ‘string labeled DEsT CLD 3 Clear DF-(ncrementing is used). in wie aie 4 - CMPS SRC, DEST ; Compare. S:SCASLS register. ssc sy . Seana string Byte or Word). : cally adjusted to Mnemonic = SCASB/SCASW Flags No flags are affected. SCASB (for byte operation) ree string. Or SCASW (for word operation) Hination string. Algorithm For SCASB se incrementing « AL-ES: (DI) ransfer © Set flags according to result + IfDF=0then DI=DI+1i For SCASW s are affected. » AX-ES: DI + Sot flags according to result « IfDF=0 then DI=DI+2 Else DI=DI-2 Addr. Mode String addressing mode ee Yperation + This instruction compares a byte in AL or word is word pointed to by DI in ES. Hence the string to be scan‘ in ES, and offset in DI. © After comparison DI will be automatically increme decremented according to direction flag DF. mnted OF - 12-64 Addressing Modes ang Instruction Set Microprocessors & | rete wOWD SE orn Operation Lt porn Ti Lond offset Buffer in DI wr ao ay; Als londed with the Byte to be compared. i. ODE Mov Al, * it is ASCH for carriage return it indicates line Example , termination. | Clear direction flag DF to use incrementing oe "Scan for byte in the string. (Load string byte in AL or string word into AX.) : Mnemonic 1¢ LODSB/LODSW Flags No flags are affected. yremonle Gr LODSB (For byte operation) Algorithm Or LODSW (For word operation) nm — LODSB + AL=DS: (80 i IDF =Othen SI =SI+1 else = ST = S-1 i LODSW + AX=DS: (SD WDF=OthenSI=Sl+2 else SI =SI-2 ‘ — Mér, Mode String addressing mode Operation is inetroseon oookee a byte from a string location pointed to by SI to ‘Example CLD , MOV SI, OFFSET Al : SL points to start of Al. )DSB : Load byte in AL from the string Mnemon Algorith Flags No flags are affected STOSB (For byte operation) = eee ig or STOSW (for word operation) ™ For STOSB tr ES: (D0 = AL DF =0 Ly Peston DIsDI+1 else DI=DI-1 * ES: DI) = AX Nee seas Othen Di= DI +2 else I= DI-2 Operat 6 addressing mode sss, Microprocessors & Interfacing (MDU) 1 12-65, Addressing Modes and Instruction Set. : (A Operation It transfers (copies) a byte or word from register AL or AX to the string clement addressed in ES by Dl. Depe on DF flag, DI is automatically inerémented or decremented. Example MOV DI, OFFSET STR 1 ; DI points to top of string STR 1. cLD ;DF=0 MOV AX, 00H sTOSWw + Store string by AX value e ‘Repeat string instruction until specified conditions exist). Mnemonic REP/REPE/REPNE/REPNZ. Algorithm Check_CX For REP . * CX=CK-1, + Repeat the instruction to which it is a prefix * go back to check _ CX else © exit from REP cycle Operation « Flags — REP is a prefix written before one of the string instructions” These instructions repeat until specified condition exists. ft tion ‘ebde | ‘Condition for exit REP CX=0 REPE/REPZ CX=0orZF=0 REPNE/REPNZ | CX = 0orZF=1 Mnemonic REPE/REPZ Algorithm- Check CK ifCX <> 0 then CX =CX-1 if ZF = 1 then Tepeat the instruction to which it is prefix go bick to check CX else exit from REPE cycle else exit from REPE cycle. ‘* These are two mnemonics for the same instruction. * This prefix will cause the string instructions to be repeated as long as 2F=laendCXz0. . IfZF = 0 or CX = tring instructions will not be repeated. Operation Microprocessors & Interfacing Example (mou) 12.66 Addressing Modes and Instruction Set LEADI STR1 ; DI = offset of STR 1 MOVAL, 05H jAL=05H. cLD ;DF=0 MOV CX, 35H ; CX = 35 Hie. counter= 35H - REPE SCASB ; Repeat, scan string byte operation till ;CX#O0andZF=1 Operation Check CX. ifCX<>0 then CX=CX-1 IfZF =0 then repeat the instruction to which it is prefix go back to check CX else exit from REPNE cycle else exit from REPNE cycle. + These are two mnemonics for the same instruction. « This will cause string instructions to be repeated as long as ZF = 0 and CX +0. + IfZ¥ = 1 or CX = 0, string instructions will not be repeated. QaQ peeee ec Assembly Language Programming rer ag 13.1 Introduction to Assembly Language Microprocessor chip designers create a basic set of instructions for every Processor they ding These are really simplistic instructions that take baby steps as compari with high-level languages such as C++. + Each instruction has a code so that the instruction decoder can decode them in order to energize the proper circuits to execute the function using the registers of the Processor. These are referred to as operation code (OPCODE). “Machine code is the instruction set that machine understands”. Machine language is the only language understood directly by the CPU in our computers. * Humans, however, understand words, so each machine code is given an "English" equivalent. These instructions in text form are called Mnemonic. Assembly language is a mnemonic representation of ‘machine code. Assembly language is not just a simple mapping of numbers to words. It also Contains many high-level-language type constructs to make data definition and " program structuring easier. There is a one-to-one correlation between assembly language instructions and the machine code. “ i Reasons for leaming the assembly language ‘The assembly language is leamt for the following reasons : (D "Tehelps to lear about the internal architecture of the Computer. The more you use ° the assembly language the more knowledge you gain about the architecture. ) Sas to make Fat the tities of a computer o.. to directly communicate ca microprocessor of the computer. This 2 = Programming in high level Po 78 is useful under the circumstan f language is difficult or even impossible. i ® Toe sot Sis 8 high level language program written for the above oP always a better solutice 2 Perormance. So use of assembly level programin (The high level the Be Bi rosrel language Programs may need a large memory ee ea iment will reduce if we use the assembly language 13-2 Assembly Language Programming 3 a ‘ fr ess numer of restrictions or rules as compared to the high level 1 oat wi ogo Methodology pr y ¥ qgerll te i iy write short, specific routines and subroutines in the assembly speed Jan arte the | programmers do not write large programs using the assembly main long program using the high level lan; disdicall thers written in assembly language as and when poe . assembly language subroutines can be written to handle operations which are not tele in the higher level language. 2. Development of an Assembly Language Program | used for development Thedevelopment of assembly language program needs following tools : + Assembler * Linker © Loader + Debugger and + Enwlator some of these tools are used for program development, some for the program vention and the remaining are useful for testing the assembly language program. 112.1 Steps for Developing an Assembly Language Program ¢ tering an assembly language program is a four step process. ‘The steps are as llows : {)‘Tospecify the source code as per the assembly language definition | © Assemble the program to create the object code. | (ii) Link the program to create an executable code. | Ge) Test and debug the program. Fig 132.1 shows the steps involved in developing and executing an assembly ‘euge program Ssciption tay ne 13.2.1 to understand the program development steps. Tefen ste itn anlyae wat the programs to dan how we wank BE FOE See Bens “using an editor create the source file for program The seco ! . ed sten § . ' Ttg, 24 step is to assemble this source file. x a ‘us assembler indicates errors then use the editar for correstn them and agnin | “stmble this source file. Microprocessors & Interfacing (MOU) 13:3 Step 3: If the program consists of several modules, then use the linker to join them into one large object module. If the system needs to locate a program in *asM order to specify its location in the memory on then use the locator. ter * At this stage the program is ready for loading into the memory and run. Step 4: +. If the developed program does not interact with any external hardware other than e. that connected directly to the system then EXE use debugger for running‘and debugging MAP your program. If the program is supposed to work with the external hardware system such a microprocessor based. instrument then use emulator to run and debug the program. Fig 13.21 13.3 Assembly Language Program Development Tools {In this section we will go into the details of some of the assembly language program development tools. 13.3.1 Editor ‘ ‘An editor is basically a software (ie. a program). Tt helps the user to create a file that contains the assembly language statements. The examples of editors used for the assembly language Programs are Wordstar, Edit, WordPad, Notepad ete. . ‘The job of the editor is to store the ASCI codes for the letters and numbers in the successive RAM locations, As the typing of program is over, this ‘This file is cailed as the “source file” ‘The source file is then processed file is stored on a floppy or hard disk. and an ASM extension is given to it, using an assembler. (MOU) 13-8 ieee Tw fe qinteracind rem m Formal \d Assembler Directives 09 the structure of general assembler a | unite structure for 8086 18 Tot oj assembler PrOBTam i is shown in Figs. 13.42 (a) ang \ \ Fig. 13.4.2(0) : Program structure 13.5 Assembler Directives ives? Explain any four assembler Q What are different types of assembler directi Zen language consist of ) Executable statements ty the pee ([These are the atatements to be exec” executed " 2 instruction set of 8086Kas az seen in the chapter ) ) Assembler directives are the statements that direct the 8 peat e Salar aey eer ino are only sab The speciality of these sta a a Santee of a program but they do not genera 259 CO eg ct We can divide the assembler ives Purpose directives and the special directive® They are classified into the following categories based on the functions performed by them. . © Simplified segment directives Data allocation directives « Segment directives © Macros related directives © Code label directives © — Scope directives . Mears & Interfacing (MOU) 13-9 Assembly Language Programming | | | ¢ Listing control directives Miscellaneous directives Fig. 13.5.1 : Assembly directives 4. . CODE _* This assembler directive indicates the beginning of the code segment. Its format is as follows : | _+ CODE [name] “ The name in this format is optional. ¢ For tiny, small and compact models the segment name is - TEXT always. ¢ The medium and large. memory models use more than one code segments which can be distinguished by name. 2 .DATA — This directive indicates the beginning of the data segment. 3. .MODEL This directive is used for selecting a standard memory model for the assembly language program. /* ach memory model has various limitation depending on the maximum space available for code and data. 's_-The general format for defining the Model directive is as follows : - MODEL [memory model] : « The memory model is chosen based on the user's requirement by referring to Table 13.5.1. ‘able 13.5. Small | One code segment and of size < = 64 | One of size < = 64 Kbytes Kbytes Medium | Code segment may be of any number and any size. One of size < = 64 Kbytes | miroprocessors & Interfacing (MOU) 1340 Assembly Language Programming | . | [Model “] Number of Code Segmentalisssa] Notberof Dail SegManWeTE { [Compact | One of size < = 64 Kbytes Data: segment of any number and any size, Large __| Any number, any size ‘Any number, any size. ‘Huge __| Any number, any size Any number, any size. i ‘The size of a memory model can be anything from small to huge. i ‘The tiny model is meant for the . COM programs because they have their code, data and stack in only one 64 kB segment of memory. On the other hand the flat model is the biggest which defines one area upto! [Link] for code and data. © The small model is useful for the student level programs because for this model 4 the assembler assumes that the addresses are within a span of 64 kB and hence generates 16 kB offset addresses. a + In the compact model, the assembler can use 92 bit addresses. So the executi time for this model is longer. | + The huge model contains variables such as arrays which need a larger space | than 64 KB. 4 | 4 stack ; \ | (> ‘This directive is used for defining the stack. Its format is as follows : + STACK [size] * — The size of the'stack is 1024 bytes by default but this size can be overridden. . ‘We can omit the . stack command if the stack segment is not to be used in l= | Example of the stack directive is | . STACK 100 Which reserves 100 bytes for the stack segment. u | & EqUEquate : | It is used to give a name to some value or symbol in thé program. | | + Bach time when the assembler finds that name in the that name with the value assigned to that r variable pes ¢ Its format is [name] EQU initial value. | ae. : FACTORIAL EQU 05H. ; ‘This statement is written during the beginning of the d g ‘program and whenever now FACTORIAL appears in an instruction irecti: 4 inte or another directive, the nies | The advantage of using EQU in this manner is that if FAGTORIAL i [ several times in a program and the value has to be changed, all that her change the EQU statement and reassemble the aia: | ‘The assembler with automatically put the new value each time it finds tid name FACTORIAL, ‘This directive defines the byte type variable. 6. Define Byte [DB] , i a | Microprocessors & interfacing (MDU) 13-11 Assembly Language Programming 4 “ «It is also useful to set one or more storage locations aside. 2 The format of this directive is as follows : [name] DB initial value * The initial-value can be a numerical value (8 - bit long) or more than one 8 bit numeric values. It can be a constant expression, or a string constant or even a question mark. © The initial value can be a signed or unsigned number. Its range is from - 198 to + 127 if unsigned and 0 to 255 if it is unsigned. ; 7. Define Word or Word (ow) ‘The DW directive dofines items that are one word (two bytes) in length. For unsigned numeric data the range of values is 0 to 65, 535 + _Fer signed data the range of values is - 32, 768 to + 32, 767, 27 Its format is [name] DW initial value. eg. List DW . 2534. Define Double Word or DWORD [0D] * It defines the data items that are a double word (four bytes) in length. | ~ It creates storage for 32 bit double words. The format is {name] DD initial value. eg. BUFF DD ? 9. een Word or QWORD (pq) ‘This directive is used to tell the assembler to or to reserve 4 words of storé declare variable 4 words in length ‘age in memory. TG Her digaat One OF More constant, each with a maxismam of 8 bytes or 16 Hex digits. * , Its format is: + {name] DQ initial value, [initial value}, eg Num DQ — 1234567898765432H. 10. Define Ten Bytes or TEYTE [DT] tis used to define the data j a Its format is : [ame] DT initial value, [initial value). [Link] DT 1234567890, ' Unlike the other data directiv ems that are 10 bytes long, ‘es with store hexadecimal numbers, DT will directly store the data in decimal form. 11, ORG-Originate The ORG directive allows us to set the location counter to any desired value at any point in the program. * Mhe location counter is automatically set to 0000H when the assembler reads a ‘segment. Its format is ORG expression. ©8 ORG 500H ; Set the location counter to 600 H. byte. din ORG statementa to info $f outer relative t its ‘current setae asvembler to make change +50 ; Increments the 0 BC ; current value. @ location counter by 50 from its; uM s . sce i sed for tling te assembler the name ofthe login seme Thich should be USP he formal assume directive is as follows, ASSUME segment register : segment-name ! ster can be CS, DS, SS and ES * the example of Assume directive is a8 follows, "ASSUME CS Code DS: Data, SS: Stack: statement can assign upto 4 segment registers in any sequence. . Inthis example, DS: Data means that associate the name ofdata segment with DS register. similarly CS: Code tells the assembler to associate the name of code segment. with CS register and so on. 4 END 7 Baa sind wt hn end of 8 the assembler is to and it acts as the last statement of & program. . Pg tbe END dirt tenes he Te «The assembler will neglect any statement after an ‘END directive. a ‘The format of END directive is as follows : END 4 SEGMENT and ENDS + The SEGMENT directive is used to indicate the start of a logical statement. ; ENDS directive is used with the segment directive. + ENDS directive indicates the end of the segment. + Its format is name SEGMENT , Begin Segment name ENDS | Bnd Segment. eg : DATA SEGMENT i a DATA ENDS. ROUP coe directive collects the segments of the same ape wn oe segment aan itso that the segments that are grouped will reside . ly data segment. Its format is Keene CHOU Sagan (o0g-naroel [NAME GROUP SEG 1, SEG? Microprocessors & Interfacing (MDU) 1313 ‘Assembly Language Programming | 48. MACRO AND ENDM ‘+ The macros in the programs can be defined by MACRO directive. ) +. The ENDM directive is used along with the Macro directive. ENDM defines the end of macro. Its format is DISP MACRO ; Statements insiue the Macro ENDM 17. ALIGN (2 This directive will tell the assembler to align the next instruction on address which corresponds to the given value. Such an alignment will allow the progessor to access words and double words. - ALIGN number ‘This number should be 2, 4, 8, 16 .... ie it should be a power of 2. * The example of Align directive are ALIGN [Link] ALIGN 4. ALIGN 2 is used for starting the data segment on a word boundary whereas ALIGN 4 will start the data segment on a double boundary word. EVEN (Align on Even Memory Address) 18. an tells the assembler to increment its location counter if required, so that the next defined data item is aligned on an even storage boundary. |_2— The 8086 can read a word from memory in one bus cycle if the word is at an even address. If the word starts at an odd address, the microprocessor must do two read cycles to get 2 bytes of the word. In the first cycle it will read the LSB and in the second it will read MSB : - « Therefore, a series of even words can be read more quickly if they are at an even address. - eg. :EVEN TABLE DB- 10DUP(O) ; It declares an array named ‘ ; TABLE of 10 bytes which are starting from an evenaddress. 49. LABEL is directive assigns name to the current value of the Location Counter. A/ the LABEL directive must be followed by a term which specifies the type associated with that symbolic name. If label is going to be used as the destination for a jump or call, then the LABEL must be specified as type near or type Far. If the label is going to be used to reference a data item, then the label must be specified as type byte, word or double word. e.g. : STACK SEGMENT DW ‘50 DUP (0) ; Set aside 50 words for stack. 3 STACK_TOP LABELWORD ; Give a symbolic name to next location ; after the last word in stack STACK ENDS iii EE Microprocessors & Interfacing (MDU) 13-14 Assembly Language Programming 20, PROC-Procedure (2 This directive is used to indicate the start of a procedure, “The procedures are of two types NEAR and FAR oe HE tas pencadite is within the same segment then the label NEAR should be given Procedure. If the procedure is in another module then the label FAR should be given after procedure. i oA Its format is {procedure-name] 1 PROC NEAR. . A 21, EXTRN '¢/ We indicates that the names dr labels that follow the EXTRN directive are in some other assembly module. eg :EXTRN DISP: FAR. ; The statement tells the assembler that DISP is a label of type far in another assembly module. ‘To call a procedure that is in a program module assembled at a different time from that which contiins the CALL instruction, the assembler has to be told that the procedure is external. ‘The assembler will then put information in thie object code file so that linker can connect the two modules together. ‘The names or labels that are external in one module must be declared public r with the PUBLIC directive in the module where they are defined. + Its format is : e.g.: Procedure_HereSegment EXTRN FACT : FAR XTRN SUM :. NEAR. Procedure_HereEnds. 22, PUBLIC if It informs the assembler and linker that the identified vs ariables in a program are to be referenced by other modules linked with the current one. ©. Its format is PUBLIC variable, [variable] . ‘The variable can be a number (up to two bytes) or a label or a symbol . be . e.g PUBLIC MULTIPLIER, DIVISOR. This makes the two variables Multiplier and Divisor available to other assembly » modules. 23. PAGE a “ ‘This directive is used-to spécify the maximum number of lines on a page and the maximum number of characters on a line, ‘The format of this directive is as follows : | PAGE [ength}, (width) : L, Number of characters on a line. ‘Number of lines on a page SS es fioroprocessors & Interfacing (MOU) 13-15 Assembly Language p, / Hy ‘The example is PAGE 65, 102 which shows th eae ac. 8 e example is » wl shows that the, there 4 ' page and 102 characters per line. A 55 lines per +The number of lines per page typically range from 10 to 255 characters per line will range from 60 to 132 and the number of 24, TITLE 2 ‘Tehelps the user for controling the format of listing of an assembled program + Teis used to give a title to program and print the title on the second l page of the program: Tne ofeach * The maximum number of characters allowed as a title is 60. + The format of this assembler directive is as follows, ‘ TITLE Text » 25. INCLUDE ** p> This directive is used to tell the assembler to insert a block of soures‘code from ‘ the named file into the current source module. This shortens the source code. Its format is INCLUDE path : file name. 36. NAME “This directive assigns a specific name to each assembly module when programs consisting of several modules are written. 27. DUP Operator Whenever we want to allocate space for a table or an array the DUP directive can be used. The DUP operator it will be used after a storage allocation directive like (DB, DW, DQ, DT, DD). = * With DUP, we can repeat one or more values while assigning the storage values . . Its format is [name] Data-Type Number DUP (value). eg.: List DB 20 DUP (0) ; A list of 20 bytes, where each byte is zero. A DUP operator may be nested. eg. LIST 1 DB 4 DUP (4 DUP (0). 3 DUP (X')); The assembler assigns the values in memory here as follows, 00, 00, 00, 00, x, x, x 00, 00, 00, 00, x, x, x 00, 00, 00, 00, x, x,x 00, 00, 00, 00, x, x, x 28, GLOBAL — Declare Symbols as PUBLIC or EXTRN + This directive can be used instead of PUBLIC directive or instead EXTRN direttive : + For aname or variable defined in the current module, the GLOBAL directive '§ used to make the variable available to all other modules. | Its format is i : GLOBAL FACTOR — ; it makes the variable FACTOR public that jt? ; be accessed from all other modules that are 4 13-16 Assembly Language Programming sembly Language Frogramming ; it tells assembler that variable FACTOR of ; type word which is in another assembly module | or EXTRN. : ieTH de : 4 OcisancBt ter o find the numberof elements i a named dat ten Iti 5s an array. thee oe atrngis aways etre in Hex by the 6086. ithe length ‘ ts fry CK, LENGTH STRING ; Loads the Length of string in CK. eg . oFFSeT : js an operator. . i pare the assembler to determine the offset or displacement of a named: item. : vas also determine the offset of a procedure from the start of the segment which contains it «Its format is: ee MOV AX, OFFSETNUM ; It will load the offset of NUM in the 3 register. 3, ENDP-End Procedure +. This directive is used along with the name of the procedure to indicate the * of procedure + ENDP defines the end of procedure. eg: FACTPROCFAR __ ; Start procedure named FACT and informs ; assembler that the procedure is FAR. Body of Procedure ; FACT ENDP 5 End of Procedure FACT. 3 PTR-Pointer + The pointer is an operator. Ttis used to assign a specific type to a variable or to a label. me, neccesary to do this in any instruction where the type of operand is *€MINCIAX) ; The assembler does not know whether to increment the Tie re, Minted by BX or increment the word pointed to by BX. 2 INC Siti could be avoided by using PTR directive. ie it increments byte pointed to by [BX] me ORD PTR [BX]: it increments word pointed to by [BXI. ee Wor PTR operator can be used to override the declared type of variable. The an CRD DB 28, 45, 10, 56. MOV ar io {be array WORDS will be in terms of bytes. iy pO BYTE PTR WORDS. indirect jump instruction, PTR could be used JMP [BX]. ‘struction does aot tell mi io Il the assembler whether to code the instruction for licroprocessors & Interfacing (MDU) 1347 Assembly Language Programming near jump o fj, For a near jump the instruction is written as © If far juchp is required the instruction is written as e JMP DWORD PTR [BX). 33. SHORT © — Short is an operator. . + Tt is used to tell the assembler that only 1-byte displ i Is used to tll tho an only 1-byte displacement is needed to code If the jump destination is after the jump i ion ‘i ascombler wil astomatally rere byte for hedisglacaaea ee e.g. JMP SHORT NEAR_LABEL. TYPE : ‘The Type is an operator It informs the assembler to find the type of a specified variable. ‘The assembler actually finds the number of bytes in the type of variable. For a byte type variable the assembler gives a value 1. For word type variable the assembler gives a value 2 and for double word 4. 13.6 Structured Programming games ¢ Structured Programming invol}es applying high level language programming concepts to assembly language p1 ing. The term structured applies to certain high- Slevel program statements that can be jlated to assembly code. High level language programmers tr} to use a few basic program structures to solve all problems. The following are the stands rogram structures for high level eR EAM CASE. Structured programming allows the user 1 descriptive sequence of operations that the used wants to carry out in the program. Pooudocode and flowcharts are two ways of thinkity about the program. Pseudocode is a think in pseudocode. Pseudocode is a p : essential features of the program Once the pro is define d in pseudocode the programmer can code various high Jevel structures into e assembly code. 13.6.1 IF...THEN...ELSE Program Structure ‘The structure has format IF condition THEN action ELSE action.

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