Digital devices and systems

Introduction
In our previous sections, we learned about combinational circuit and their working.
The combinational circuits have set of outputs, which depends only on the present
combination of inputs. Below is the block diagram of the synchronous logic circuit.

The sequential circuit is a special type of circuit that has a series of inputs and
outputs. The outputs of the sequential circuits depend on both the combination of
present inputs and previous outputs. The previous output is treated as the present
state. So, the sequential circuit contains the combinational circuit and its memory
storage elements. A sequential circuit doesn't need to always contain a
combinational circuit. So, the sequential circuit can contain only the memory
element.

Difference between the combinational circuits and sequential circuits are given
below:

Combinational Circuits Sequential Circuits

1 The outputs of the combinational circuit The outputs of the sequential circuits de
) depend only on the present inputs. both present inputs and present state(
output).

2 The feedback path is not present in the The feedback path is present in the se
) combinational circuit. circuits.

3 In combinational circuits, memory In the sequential circuit, memory elements

) elements are not required. important role and require.

4 The clock signal is not required for The clock signal is required for sequential ci
) combinational circuits.
 5 The combinational circuit is simple to It is not simple to design a sequential circui
) design.

Types of Sequential Circuits

Asynchronous sequential circuits
The clock signals are not used by the Asynchronous sequential circuits. The
asynchronous circuit is operated through the pulses. So, the changes in the input can
change the state of the circuit. The asynchronous circuits do not use clock pulses.
The internal state is changed when the input variable is changed. The un-clocked
flip-flops or time-delayed are the memory elements of asynchronous sequential
circuits. The asynchronous sequential circuit is similar to the combinational circuits
with feedback.

Synchronous sequential circuits

In synchronous sequential circuits, synchronization of the memory element's state is
done by the clock signal. The output is stored in either flip-flops or latches(memory
devices). The synchronization of the outputs is done with either only negative edges
of the clock signal or only positive edges.

Clock Signal and Triggering

Clock signal
A clock signal is a periodic signal in which ON time and OFF time need not be the
same. When ON time and OFF time of the clock signal are the same, a square wave
is used to represent the clock signal. Below is a diagram which represents the clock
signal:

A clock signal is considered as the square wave. Sometimes, the signal stays at logic,
either high 5V or low 0V, to an equal amount of time. It repeats with a certain time
period, which will be equal to twice the 'ON time' or 'OFF time'.

Types of Triggering
These are two types of triggering in sequential circuits:

Level triggering
The logic High and logic Low are the two levels in the clock signal. In level triggering,
when the clock pulse is at a particular level, only then the circuit is activated. There
are the following types of level triggering:

Positive level triggering

In a positive level triggering, the signal with Logic High occurs. So, in this triggering,
the circuit is operated with such type of clock signal. Below is the diagram of positive
level triggering:

Negative level triggering

In negative level triggering, the signal with Logic Low occurs. So, in this triggering,
the circuit is operated with such type of clock signal. Below is the diagram of
Negative level triggering:

Edge triggering
In clock signal of edge triggering, two types of transitions occur, i.e., transition either
from Logic Low to Logic High or Logic High to Logic Low.

Based on the transitions of the clock signal, there are the following types of edge
triggering:

Positive edge triggering

The transition from Logic Low to Logic High occurs in the clock signal of positive
edge triggering. So, in positive edge triggering, the circuit is operated with such type
of clock signal. The diagram of positive edge triggering is given below.
Negative edge triggering
The transition from Logic High to Logic low occurs in the clock signal of negative
edge triggering. So, in negative edge triggering, the circuit is operated with such
type of clock signal. The diagram of negative edge triggering is given below.

Basics of Flip Flop

A circuit that has two stable states is treated as a flip flop. These stable states are
used to store binary data that can be changed by applying varying inputs. The flip
flops are the fundamental building blocks of the digital system. Flip flops and latches
are examples of data storage elements. In the sequential logical circuit, the flip flop
is the basic storage element. The latches and flip flops are the basic storage
elements but different in working. There are the following types of flip flops:

SR Flip Flop
The S-R flip flop is the most common flip flop used in the digital system. In SR flip
flop, when the set input "S" is true, the output Y will be high, and Y' will be low. It is
required that the wiring of the circuit is maintained when the outputs are
established. We maintain the wiring until set or reset input goes high, or power is
shutdown.

The S-R flip flop is the simplest and easiest circuit to understand.

Truth Table:

J-K Flip-flop
The JK flip flop is used to remove the drawback of the S-R flip flop, i.e., undefined
states. The JK flip flop is formed by doing modification in the SR flip flop. The S-R flip
flop is improved in order to construct the J-K flip flop. When S and R input is set to
true, the SR flip flop gives an inaccurate result. But in the case of JK flip flop, it gives
the correct output.

In J-K flip flop, if both of its inputs are different, the value of J at the next clock edge
is taken by the output Y. If both of its input is low, then no change occurs, and if high
at the clock edge, then from one state to the other, the output will be toggled. The JK
Flip Flop is a Set or Reset Flip flop in the digital system.

Truth Table:

D Flip Flop
D flip flop is a widely used flip flop in digital systems. The D flip flop is mostly used in
shift-registers, counters, and input synchronization.
Truth Table:

T Flip Flop
Just like JK flip-flop, T flip flop is used. Unlike JK flip flop, in T flip flop, there is only
single input with the clock input. The T flip flop is constructed by connecting both of
the inputs of JK flip flop together as a single input.

The T flip flop is also known as Toggle flip-flop. These T flip-flops are able to find
the complement of its state.

Truth Table:
SR Flip Flop
The SR flip flop is a 1-bit memory bistable device having two inputs, i.e., SET and
RESET. The SET input 'S' set the device or produce the output 1, and the RESET input
'R' reset the device or produce the output 0. The SET and RESET inputs are labeled
as S and R, respectively.

The SR flip flop stands for "Set-Reset" flip flop. The reset input is used to get back
the flip flop to its original state from the current state with an output 'Q'. This output
depends on the set and reset conditions, which is either at the logic level "0" or "1".

The NAND gate SR flip flop is a basic flip flop which provides feedback from both of
its outputs back to its opposing input. This circuit is used to store the single data bit
in the memory circuit. So, the SR flip flop has a total of three inputs, i.e., 'S' and 'R',
and current output 'Q'. This output 'Q' is related to the current history or state. The
term "flip-flop" relates to the actual operation of the device, as it can be "flipped" to
a logic set state or "flopped" back to the opposing logic reset state.

The NAND Gate SR Flip-Flop

We can implement the set-reset flip flop by connecting two cross-coupled 2-input
NAND gates together. In the SR flip flop circuit, from each output to one of the other
NAND gate inputs, feedback is connected. So, the device has two inputs, i.e., Set 'S'
and Reset 'R' with two outputs Q and Q' respectively. Below are the block diagram
and circuit diagram of the S-R flip flop.

Block Diagram:
Circuit Diagram:

The Set State

In the above diagram, when the input R is set to false or 0 and the input S is set to
true or 1, the NAND gate Y has an input 0, which will produce the output Q' 1. The
value of Q' is faded to the NAND gate 'X' as input 'A', and now both the inputs of the
NAND gate 'X' are 1(S=A=1), which will produce the output 'Q' 0.

Now, if the input R is changed to 1 with 'S' remaining 1, the inputs of NAND gate 'Y' is
R=1 and B=0. Here, one of the inputs is also 0, so the output of Q' is 1. So, the flip
flop circuit is set or latched with Q=0 and Q'=1.

Reset State
The output Q' is 0, and output Q is 1 in the second stable state. It is given by R =1
and S = 0. One of the inputs of NAND gate 'X' is 0, and its output Q is 1. Output Q is
faded to NAND gate Y as input B. So, both the inputs to NAND gate Y are set to 1,
therefore, Q' = 0.
Now, if the input S is changed to 0 with 'R' remaining 1, the output Q' will be 0 and
there is no change in state. So, the reset state of the flip flop circuit has been
latched, and the set/reset actions are defined in the following truth table:

From the above truth table, we can see that when set 'S' and reset 'R' inputs are set
to 1, the outputs Q and Q' will be either 1 or 0. These outputs depend on the input
state S or R before the input condition exist. So, when the inputs are 1, the states of
the outputs remain unchanged.

The condition in which both the inputs states are set to 0 is treated as invalid and
must be avoided.

JK Flip Flop
The SR Flip Flop or Set-Reset flip flop has lots of advantages. But, it has the following
switching problems:

o When Set 'S' and Reset 'R' inputs are set to 0, this condition is always avoided.
o When the Set or Reset input changes their state while the enable input is 1,
the incorrect latching action occurs.

The JK Flip Flop removes these two drawbacks of SR Flip Flop.

The JK flip flop is one of the most used flip flops in digital circuits. The JK flip flop is a
universal flip flop having two inputs 'J' and 'K'. In SR flip flop, the 'S' and 'R' are the
shortened abbreviated letters for Set and Reset, but J and K are not. The J and K are
themselves autonomous letters which are chosen to distinguish the flip flop design
from other types.

The JK flip flop work in the same way as the SR flip flop work. The JK flip flop has 'J'
and 'K' flip flop instead of 'S' and 'R'. The only difference between JK flip flop and SR
flip flop is that when both inputs of SR flip flop is set to 1, the circuit produces the
invalid states as outputs, but in case of JK flip flop, there are no invalid states even if
both 'J' and 'K' flip flops are set to 1.

The JK Flip Flop is a gated SR flip-flop having the addition of a clock input circuitry.
The invalid or illegal output condition occurs when both of the inputs are set to 1 and
are prevented by the addition of a clock input circuit. So, the JK flip-flop has four
possible input combinations, i.e., 1, 0, "no change" and "toggle". The symbol of JK flip
flop is the same as SR Bistable Latch except for the addition of a clock input.
Block Diagram:

Circuit Diagram:

In SR flip flop, both the inputs 'S' and 'R' are replaced by two inputs J and K. It means
the J and K input equates to S and R, respectively.
The two 2-input AND gates are replaced by two 3-input NAND gates. The third input
of each gate is connected to the outputs at Q and Q'. The cross-coupling of the SR
flip-flop permits the previous invalid condition of (S = "1", R = "1") to be used to
produce the "toggle action" as the two inputs are now interlocked.

If the circuit is "set", the J input is interrupted from the "0" position of Q' through the
lower NAND gate. If the circuit is "RESET", K input is interrupted from 0 positions of Q
through the upper NAND gate. Since Q and Q' are always different, we can use them
to control the input. When both inputs 'J' and 'K' are set to 1, the JK toggles the flip
flop as per the given truth table.

Truth Table:

When both of the inputs of JK flip flop are set to 1 and clock input is also pulse "High"
then from the SET state to a RESET state, the circuit will be toggled. The JK flip flop
work as a T-type toggle flip flop when both of its inputs are set to 1.

The JK flip flop is an improved clocked SR flip flop. But it still suffers from
the "race" problem. This problem occurs when the state of the output Q is changed
before the clock input's timing pulse has time to go "Off". We have to keep short
timing plus period (T) for avoiding this period.

D Flip Flop
In SR NAND Gate Bistable circuit, the undefined input condition of SET = "0" and
RESET = "0" is forbidden. It is the drawback of the SR flip flop. This state:

1. Override the feedback latching action.

2. Force both outputs to be 1.
3. Lose the control by the input, which first goes to 1, and the other input remains
"0" by which the resulting state of the latch is controlled.
We need an inverter to prevent this from happening. We connect the inverter
between the Set and Reset inputs for producing another type of flip flop circuit
called D flip flop, Delay flip flop, D-type Bistable, D-type flip flop.

The D flip flop is the most important flip flop from other clocked types. It ensures that
at the same time, both the inputs, i.e., S and R, are never equal to 1. The Delay flip-
flop is designed using a gated SR flip-flop with an inverter connected between the
inputs allowing for a single input D(Data).

This single data input, which is labeled as "D" used in place of the "Set" input and for
the complementary "Reset" input, the inverter is used. Thus, the level-sensitive D-
type or D flip flop is constructed from a level-sensitive SR flip flop.

So, here S=D and R= ~D(complement of D)

Block Diagram

Circuit Diagram

We know that the SR flip-flop requires two inputs, i.e., one to "SET" the output and
another to "RESET" the output. By using an inverter, we can set and reset the
outputs with only one input as now the two input signals complement each other. In
SR flip flop, when both the inputs are 0, that state is no longer possible. It is an
ambiguity that is removed by the complement in D-flip flop.

In D flip flop, the single input "D" is referred to as the "Data" input. When the data
input is set to 1, the flip flop would be set, and when it is set to 0, the flip flop would
change and become reset. However, this would be pointless since the output of the
flip flop would always change on every pulse applied to this data input.

The "CLOCK" or "ENABLE" input is used to avoid this for isolating the data input from
the flip flop's latching circuitry. When the clock input is set to true, the D input
condition is only copied to the output Q. This forms the basis of another sequential
device referred to as D Flip Flop.

When the clock input is set to 1, the "set" and "reset" inputs of the flip-flop are both
set to 1. So it will not change the state and store the data present on its output
before the clock transition occurred. In simple words, the output is "latched" at either
0 or 1.

Truth Table for the D-type Flip Flop

Symbols ↓ and ↑ indicates the direction of the clock pulse. D-type flip flop assumed
these symbols as edge-triggers.

T Flip Flop
In T flip flop, "T" defines the term "Toggle". In SR Flip Flop, we provide only a single
input called "Toggle" or "Trigger" input to avoid an intermediate state occurrence.
Now, this flip-flop work as a Toggle switch. The next output state is changed with the
complement of the present state output. This process is known as "Toggling"'.

We can construct the "T Flip Flop" by making changes in the "JK Flip Flop". The "T Flip
Flop" has only one input, which is constructed by connecting the input of JK flip flop.
This single input is called T. In simple words, we can construct the "T Flip Flop" by
converting a "JK Flip Flop". Sometimes the "T Flip Flop" is referred to as single input
"JK Flip Flop".

Block diagram of the "T-Flip Flop" is given where T defines the "Toggle input", and
CLK defines the clock signal input.
T Flip Flop Circuit
There are the following two methods which are used to form the "T Flip Flop":

o By connecting the output feedback to the input in "SR Flips Flop".

o We pass the output that we get after performing the XOR operation of T and
QPREV output as the D input in D Flip Flop.

Construction
The "T Flip Flop" is designed by passing the AND gate's output as input to the NOR
gate of the "SR Flip Flop". The inputs of the "AND" gates, the present output state Q,
and its complement Q' are sent back to each AND gate. The toggle input is passed to
the AND gates as input. These gates are connected to the Clock (CLK) signal. In the
"T Flip Flop", a pulse train of narrow triggers are passed as the toggle input, which
changes the flip flop's output state. The circuit diagram of the "T Flip Flop" using "SR
Flip Flop" is given below:

The "T Flip Flop" is formed using the "D Flip Flop". In D flip - flop, the output after
performing the XOR operation of the T input with the output "Q PREV" is passed as the
D input. The logical circuit of the "T-Flip Flop" using the "D Flip Flop" is given below:
The simplest construction of a D Flip Flop is with JK Flip Flop. Both the inputs of the
"JK Flip Flop" are connected as a single input T. Below is the logical circuit of the T
Flip Flop" which is formed from the "JK Flip Flop":

Truth Table of T Flip Flop

The upper NAND gate is enabled, and the lower NAND gate is disabled when the
output Q To is set to 0. make the flip flop in "set state(Q=1)", the trigger passes the
S input in the flip flop.

The upper NAND gate is disabled, and the lower NAND gate is enabled when the
output Q is set to 1. The trigger passes the R input in the flip flop to make the flip
flop in the reset state(Q=0).

Operations of T-Flip Flop

The next sate of the T flip flop is similar to the current state when the T input is set
to false or 0.
 o If toggle input is set to 0 and the present state is also 0, the next state will be
0.
o If toggle input is set to 0 and the present state is 1, the next state will be 1.

The next state of the flip flop is opposite to the current state when the toggle input is
set to 1.

o If toggle input is set to 1 and the present state is 0, the next state will be 1.
o If toggle input is set to 1 and the present state is 1, the next state will be 0.

The "T Flip Flop" is toggled when the set and reset inputs alternatively changed by
the incoming trigger. The "T Flip Flop" requires two triggers to complete a full cycle
of the output waveform. The frequency of the output produced by the "T Flip Flop" is
half of the input frequency. The "T Flip Flop" works as the "Frequency Divider
Circuit."

In "T Flip Flop", the state at an applied trigger pulse is defined only when the
previous state is defined. It is the main drawback of the "T Flip Flop".

The "T flip flop" can be designed from "JK Flip Flop", "SR Flip Flop", and "D Flip Flop"
because the "T Flip Flop" is not available as ICs. The block diagram of "T Flip Flop"
using "JK Flip Flop" is given below:

Master-Slave JK Flip Flop

In "JK Flip Flop", when both the inputs and CLK set to 1 for a long time, then Q output
toggle until the CLK is 1. Thus, the uncertain or unreliable output produces. This
problem is referred to as a race-round condition in JK flip-flop and avoided by
ensuring that the CLK set to 1 only for a very short time.

Explanation
The master-slave flip flop is constructed by combining two JK flip flops. These flip
flops are connected in a series configuration. In these two flip flops, the 1st flip flop
work as "master", called the master flip flop, and the 2nd work as a "slave", called
slave flip flop. The master-slave flip flop is designed in such a way that the output of
the "master" flip flop is passed to both the inputs of the "slave" flip flop. The output
of the "slave" flip flop is passed to inputs of the master flip flop.

In "master-slave flip flop", apart from these two flip flops, an inverter or NOT gate is
also used. For passing the inverted clock pulse to the "slave" flip flop, the inverter is
connected to the clock's pulse. In simple words, when CP set to false for "master",
then CP is set to true for "slave", and when CP set to true for "master", then CP is set
to false for "slave".

Registers
A Register is a collection of flip flops. A flip flop is used to store single bit digital
data. For storing a large number of bits, the storage capacity is increased by
grouping more than one flip flops. If we want to store an n-bit word, we have to use
an n-bit register containing n number of flip flops.

The register is used to perform different types of operations. For performing the
operations, the CPU use these registers. The faded inputs to the system will store
into the registers. The result returned by the system will store in the registers. There
are the following operations which are performed by the registers:

Fetch:
It is used

o To take the instructions given by the users.

o To fetch the instruction stored into the main memory.

Decode:
The decode operation is used to interpret the instructions. In decode, the operation
performed on the instructions is identified by the CPU. In simple words, the decode
operation is used to decode the instructions.

Execute:
The execution operation is used to store the result produced by the CPU into the
memory. After storing this result, it is displayed on the user screen.

Types of Registers
There are various types of registers which are as follows:

MAR or Memory Address Register

The MAR is a special type of register that contains the memory address of the data
and instruction. The main task of the MAR is to access instruction and data from
memory in the execution phase. The MAR stores the address of the memory location
where the data is to be read or to be stored by the CPU.

Program Counter
The program counter is also called an instruction address register or instruction
pointer. The next memory address of the instruction, which is going to be executed
after completing the execution of current instruction is contained in the program
counter. In simple words, the program counter contains the memory address of the
location of the next instruction.

Accumulator Register
The CPU mostly uses an accumulator register. The accumulator register is used to
store the system result. All the results will be stored in the accumulator register
when the CPU produces some results after processing.

MDR or Memory Data Register

Memory Data Register is a part of the computer's control unit. It contains the data
that we want to store in the computer storage or the data fetched from the computer
storage. The MDR works as a buffer that contains anything for which the processor is
ready to use it. The MDR contains the copied data of the memory for the processor.
Firstly the MDR holds the information, and then it goes to the decoder.

The data which is to be read out or written into the address location is contained in
the Memory Data Register.
The data is written in one direction when it is fetched from memory and placed into
the MDR. In write instruction, the data place into the MDR from another CPU register.
This CPU register writes the data into the memory. Half of the minimal interface
between the computer storage and the microprogram is the memory data address
register, and the other half is the memory data register.

Index Register
The Index Register is the hardware element that holds the number. The number
adds to the computer instruction's address to create an effective address. In CPU,
the index register is a processor register used to modify the operand address during
the running program.

Memory Buffer Register

Memory Buffer Register is mostly called MBR. The MBR contains the Metadata of the
data and instruction written in or read from memory. In simple words, it adds is used
to store the upcoming data/instruction from the memory and going to memory.

Data Register
The data register is used to temporarily store the data. This data transmits to or from
a peripheral device.

Working:

o When the clock pulse is true, the slave flip flop will be in the isolated state, and
the system's state may be affected by the J and K inputs. The "slave" remains
isolated until the CP is 1. When the CP set to 0, the master flip-flop passes the
information to the slave flip flop to obtain the output.
 o The master flip flop responds first from the slave because the master flip flop is
the positive level trigger, and the slave flip flop is the negative level trigger.
o The output Q'=1 of the master flip flop is passed to the slave flip flop as an
input K when the input J set to 0 and K set to 1. The clock forces the slave flip
flop to work as reset, and then the slave copies the master flip flop.
o When J=1, and K=0, the output Q=1 is passed to the J input of the slave. The
clock's negative transition sets the slave and copies the master.
o The master flip flop toggles on the clock's positive transition when the inputs J
and K set to 1. At that time, the slave flip flop toggles on the clock's negative
transition.
o The flip flop will be disabled, and Q remains unchanged when both the inputs
of the JK flip flop set to 0.

Timing Diagram of a Master Flip Flop:

o When the clock pulse set to 1, the output of the master flip flop will be one
until the clock input remains 0.
o When the clock pulse becomes high again, then the master's output is 0, which
will be set to 1 when the clock becomes one again.
 o The master flip flop is operational when the clock pulse is 1. The slave's output
remains 0 until the clock is not set to 0 because the slave flip flop is not
operational.
o The slave flip flop is operational when the clock pulse is 0. The output of the
master remains one until the clock is not set to 0 again.
o Toggling occurs during the entire process because the output changes once in
the cycle.

Shift Register
A group of flip flops which is used to store multiple bits of data and the data is
moved from one flip flop to another is known as Shift Register. The bits stored in
registers shifted when the clock pulse is applied within and inside or outside the
registers. To form an n-bit shift register, we have to connect n number of flip flops.
So, the number of bits of the binary number is directly proportional to the number of
flip flops. The flip flops are connected in such a way that the first flip flop's output
becomes the input of the other flip flop.

A Shift Register can shift the bits either to the left or to the right. A Shift Register,
which shifts the bit to the left, is known as "Shift left register", and it shifts the bit
to the right, known as "Right left register".

The shift register is classified into the following types:

o Serial In Serial Out

o Serial In Parallel Out
o Parallel In Serial Out
o Parallel In Parallel Out
o Bi-directional Shift Register
o Universal Shift Register

Serial IN Serial OUT

In "Serial Input Serial Output", the data is shifted "IN" or "OUT" serially. In SISO, a
single bit is shifted at a time in either right or left direction under clock control.

Initially, all the flip-flops are set in "reset" condition i.e. Y 3 = Y2 = Y1 = Y0 = 0. If we

pass the binary number 1111, the LSB bit of the number is applied first to the Din bit.
The D3 input of the third flip flop, i.e., FF-3, is directly connected to the serial data
input D3. The output Y3 is passed to the data input d2 of the next flip flop. This
process remains the same for the remaining flip flops. The block diagram of
the "Serial IN Serial OUT" is given below.

Block Diagram:

Operation
When the clock signal application is disabled, the outputs Y 3 Y2 Y1 Y0 = 0000. The LSB
bit of the number is passed to the data input D in, i.e., D3. We will apply the clock, and
this time the value of D3 is 1. The first flip flop, i.e., FF-3, is set, and the word is
stored in the register at the first falling edge of the clock. Now, the stored word is
1000.

The next bit of the binary number, i.e., 1, is passed to the data input D 2. The second
flip flop, i.e., FF-2, is set, and the word is stored when the next negative edge of the
clock hits. The stored word is changed to 1100.

The next bit of the binary number, i.e., 1, is passed to the data input D 1, and the
clock is applied. The third flip flop, i.e., FF-1, is set, and the word is stored when the
negative edge of the clock hits again. The stored word is changed to 1110.
Similarly, the last bit of the binary number, i.e., 1, is passed to the data input D 0, and
the clock is applied. The last flip flop, i.e., FF-0, is set, and the word is stored when
the clock's negative edge arrives. The stored word is changed to 1111.

Truth Table
Waveforms

Serial IN Parallel OUT

In the "Serial IN Parallel OUT" shift register, the data is passed serially to the flip
flop, and outputs are fetched in a parallel way. The data is passed bit by bit in the
register, and the output remains disabled until the data is not passed to the data
input. When the data is passed to the register, the outputs are enabled, and the flip
flops contain their return value

Below is the block diagram of the 4-bit serial in the parallel-out shift register. The
circuit having four D flip-flops contains a clear and clock signal to reset these four flip
flops. In SIPO, the input of the second flip flop is the output of the first flip flop, and
so on. The same clock signal is applied to each flip flop since the flip flops
synchronize each other. The parallel outputs are used for communication.

Block Diagram
Parallel IN Serial OUT
In the "Parallel IN Serial OUT" register, the data is entered in a parallel way, and
the outcome comes serially. A four-bit "Parallel IN Serial OUT" register is designed
below. The input of the flip flop is the output of the previous Flip Flop. The input and
outputs are connected through the combinational circuit. Through this combinational
circuit, the binary input B 0, B1, B2, B3 are passed. The shift mode and the load
mode are the two modes in which the "PISO" circuit works.

Load mode
The bits B0, B1, B2, and B3 are passed to the corresponding flip flops when the second,
fourth, and sixth "AND" gates are active. These gates are active when the shift or
load bar line set to 0. The binary inputs B0, B1, B2, and B3 will be loaded into the
respective flip-flops when the edge of the clock is low. Thus, parallel loading occurs.

Shift mode
The second, fourth, and sixth gates are inactive when the load and shift line set to 0.
So, we are not able to load data in a parallel way. At this time, the first, third, and
fifth gates will be activated, and the shifting of the data will be left to the right bit. In
this way, the "Parallel IN Serial OUT" operation occurs.

Block Diagram
Parallel IN Parallel OUT
In "Parallel IN Parallel OUT", the inputs and the outputs come in a parallel way in
the register. The inputs A0, A1, A2, and A3, are directly passed to the data inputs D 0,
D1, D2, and D3 of the respective flip flop. The bits of the binary input is loaded to the
flip flops when the negative clock edge is applied. The clock pulse is required for
loading all the bits. At the output side, the loaded bits appear.

Block Diagram

Bidirectional Shift Register

The binary number after shifting each bit of the number to the left by one position
will be equivalent to the number produced by multiplying the original number by 2.
In the same way, the binary number after shifting each bit of the number to the right
by one position will be equivalent to the number produced by dividing the original
number by 2.

For performing the multiplication and division operation using the shift register, it is
required that the data should be moved in both the direction, i.e., left or right in the
register. Such registers are called the "Bidirectional" shift register.

Below is the diagram of 4-bit "bidirectional" shift register where DR is the "serial
right shift data input", DL is the "left shift data input", and M is the "mode
select input".
Block Diagram

Operations
1) Shift right operation(M=1)

o The first, third, fifth, and seventh AND gates will be enabled, but the second,
fourth, sixth, and eighth AND gates will be disabled.
o The data present on the data input DR is shifted bit by bit from the fourth flip
flop to the first flip flop when the clock pulse is applied. In this way, the shift
right operation occurs.

2) Shift left operation(M=0)

o The second, fourth, sixth and eighth AND gates will be enabled, but the AND
gates first, third, fifth, and seventh will be disabled.
o The data present on the data input DR is shifted bit by bit from the first flip flop
to the fourth flip flop when the clock pulse is applied. In this way, the shift right
operation occurs.

Universal Shift Register

A register where the data is shifted in one direction is known as the "uni-
directional" shift register. A register in which the data is shifted in both the
direction is known as "bi-directional" shift register. A "Universal" shift register is a
special type of register that can load the data in a parallel way and shift that data in
both directions, i.e., right and left.

The input M, i.e., the mode control input, is set to 1 to perform the parallel loading
operation. If this input set to 0, then the serial shifting operation is performed. If we
connect the mode control input with the ground, then the circuit will work as a "bi-
directional" register. The diagram of the universal shift register is given below.
When the input is passed to the serial input, the register performs the "serial left"
operation. When the input is passed to the input D, the register performs the serial
right operation.

Block Diagram

Counters
A special type of sequential circuit used to count the pulse is known as a counter, or
a collection of flip flops where the clock signal is applied is known as counters.

The counter is one of the widest applications of the flip flop. Based on the clock
pulse, the output of the counter contains a predefined state. The number of the pulse
can be counted using the output of the counter.
Truth Table

There are the following types of counters:

o Asynchronous Counters
o Synchronous Counters

Asynchronous or ripple counters

The Asynchronous counter is also known as the ripple counter. Below is a
diagram of the 2-bit Asynchronous counter in which we used two T flip-flops. Apart
from the T flip flop, we can also use the JK flip flop by setting both of the inputs to 1
permanently. The external clock pass to the clock input of the first flip flop, i.e., FF-A
and its output, i.e., is passed to clock input of the next flip flop, i.e., FF-B.
Block Diagram

Signal Diagram
Operation

1. Condition 1: When both the flip flops are in reset condition.

Operation: The outputs of both flip flops, i.e., Q A QB, will be 0.
2. Condition 2: When the first negative clock edge passes.
Operation: The first flip flop will toggle, and the output of this flip flop will
change from 0 to 1. The output of this flip flop will be taken by the clock input
of the next flip flop. This output will be taken as a positive edge clock by the
second flip flop. This input will not change the second flip flop's output state
because it is the negative edge triggered flip flop.
So, QA = 1 and QB = 0
3. Condition 3: When the second negative clock edge is applied.
Operation: The first flip flop will toggle again, and the output of this flip flop
will change from 1 to 0. This output will be taken as a negative edge clock by
the second flip flop. This input will change the second flip flop's output state
because it is the negative edge triggered flip flop.
So, QA = 0 and QB = 1.
4. Condition 4: When the third negative clock edge is applied.
Operation: The first flip flop will toggle again, and the output of this flip flop
will change from 0 to 1. This output will be taken as a positive edge clock by
the second flip flop. This input will not change the second flip flop's output
state because it is the negative edge triggered flip flop.
So, QA = 1 and QB = 1
5. Condition 5: When the fourth negative clock edge is applied.
Operation: The first flip flop will toggle again, and the output of this flip flop
will change from 1 to 0. This output will be taken as a negative edge clock by
the second flip flop. This input will change the output state of the second flip
flop.
So, QA = 0 and QB = 0

Synchronous counters
In the Asynchronous counter, the present counter's output passes to the input of
the next counter. So, the counters are connected like a chain. The drawback of this
system is that it creates the counting delay, and the propagation delay also occurs
during the counting stage. The synchronous counter is designed to remove this
drawback.

In the synchronous counter, the same clock pulse is passed to the clock input of
all the flip flops. The clock signals produced by all the flip flops are the same as each
other. Below is the diagram of a 2-bit synchronous counter in which the inputs of the
first flip flop, i.e., FF-A, are set to 1. So, the first flip flop will work as a toggle flip-flop.
The output of the first flip flop is passed to both the inputs of the next JK flip flop.
Logical Diagram

Signal Diagram
Operation

1. Condition 1: When both the flip flops are in reset condition.

Operation: The outputs of both flip flops, i.e., Q A QB, will be 0.
So, QA = 0 and QB = 0
2. Condition 2: When the first negative clock edge passes.
Operation: The first flip flop will be toggled, and the output of this flip flop will
be changed from 0 to 1. When the first negative clock edge is passed, the
output of the first flip flop will be 0. The clock input of the first flip flop and both
of its inputs will set to 0. In this way, the state of the second flip flop will
remain the same.
So, QA = 1 and QB = 0
3. Condition 2: When the second negative clock edge is passed.
Operation: The first flip flop will be toggled again, and the output of this flip
flop will be changed from 1 to 0. When the second negative clock edge is
passed, the output of the first flip flop will be 1. The clock input of the first flip
flop and both of its inputs will set to 1. In this way, the state of the second flip
flop will change from 0 to 1.
So, QA = 0 and QB = 1
4. Condition 2: When the third negative clock edge passes.
Operation: The first flip flop will toggle from 0 to 1, but at this instance, both
the inputs and the clock input set to 0. Hence, the outputs will remain the
same as before.
So, QA = 1 and QB = 1
5. Condition 2: When the fourth negative clock edge passes.
Operation: The first flip flop will toggle from 1 to 0. At this instance, the inputs
and the clock input of the second flip flop set to 1. Hence, the outputs will
 change from 1 to 0.
So, QA = 0 and QB = 0

Ripple Counter
Ripple counter is a special type of Asynchronous counter in which the clock pulse
ripples through the circuit. The n-MOD ripple counter forms by combining n number
of flip-flops. The n-MOD ripple counter can count 2n states, and then the counter
resets to its initial value.

Features of the Ripple Counter:

o Different types of flip flops with different clock pulse are used.
o It is an example of an asynchronous counter.
o The flip flops are used in toggle mode.
o The external clock pulse is applied to only one flip flop. The output of this flip
flop is treated as a clock pulse for the next flip flop.
o In counting sequence, the flip flop in which external clock pulse is passed, act
as LSB.

Based on their circuitry design, the counters are classified into the following types:

Up Counter

The up-counter counts the states in ascending order.

Down Counter

The down counter counts the states in descending order.

Up-Down Counter
The up and down counter is a special type of bi-directional counter which counts the
states either in the forward direction or reverse direction. It also refers to a reversible
counter.

Binary Ripple Counter

A Binary counter is a 2-Mod counter which counts up to 2-bit state values, i.e., 22
= 4 values. The flip flops having similar conditions for toggling like T and JK are used
to construct the Ripple counter. Below is a circuit diagram of a binary ripple
counter.

In the circuit design of the binary ripple counter, two JK flip flops are used. The high
voltage signal is passed to the inputs of both flip flops. This high voltage input
maintains the flip flops at a state 1. In JK flip flops, the negative triggered clock pulse
use.

The outputs Q0 and Q1 are the LSB and MSB bits, respectively. The truth table of JK
flip flop helps us to understand the functioning of the counter.

When the high voltage to the inputs of the flip flops, the fourth condition is of the JK
flip flop occurs. The flip flops will be at the state 1 when we apply high voltage to the
input of the flip-flop. So, the states of the flip flops passes are toggled at the
negative going end of the clock pulse. In simple words, the flip flop toggle when the
clock pulse transition takes place from 1 to 0.
The state of the output Q0 change when the negative clock edge passes to the flip
flop. Initially, all the flip flops are set to 0. These flip flop changes their states when
the passed clock goes from 1 to 0. The JK flip flop toggles when the inputs of the flip
flops are one, and then the flip flop changes its state from 0 to 1. For all the clock
pulse, the process remains the same.

The output of the first flip flop passes to the second flip flop as a clock pulse. From
the above timing diagram, it is clear that the state of the second flip flop is changed
when the output Q0 goes transition from 1 to 0. The outputs Q 0 and Q1 treat as LSB
and MSB. The counter counts the values 00, 01, 10, 11. After counting these values,
the counter resets itself and starts counting again from 00, 01, 10, and 1. The count
values until the clock pulses are passed to J 0K0 flip flop.

Ring Counter
A ring counter is a special type of application of the Serial IN Serial OUT Shift
register. The only difference between the shift register and the ring counter is that
the last flip flop outcome is taken as the output in the shift register. But in the ring
counter, this outcome is passed to the first flip flop as an input. All of the remaining
things in the ring counter are the same as the shift register.

In the Ring counter

No. of states in Ring counter = No. of flip-flop used

Below is the block diagram of the 4-bit ring counter. Here, we use 4 D flip flops. The
same clock pulse is passed to the clock input of all the flip flops as a synchronous
counter. The Overriding input(ORI) is used to design this circuit.

The Overriding input is used as clear and pre-set.

The output is 1 when the pre-set set to 0. The output is 0 when the clear set to 0.
Both PR and CLR always work in value 0 because they are active low signals.

1. PR = 0, Q = 1
2. CLR = 0, Q = 0

These two values(always fixed) are independent with the input D and the Clock pulse
(CLK).

Working
The ORI input is passed to the PR input of the first flip flop, i.e., FF-0, and it is also
passed to the clear input of the remaining three flip flops, i.e., FF-1, FF-2, and FF-3.
The pre-set input set to 0 for the first flip flop. So, the output of the first flip flop is
one, and the outputs of the remaining flip flops are 0. The output of the first flip flop
is used to form the ring in the ring counter and referred to as Pre-set 1.
In the above table, the highlighted 1's are pre-set 1.

The Pre-set 1 is generated when

o ORI input set to low, and that time the Clk doesn't care.
o

o When the ORI input set to high, and the low clock pulse signal is passed as the
negative clock edge triggered.

A ring forms when the pre-set 1 is shifted to the next flip-flop at each clock pulse.

So, 4-bit counter, 4 states are possible which are as follows:

1. 1 0 0 0
2. 0100
3. 0 0 1 0
4. 0001

Types of Ring Counter

The ring counter is classified into two parts which are as follows:

Straight Ring Counter

The Straight Ring Counter refers to as One hot Counter. The outcome of the last
flip-flop is passed to the first flip-flop as an input. In the ring counter, the ORI input is
passed to the PR input for the first flip flop and to the clear input of the remaining flip
flops.

Note: The straight ring counter circulates the single 1 (or 0) bit around the ring.

Logic Diagram
Truth Table

Signal Diagram
Twisted Ring Counter
The Twisted Ring Counter refers to as a switch-tail ring Counter. Like
the straight ring counter, the outcome of the last flip-flop is passed to the first flip-
flop as an input. In the twisted ring counter, the ORI input is passed to all the flip
flops as clear input.

Note: The twisted ring counter circulates a stream of 1's followed by 0 around the ring.

Logic Diagram

Truth Table

Signal Diagram
johnson Counter
The Johnson counter is similar to the Ring counter. The only difference between
the Johnson counter and the ring counter is that the outcome of the last flip flop
is passed to the first flip flop as an input. But in Johnson counter, the inverted
outcome Q' of the last flip flop is passed as an input. The remaining work of
the Johnson counter is the same as a ring counter. The Johnson counter is also
referred to as the Creeping counter.

In Johnson counter

1. No. of states in Johnson counter = No. of flip-flop used

2. Number of used states=2n
3. Number of unused states=2n - 2*n

Below is the diagram of the 4-bit Johnson counter. Like Ring counter, four D flip flops
are used in the 4-bit Johnson counter, and the same clock pulse is passed to all the
input of the flip flops.

Truth Table

CP Q1 Q2 Q3 Q4
 0 0 0 0 0

1 1 0 0 0

2 1 1 0 0

3 1 1 1 0

4 1 1 1 1

5 0 1 1 1

6 0 0 1 1

7 0 1 1 1

The above table state that

o The counter produces the output 0000 when there is no clock input passed(0).
o The counter produces the output 1000 when the 1 st clock pulse is passed to the
flip flops.
o The counter produces the output 1100 when the 2 nd clock pulse is passed to
the flip flops.
o The counter produces the output 1110 when the 3 rd clock pulse is passed to
the flip flops.
o The counter produces the output 1111 when the 4 th clock pulse is passed to
the flip flops.
o The counter produces the output 0111 when the 5 th clock pulse is passed to
the flip flops.
o The counter produces the output 0011 when the 6 th clock pulse is passed to
the flip flops.
o The counter produces the output 0001 when the 7 th clock pulse is passed to
the flip flops.

Timing diagram

Advantages
 o The number of flip flops in the Johnson counter is equal to the number of flip
flops in the ring counter, and the Johnson counter counts twice the number of
states the ring counter can count.
o The Johnson counter can also be designed by using D or JK flip flop.
o The data is count in a continuous loop in the Johnson ring counter.
o The circuit of the Johnson counter is self-decoding.

Disadvantages

o The Johnson counter is not able to count the states in a binary sequence.
o In the Johnson counter, the unutilized states are greater than the states being
utilized.
o The number of flip flops is equal to one half of the number of timing signals.
o It is possible to design the Johnson counter for any number of timing
sequences.

Computer Memory
A computer is an electronic device that takes raw data as input and, processes it,
then provides the desired result. It has the potential to execute programmed
computations quickly and with great accuracy. Put in another way, the computer
receives input such as data and stores it together with instructions in memory (use
them when required). The data is then processed and converted into valuable
information. After that, it provides the result according to the inputs. Here, input
means the unprocessed data that we want the machine to handle and then give us a
response, and output refers to the outcome of the machine's processing of the
unprocessed data, which may include data analysis, searching, distributing, storing,
and more. Consequently, a computer is also referred to as a data processing system.
What is Memory?
The computer memory holds the data and instructions needed to process raw data
and produce output. It is the same as a human mind, where data, information, and
instructions are stored. It is a data storage device or a data storage component
where instructions for processing data are kept along with the data that has to be
processed. Both the input and the output can be held here.

The computer memory is divided into large number of small parts known as cells.
Each cell has a unique address which varies from 0 to memory size minus
one. Computer memory is of two types: Volatile (RAM) and Non-volatile (ROM). The
secondary memory (hard disk) is referred as storage not memory.

Characteristics of Main Memory:

o It serves as the computer's main memory.
o As compared to secondary memory, it is faster computer memory.
o Typically, it is a volatile memory.
o Without primary memory, a computer system cannot run.
o These memories are semiconductors.

But, if we categorize memory on behalf of space or location, it is of four types:

o Register memory
o Cache memory
o Primary memory
o Secondary memory
How does computer memory work?
A program is loaded from secondary memory to primary memory when it is opened.
There are several types of memory and storage, for example, a program being
moved from a solid-state drive (SSD) to RAM (Random Access Memory). The opened
software will be able to communicate with the computer's processor at a faster rate
because primary storage is accessed more quickly. The main or primary memory can
be accessed quickly from storage locations such as temporary memory slots.

Data in memory is only saved temporarily since memory is volatile. Data saved in
volatile memory will be erased immediately whenever a computer is turned off. A file
is transported to secondary memory for permanently storage when it is saved.

There are numerous kinds of memory present in a computer. Depending on the

primary memory utilized, it will perform differently, but semiconductor-based
memory is typically connected with memory. Integrated circuits utilizing metal-oxide-
semiconductor (MOS) transistors based on silicon will be used to make
semiconductor memory.

Types of computer memory

In general, memory can be classified into primary and secondary memory, however
even when just talking about primary memory, there are many different types of
memory. There are some examples of primary memory, such as follows:

o Cache memory: The cache, also known as a temporary storage area, is more
readily available to the processor as compared to the main memory source of
the computer system. It is mounted on a different chip that connects to the
CPU via a bus or is frequently built directly into the CPU chip; hence, it is also
known as CPU memory.
o RAM: The term refers to the fact that the processor can directly access any
storage location. Random Access Memory, or RAM, is a piece of hardware that
serves as the internal memory of the CPU. It is often found on a on the
motherboard of a computer. When the computer is turned on, it enables the
CPU to store programs, information, and result of the program. Also, it is a
computer's read-write memory, which means data can be added to it as well as
read from it.
o Dynamic RAM: A type of random-access memory that is used in computing
systems (primarily PCs) is called dynamic random-access memory (DRAM). The
data or program code required for a computer processor to operate is often
stored in DRAM, which is a kind of semiconductor memory. Each piece of data
is stored in DRAM in its own passive electrical component, which is located
inside an integrated circuit board. Each electrical component has two value
states, known as 0 and 1, in one bit.
 o Static RAM: As long as SRAM receives power, it keeps data bits in its memory.
It does not need to be refreshed on a regular basis, in contrast to DRAM, which
stores bits in cells made up of a capacitor and a transistor.
o Double Data Rate SDRAM: Theoretically, DDR SRAM can increase the
memory clock speed to at least 200 MHz. It is an SDRAM.
o Double Data Rate 4 Synchronous Dynamic RAM: DDR4 RAM is the
successor to its preceding DDR2 and DDR3 iterations. It is a kind of DRAM that
contains a high-bandwidth interface. Higher module density and lower voltage
requirements are both possible with DDR4 RAM. It enables dual in-line memory
modules (DIMMS) up to 64 GB; Also, higher data rate transfer speeds are
paired with it.
o Rambus Dynamic RAM: A memory component called DRDRAM made a
guarantee to transport up to 1.6 billion bytes per second. The RAM controller
subsystem consists of RAM, a bus connecting RAM to the microprocessor, and
computer-using devices that make up the subsystem.
o Read-only memory: ROM is often only read from and not written to, which is
a type of computer storage. It is nonvolatile in nature, which means it stores
data permanently. The programming code is stored in the ROM that enables a
computer system to boot up or regenerate every time when it is turned on.
o Programmable ROM: PROM is ROM that a user can modify only once. Using a
unique device known as a PROM programmer enables a user to customize a
microcode program.
o Erasable PROM: EPROM is a type of computer memory that can be erased
and re-used. It is programmable read-only memory PROM.
o Electrically erasable PROM: A user-modifiable ROM called an EEPROM can
be repeatedly wiped and reprogrammed with the help of an using electrical
voltage that is higher than usual. Unlike EPROM chips, EEPROMs can be
changed without being taken out of the computer. However, an EEPROM chip
must be completely deleted and reprogrammed, not just some parts of it.
o Virtual memory: A memory management method that enables the use of
secondary memory just like it was a component of main memory. In order to
compensate for physical memory shortages, virtual memory uses hardware
and software to temporarily shift data from RAM to disk storage.

Memory vs. Storage

Although the terms "memory" and "storage" are frequently used interchangeably,
there are some distinct and important differences between both. Simply said,
storage is secondary memory, while memory is primary or main memory. Storage
refers to where long-term data is stored, whereas memory refers to where short-
term data is stored.
On a computer, the term "memory" is most frequently used to describe the main
storage, such as RAM. Information is also processed in memory. With the help of
RAM, users have the potential to access data that is stored for a short time. As
primary memory is volatile, meaning it is not retained when the computer is shut off,
the data is only stored for a brief period of time.

Data in a computer is stored in secondary memory, which is referred to as storage. A

hard drive (HDD), often known as a hard disk drive, is an example of storage.
Because storage is nonvolatile, data is not lost even after the computer is powered
off and back on. For quick information retrieval, a running program may be in the
main memory of the computer, but when the program is closed, it moves to
secondary memory or storage.

The amount of storage and memory space that is accessible differs as well. As
compared to memory, a computer will often have greater storage capacity. For
instance, a laptop may have 250 GB of storage space and 8 GB of RAM. The reason
for the difference in space is that a computer will not need to quickly access all the
data stored on it at once; therefore, assigning about 8 GB of space will be plenty to
run programs.

Due to the inconsistent usage of this terminology in modern technology, memory

and storage can be difficult to understand. For instance, flash memory is a sort of
secondary storage, whereas RAM can be referred to as primary storage. It may be
simpler to talk about memory in terms of whether it is volatile or nonvolatile and
storage in terms of whether it is primary or secondary in order to avoid
misunderstanding.

What is Primary memory?

The primary memory of a PC system is its primary memory. The instructions that
must be performed at the time are copied to primary memory because the CPU may
directly access data from the primary memory. Accessing data from this memory is
faster because it is the internal memory, and the CPU accesses data from primary
memory via the data bus.

Primary memory is typically volatile in nature, which implies that information in

primary memory doesn't exist if the information is not stored in the event of a power
loss. It is more costly than secondary memory because it is made of semiconductors,
and primary memory capacity in a computer is restricted and is always less than
secondary memory.

Types of Primary Memory

RAM (Random Access Memory) and ROM (Read Only Memory) are the two
types of primary memory.

1. RAM (Random Access Memory)

RAM is both a read and writes type of memory. The information that has to be
currently processed is stored in RAM, which the CPU may immediately access. It is a
volatile memory that loses data when the electricity is turned off. RAM may be static
or dynamic in nature.

2. ROM (Read Only Memory)

ROM is a read-only memory, which implies that its contents may not be altered. It
contains the instructions that are executed when the system boots up. It is a non-
volatile memory, which implies that it preserves its contents even after the power is
turned off. It has three types of ROM, such as PROM, EPROM, and EEPROM.

 Question 13
Determine what input conditions are necessary to set, reset, and
toggle these two J-K flip-flops:

For the J-K flip-flop with active-high inputs:

Set by . . .
Reset by . . .
Toggle by . . .
For the J-K flip-flop with active-low inputs:
Set by . . .
Reset by . . .
Toggle by . . .
Hide Answer
In either case, you cause the flip-flop to go into these three modes by
doing the following:
Set by activating J, deactivating K, and clocking C.
Reset by activating K, deactivating J, and clocking C.
Toggle by activating J and K simultaneously, and clocking C.
 Specifically, though, here is what you would need to do to each flip-
flop, stated in terms of “high” and “low” logic states:
For the J-K flip-flop with active-high inputs:
Set by making J high, K low, and C transition from low to high.
Reset by making K high, J low, and C transition from low to high.
Toggle by making J high, K high, and C transition from low to high.
For the J-K flip-flop with active-low inputs:
Set by making K high, J low, and C transition from high to low.
Reset by making J high, K low, and C transition from high to low.
Toggle by making J low, K low, and C transition from high to low.
Notes:
This question reviews the basic modes of J-K flip-flops, as well as the significance
of active-low inputs.

 Question 17
Flip-flops often come equipped with asynchronous input lines as well
as synchronous input lines. This J-K flip-flop, for example, has both
“preset” and “clear” asynchronous inputs:

Describe the functions of these inputs. Why would we ever want to

use them in a circuit? Explain what the “synchronous” inputs are, and
why they are designated by that term.
Also, note that both of the asynchronous inputs are active-low. As a
rule, asynchronous inputs are almost always active-low rather than
active-high, even if all the other inputs on the flip-flop are active-high.
Why do you suppose this is?
Hide Answer
“Asynchronous” inputs force the outputs to either the “set” or “reset”
state independent of the clock. “Synchronous” inputs have control
over the flip-flop’s outputs only when the clock pulse allows.
 As for why the asynchronous inputs are active-low, I won’t directly
give you the answer. But I will give you a hint: consider
a TTL implementation of this flip-flop.
Notes:
Note to your students that sometimes the Preset and Clear inputs are called direct
set and direct reset, respectively. Review with your students what it means for an
input to be “active-low” versus “active-high.” Ask them what consequences might
arise if a circuit designer misunderstood the input states and failed to provide the
right type of signal to the circuit.

 Question 22
The flip-flop circuit shown here is classified as synchronous because
both flip-flops receive clock pulses at the exact same time:

Define the following parameters:

Set-up time
Hold time
Propagation delay time
Minimum clock pulse duration
Then, explain how each of these parameters is relevant in the circuit
shown.
Hide Answer
The clock frequency must be slow enough that there is adequate set-
up time before the next clock pulse. The propagation delay time of
FF1 must also be larger than the hold time of FF2. And, of course, the
pulse width of the clock signal must be long enough for both flip-flops
to reliably “clock.”
Notes:
I could have simply asked students to define the terms, but where’s the fun in
that? Seriously, though, these concepts will make far more sense to students
 when they are viewed in a practical context. After all, the whole purpose of
teaching these concepts is so students will be able to apply them, right?

 Question 24
Although the toggle function of the J-K flip-flop is one of its most
popular uses, this is not the only type of flip-flop capable of
performing a toggle function. Behold the surprisingly versatile D-type
flip-flop configured to do the same thing:

Explain how this circuit performs the “toggle” function more

commonly associated with J-K flip-flops.
Hide Answer
At each clock pulse, the flip-flop must switch to the opposite state
because D receives inverted feedback from [Q].
Notes:
The main purpose of this question is to get students to see that toggling is not the
exclusive domain of J-K flip-flops. This fact may be particularly handy to know if
one needs a toggle function in a circuit but only has a D-type flip-flop available,
not a J-K flip-flop.

 Question 16
Determine the output states for this J-K flip-flop, given the pulse
inputs shown:
 Hide Answer

Notes:
Ask students to identify those regions on the timing diagram where the flip-flop is
being set, reset, and toggled.

 Question 4
Determine the final output states over time for the following circuit,
built from D-type gated latches:
At what specific times in the pulse diagram does the final output
assume the input’s state? How does this behavior differ from the
normal response of a D-type latch?
Hide Answer

The final output assumes the same logic state as the input only when
the enable input signal (B) transitions from “high” to “low”.
Notes:
Note that by adding another latch, the overall behavior only slightly resembles the
behavior of a D-type latch. With the addition of the second latch, we’ve changed
this circuit into a flip-flop, specifically of the master-slave variety.