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Cache Memory
Chapter 4

Advanced Computer Architecture

Sheheryar Malik, Ph.D.

Advanced Computer Architecture

Cache Memory

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The Bottom Line

• How much memory?
o Capacity
• How fast memory?
o Time is money
• How much expensive?

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Memory Hierarchy List

• Registers
• L1 Cache
• L2 Cache
• L3 Cache
• Main memory
• Disk cache
• Disk
• Optical
• Tape

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So you want fast?

• It is possible to build a computer which uses only static RAM
• This would be very fast
• This would need no cache
o How can you cache cache?
• This would cost a very large amount

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Locality of Reference
• During the course of the execution of a program, memory references
tend to cluster
o e.g. Loops
• Spatial locality vs Temporal locality

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Cache
• Small amount of fast memory
• Sits between normal main memory and CPU
• May be located on CPU chip or module

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Cache and Main Memory

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Memory Hierarchy

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Cache/Main Memory Structure

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Cache Operation – Overview

• CPU requests contents of memory location
• Check cache for this data
• If present, get from cache (fast)
• If not present, read required block from main memory to cache
• Then deliver from cache to CPU
• Cache includes tags to identify which block of main memory is in each
cache slot

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Cache Read Operation - Flowchart

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Elements of Cache Design

• Addressing
• Size
• Mapping Function
• Replacement Algorithm
• Write Policy
• Block Size
• Number of Caches

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Cache Addressing
• Where does cache sit?
o Between processor and virtual memory management unit
o Between MMU and main memory

• Logical cache (virtual cache) stores data using virtual addresses

o Processor accesses cache directly, not thorough physical cache
o Cache access faster, before MMU address translation
o Virtual addresses use same address space for different applications
▪ Must flush cache on each context switch
• Physical cache stores data using main memory physical addresses

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Cache Addressing
• Virtual memory
o Facility that allows programs to address memory from a logical point of view,
without regard to the amount of main memory physically available
o When used, the address fields of machine instructions contain virtual
addresses
o For reads to and writes from main memory, a hardware memory
management unit (MMU) translates each virtual address into a physical
address in main memory

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Logical vs Physical Cache Addressing

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Cache Size Does Matter

• Cost
o More cache is expensive
• Speed
o More cache is faster (up to a point)
o Checking cache for data takes time

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Typical Cache Organization

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Comparison of Cache Sizes

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Mapping Function
• Because there are fewer cache lines than main memory blocks, an
algorithm is needed for mapping main memory blocks into cache lines
• Three techniques can be used
o Direct
▪ The simplest technique
▪ Maps each block of main memory into only one possible cache line
o Associative
▪ Permits each main memory block to be loaded into any line of the cache
▪ The cache control logic interprets a memory address simply as a Tag and a Word field
▪ To determine whether a block is in the cache, the cache control logic must simultaneously
examine every line’s Tag for a match
o Set Associative
▪ A compromise that exhibits the strengths of both the direct and associative approaches while
reducing their disadvantages

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Mapping Function
• Cache of 64kByte
• Cache block of 4 bytes
o i.e. cache is 16k (214) lines of 4 bytes
• 16MBytes main memory
• 24 bit address
o (224=16M)

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Direct Mapping
• Each block of main memory maps to only one cache line
o i.e. if a block is in cache, it must be in one specific place
• Address is in two parts
• Least Significant w bits identify unique word
• Most Significant s bits specify one memory block
• The MSBs are split into a cache line field r and a tag of s-r (most
significant)

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Direct Mapping
• Address length = (s + w) bits
• Number of addressable units = 2s+w words or bytes
• Block size line size = 2w words or bytes
• Number of blocks in main memory = 2s
• Number of lines in cache = m = 2r
• Size of cache = 2r+w words or bytes
• Size of tag = (s-r) bits

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Direct Mapping Address Structure

• 24 bit address
• 2 bit word identifier (4 byte block)
• 22 bit block identifier
o 8 bit tag (=22-14)
o 14 bit slot or line

• No two blocks in the same line have the same Tag field
• Check contents of cache by finding line and checking Tag

Tag s-r Line or Slot r Word w

8 14 2

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Direct Mapping
• Mapping method
• i = j modulo m
• where
o i cache line number
o j main memory block number
o m number of lines in the cache

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Direct Mapping from Cache to Main Memory

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Direct Mapping Cache Line Table

Cache line Main Memory blocks held

0 0, m, 2m, 3m…2s-m

1 1,m+1, 2m+1…2s-m+1

…
m-1 m-1, 2m-1,3m-1…2s-1

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Direct Mapping Cache Organization

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Direct Mapping Example

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Direct Mapping Summary

• Address length = (s + w) bits
• Number of addressable units = 2s+w words or bytes
• Block size = line size = 2w words or bytes
• Number of blocks in main memory = 2s+ w/2w = 2s
• Number of lines in cache = m = 2r
• Size of tag = (s – r) bits

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Direct Mapping Pros & Cons

• Simple
• Inexpensive
• Fixed location for given block
o If a program accesses 2 blocks that map to the same line repeatedly, cache
misses are very high

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Victim Cache
• Lower miss penalty
• Remember what was discarded
o Already fetched
o Use again with little penalty

• Fully associative
• 4 to 16 cache lines
• Between direct mapped L1 cache and next memory level

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(Fully) Associative Mapping

• A main memory block can load into any line of cache
• Memory address is interpreted as tag and word
• Tag uniquely identifies block of memory
• Every line’s tag is examined for a match
• Cache searching gets expensive

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Associative Mapping from Cache to Main Memory

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Fully Associative Cache Organization

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Associative Mapping Example

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Associative Mapping Address Structure

Tag 22 bit Word

2 bit

• 22 bit tag stored with each 32 bit block of data

• Compare tag field with tag entry in cache to check for hit
• Least significant 2 bits of address identify which 16 bit word is
required from 32 bit data block
• e.g.
o Address Tag Data Cache line
o FFFFFC FFFFFC 24682468 3FFF

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Associative Mapping Summary

• Address length = (s + w) bits
• Number of addressable units = 2s+w words or bytes
• Block size = line size = 2w words or bytes
• Number of blocks in main memory = 2s+ w/2w = 2s
• Number of lines in cache = undetermined
• Size of tag = s bits

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Set Associative Mapping

• Cache is divided into a number of sets
• Each set contains a number of lines
• A given block maps to any line in a given set
o e.g. Block B can be in any line of set i
• e.g. 2 lines per set
o 2 way associative mapping
o A given block can be in one of 2 lines in only one set

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Set Associative Mapping Example

• 13 bit set number
• Block number in main memory is modulo 213
• 000000, 00A000, 00B000, 00C000 … map to same set

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Mapping From Main Memory to Cache:

v Associative

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Mapping From Main Memory to Cache:

k-way Associative

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K-Way Set Associative Cache Organization

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Set Associative Mapping Address Structure

Word
Tag 9 bit Set 13 bit
2 bit

• Use set field to determine cache set to look in

• Compare tag field to see if we have a hit
• e.g
o Address Tag Data Set number
o 1FF 7FFC 1FF 12345678 1FFF
o 001 7FFC 001 11223344 1FFF

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Two Way Set Associative Mapping Example

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Set Associative Mapping Summary

• Address length = (s + w) bits
• Number of addressable units = 2s+w words or bytes
• Block size = line size = 2w words or bytes
• Number of blocks in main memory = 2d
• Number of lines in set = k
• Number of sets = v = 2d
• Number of lines in cache = kv = k * 2d
• Size of tag = (s – d) bits

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Direct and Set Associative Cache

Performance Differences
• Significant up to at least 64kB for 2-way
• Difference between 2-way and 4-way at 4kB much less than 4kB to
8kB
• Cache complexity increases with associativity
• Not justified against increasing cache to 8kB or 16kB
• Above 32kB gives no improvement

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Varying Associativity Over Cache Size

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Replacement Algorithms
• Once the cache has been filled, when a new block is brought into the
cache, one of the existing blocks must be replaced
• For direct mapping there is only one possible line for any particular
block and no choice is possible
• For the associative and set-associative techniques a replacement
algorithm is needed
• To achieve high speed, an algorithm must be implemented in
hardware

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Replacement Algorithms: Direct mapping

• No choice
• Each block only maps to one line
• Replace that line

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Replacement Algorithms: Associative & Set

Associative
• Hardware implemented algorithm (speed)
• Least Recently used (LRU)
o Most effective
o Replace that block in the set that has been in the cache longest with no reference to
it
o Because of its simplicity of implementation, LRU is the most popular replacement
algorithm
• First in first out (FIFO)
o Replace block that has been in cache longest
o Easily implemented as a round-robin or circular buffer technique
• Least frequently used
o replace block which has had fewest hits
• Random
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Write Policy
• Must not overwrite a cache block unless main memory is up to date
o Even if one write operation has been performed on a word in some line of the
cache then main memory must be updated by writing that line of cache out
to the block of memory before bringing in the new block
• Multiple CPUs may have individual caches
• I/O may address main memory directly
• Two cache write policies
o Write through
o Write back

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Write Through
• All writes go to main memory as well as cache
• Multiple CPUs can monitor main memory traffic to keep local (to CPU)
cache up to date
• Lots of traffic
• Slows down writes

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Write Back
• Updates initially made in cache only
• Update bit for cache slot is set when update occurs
• If block is to be replaced, write to main memory only if update bit is
set
• Other caches get out of sync
• I/O must access main memory through cache
• 15% of memory references are writes

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Line Size
• Retrieve not only desired word but a number of adjacent words as well
• Increased block size will increase hit ratio at first
o the principle of locality
• Hit ratio will decreases as block becomes even bigger
o Probability of using newly fetched information becomes less than probability of
reusing replaced
• Larger blocks
o Reduce number of blocks that fit in cache
o Data overwritten shortly after being fetched
o Each additional word is less local so less likely to be needed
• No definitive optimum value has been found
• 8 to 64 bytes seems reasonable
• For HPC systems, 64 and 128 bytes most common

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Multilevel Caches
• High logic density enables caches on chip
o The on-chip cache reduces the processor’s external bus activity and speeds up
execution time and increases overall system performance
o Faster than bus access
o Frees bus for other transfers
• Common to use both on and off chip cache
o L1 on chip, L2 off chip in static RAM
o L2 access much faster than DRAM or ROM
o L2 often uses separate data path
o L2 may now be on chip
o Resulting in L3 cache
• The use of multilevel caches complicates all of the design issues related to
caches, including size, replacement algorithm, and write policy

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Unified v Split Caches

• Unified cache
o One cache for data and instructions
• Split cache
o Two separate caches, one for data and one for instructions
• Advantages of unified cache
o Higher hit rate
▪ Balances load of instruction and data fetch
▪ Only one cache to design & implement
• Advantages of split cache
o Eliminates cache contention between instruction fetch/decode unit and
execution unit
▪ Important in pipelining
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Pentium 4 Cache
• 80386 – no on chip cache
• 80486 – 8k using 16 byte lines and four way set associative organization
• Pentium (all versions) – two on chip L1 caches
o Data & instructions
• Pentium III – L3 cache added off chip
• Pentium 4
o L1 caches
▪ 16k bytes each
▪ 64 byte lines
▪ four way set associative
o L2 cache
▪ Feeding both L1 caches
▪ 256kB
▪ 128 byte lines
▪ 8 way set associative
o L3 cache on chip

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Intel Cache Evolution

Problem Solution Processor on
which feature
first appears
External memory slower than the system bus Add external cache using faster memory 386
technology
Increased processor speed results in external bus Move external cache on-chip, operating at the 486
becoming a bottleneck for cache access same speed as the processor
Internal cache is rather small, due to limited Add external L2 cache using faster technology 486
space on chip than main memory
Contention occurs when both the Instruction Create separate data and instruction caches Pentium
Prefetcher and the Execution Unit
simultaneously require access to the cache. In
that case, the Prefetcher is stalled while the
Execution Unit’s data access takes place
Increased processor speed results in external bus Create separate back-side bus that runs at higher Pentium Pro
becoming a bottleneck for L2 cache access speed than the main (front-side) external bus.
The BSB is dedicated to the L2 cache
Move L2 cache on to the processor chip Pentium II
Some applications deal with massive databases Add external L3 cache Pentium III
and must have rapid access to large amounts of
Move L3 cache on-chip Pentium 4
data. The on-chip caches are too small
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Pentium 4 Block Diagram

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Pentium 4 Core Processor

• Fetch/Decode Unit
o Fetches instructions from L2 cache
o Decode into micro-ops
o Store micro-ops in L1 cache
• Out of order execution logic
o Schedules micro-ops
o Based on data dependence and resources
o May speculatively execute
• Execution units
o Execute micro-ops
o Data from L1 cache
o Results in registers
• Memory subsystem
o L2 cache and systems bus

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Pentium 4 Design Reasoning

• Decodes instructions into RISC like micro-ops before L1 cache
• Micro-ops fixed length
o Superscalar pipelining and scheduling
• Pentium instructions long & complex
• Performance improved by separating decoding from scheduling & pipelining
• Data cache is write back
o Can be configured to write through
• L1 cache controlled by 2 bits in register
o CD = cache disable
o NW = not write through
o 2 instructions to invalidate (flush) cache and write back then invalidate
• L2 and L3 8-way set-associative
o Line size 64-128 bytes

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ARM Cache Features

Core Cache Cache Size (kB) Cache Line Associativity Location Write Buffer
Type Size (words) Size (words)

ARM720T Unified 8 4 4-way Logical 8

ARM920T Split 16/16 D/I 8 64-way Logical 16
ARM926EJ-S Split 4-128/4-128 8 4-way Logical 16
D/I
ARM1022E Split 16/16 D/I 8 64-way Logical 16
ARM1026EJ-S Split 4-128/4-128 8 4-way Logical 8
D/I
Intel StrongARM Split 16/16 D/I 4 32-way Logical 32

Intel Xscale Split 32/32 D/I 8 32-way Logical 32

ARM1136-JF-S Split 4-64/4-64 D/I 8 4-way Physical 32

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ARM Cache Organization

• Small FIFO write buffer
o Enhances memory write performance
o Between cache and main memory
o Data put in write buffer at processor clock speed
o Processor continues execution
o External write in parallel until empty
o If buffer full, processor stalls
o Data in write buffer not available until written
▪ So keep buffer small

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ARM Cache and Write Buffer Organization

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