IFT 211 — DIGITAL LOGIC DESIGN

Complete Exam Solutions with Circuit Diagrams

University of Ilesa | Questions 1–4

QUESTION ONE

(a) Full Adder — Truth Table & Logic Circuit

A Full Adder adds three inputs: A, B, and Cin (carry-in), producing Sum (S) and Carry-out (Cout).

Boolean expressions: S = A ⊕ B ⊕ Cin | Cout = AB + BCin + ACin

A B Cin Sum (S) Cout

0 0 0 0 0

0 0 1 1 0

0 1 0 1 0

0 1 1 0 1

1 0 0 1 0

1 0 1 0 1

1 1 0 0 1

1 1 1 1 1

Full Adder Logic Circuit Diagram

FULL ADDER Logic Circuit

A
XOR XOR S (Sum)
B
Cin

AND AND
OR Cout

Half Adder 1 Half Adder 2

★ Two Half Adders (each = XOR + AND) plus one OR gate = Full Adder

(b) D Flip-Flop — Operation & Symbol

The D (Data) Flip-Flop captures the value at input D on the rising clock edge and holds it at output Q
until the next clock edge. It eliminates the forbidden state of SR FF.
 CLK Edge D Q (next) State

↑ Rising 0 0 Reset

↑ Rising 1 1 Set

No edge X Q (hold) Memory

D Flip-Flop Block Symbol

D FLIP-FLOP — Block Symbol

D D D FF Q Q

CLK Q' Q'

On rising CLK edge: Q ← D

(c) BCD 0110 1000 0011 1001 → Decimal

BCD Group Binary Decimal Digit

Group 1 0110 6

Group 2 1000 8

Group 3 0011 3

Group 4 1001 9

∴ 0110 1000 0011 1001 (BCD) = 6839 (Decimal)

(d) Simplify z = A + B·C using De Morgan's Theorem

De Morgan's Laws: NOT(A+B) = ■·B■ | NOT(A·B) = ■+B■

Step 1: Take complement of z:

z■ = NOT(A + B·C) = ■ · NOT(B·C) [Law 1]
= ■ · (B■ + C■) [Law 2]
= ■·B■ + ■·C■ [Distributive]

Step 2: Complement both sides to get z:

z = NOT(■·B■ + ■·C■) = (A+B)·(A+C) [De Morgan + Double Negation]

∴ z = A + B·C ≡ (A + B)·(A + C)
★ Verify: (A+B)·(A+C) = A + BC ✓ (by Distributive Law)
 QUESTION TWO

(a) Operation of a Multiplexer

A Multiplexer (MUX) is a combinational circuit that selects one of 2n data inputs and routes it to a single
output using n select lines.

A 4-to-1 MUX has 4 data inputs (I0–I3), 2 select lines (S1, S0), and 1 output Y.
Y = S■1·S■0·I0 + S■1·S0·I1 + S1·S■0·I2 + S1·S0·I3

(b) 4-to-1 MUX — Truth Table & Logic Circuit

S1 S0 Selected Input Output Y

0 0 I0 Y = I0

0 1 I1 Y = I1

1 0 I2 Y = I2

1 1 I3 Y = I3

4-to-1 Multiplexer Logic Circuit Diagram

4-to-1 MULTIPLEXER Logic Circuit

I0
S1 NOT AND

I1
S0 NOT
AND
OR Y (Output)

I2
AND

I3
AND

★ Each AND gate enables one input; OR gate combines all — only the selected AND passes its input.

(c) 2's Complement of 111001

Step 1 — Original: 1 1 1 0 0 1
Step 2 — 1's complement (flip all): 0 0 0 1 1 0
Step 3 — Add 1:

000110
+ 1
■■■■■■■■■■■■■■
000111
∴ 2's complement of 111001 = 000111

(d) 3-Input OR & AND Gates — Symbols & Truth Tables

Logic Gate Symbols

Logic Gate Symbols

3-input OR Gate 3-input AND Gate

A A

B OR Y=A+B+C B AND Y=A·B·C

C C

A B C Y=A+B+C A B C Y=A·B·C

0 0 0 0 0 0 0 0

0 0 1 1 0 0 1 0

0 1 0 1 0 1 0 0

0 1 1 1 0 1 1 0

1 0 0 1 1 0 0 0

1 0 1 1 1 0 1 0

1 1 0 1 1 1 0 0

1 1 1 1 1 1 1 1

★ OR: output = 0 only when ALL inputs = 0. AND: output = 1 only when ALL inputs = 1.
 QUESTION THREE

(a) Shift Register Operation — X transfers serially into Y

Two 3-bit registers X and Y are connected so contents of X shift into Y bit by bit, MSB first, on each clock
pulse. Initial state: X = 101, Y = 000.

Clock Pulse X Register Y Register Bit Transferred

Initial 101 000 —

Pulse 1 010 100 1 (MSB of X)

Pulse 2 001 010 0

Pulse 3 000 101 1 (LSB of X)

After 3 pulses: X = 000 (emptied), Y = 101 (full copy of original X). This is a Serial-In Serial-Out (SISO)
shift register. Each register uses D flip-flops clocked in synchrony.

(b) Number Conversions

(i) 11010.10112 → Octal — Group bits in 3s from binary point:

Integer: 0 1 1 | 0 1 0 → 3 2 Fraction: 1 0 1 | 1 0 0 → 5 4 (pad right with zeros for
fraction)

∴ 11010.1011■ = 32.54■

(ii) 24.68 → Decimal

2 × 81 + 4 × 80 + 6 × 8-1
= 16 + 4 + 0.75

∴ 24.6■ = 20.75■■

(iii) 25.37510 → Binary

Integer 25 (÷ 2 repeatedly, read remainders upward):

25÷2=12 r1, 12÷2=6 r0, 6÷2=3 r0, 3÷2=1 r1, 1÷2=0 r1
→ 11001

Fraction 0.375 (×2 repeatedly, read integer parts downward):

0.375×2=0.75 → 0, 0.75×2=1.5 → 1, 0.5×2=1.0 → 1
→ .011

∴ 25.375■■ = 11001.011■
★ Check: 16+8+1 = 25 ✓ and 0+0.25+0.125 = 0.375 ✓
 QUESTION FOUR

(a) SR Flip-Flop using NOR Gates — Circuit & Truth Table

SR Flip-Flop (NOR Gate Implementation)

SR FLIP-FLOP using NOR Gates

Q' (feedback to NOR1)

S
NOR1 Q

NOR2 Q'
R

Q (feedback to NOR2)

S R Q (next) Q' (next) State

0 0 Q (hold) Q' Memory — no change

0 1 0 1 Reset — Q = 0

1 0 1 0 Set — Q = 1

1 1 INVALID INVALID Forbidden state!

★ S=R=1 is forbidden because both outputs try to go to 0, violating Q ≠ Q'.

(a cont.) NAND Gate Implementations of NOT, AND, OR

Universal NAND Gate Diagrams

Universal NAND Gate Implementations

(i) NOT Gate (iii) OR Gate
A NAND
A NAND A' (NOT A)
NAND A+B
B NAND
(ii) AND Gate

A NAND NAND A·B (AND)

B

★ NAND is a universal gate — any logic function can be built from NAND gates alone (same for NOR).

(b) Convert 46 to Excess-3 (XS-3) Code

Rule: Add 3 to each BCD digit, then express in 4-bit binary.

Decimal 46 → digits are 4 and 6

Digit +3 Result XS-3 Binary

4 4+3 7 0111

6 6+3 9 1001

∴ Excess-3 code of 46 = 0111 1001

★ XS-3 is self-complementing: flip all bits of any digit to get the 9's complement — useful in BCD subtraction.

(c) Evaluate x = [D + (A + B)·C] · E

Given: A=0, B=0, C=1, D=1, E=1

Step 1: A + B = 0 + 0 = 0
Step 2: (A+B) · C = 0 · 1 = 0
Step 3: D + (A+B)·C = 1 + 0 = 1
Step 4: [D + (A+B)·C] · E = 1 · 1 = 1

∴ x = 1 (Output is Logic HIGH)

★ D=1 dominates the OR in Step 3, making the bracket = 1; E=1 keeps the final AND = 1.

IFT 211 Digital Logic Design | University of Ilesa | All Diagrams Included
Read the circuits, trace the wires, understand every gate — you go shine! ■■