.

DHANALAKSHMI SRINIVASAN UNIVERSITY

Thuraiyur Road, Perambalur – 621 212, Tamil Nadu.

SCHOOL OF ENGINEERING AND TECHNOLOGY

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

MANUAL CUM OBSERVATION

SUBJECT CODE/NAME: 24ECE409/ VLSI DESGIN LABORATORY

YEAR/SEM: II ECE / IV SEM

 INDEX

EXP. PAGE
NO. DATE NAME OF THE EXPERIMENT NO. MARK SIGN

1 Simulation of NMOS and PMOS transistors

using SPICE.
2 Stick diagram and layout of a CMOS inverter
using CAD tools.
3 Design and simulation of CMOS NAND,
NOR, and XOR gates in Verilog/VHDL.
4 Timing analysis of static CMOS logic gates.
5 CMOS logic layout design of basic gates
using CAD tools.

6 Design Rule Checking (DRC) of a 2-input

CMOS NAND gate layout.

7 Design and simulation of Ripple Carry

Adder and Carry Look-Ahead Adder using
Verilog/VHDL.

8 SRAM cell design and simulation using

Verilog.

9 Low power analysis for arithmetic circuits

and memory designs using Verilog/VHDL.

10 HDL coding and FPGA synthesis of a simple

digital circuit, followed by implementation
on FPGA

Page 2 of 28
 [Link]:
Design and simulation of CMOS NAND, NOR, and XOR gates in
DATE:
Verilog/VHDL.

AIM:
To implement Logic gates using the Xilinx ISE12.1i software tool.

TOOLS REQUIRED:
Software: Xilinx ISE12.1i software tool.

SIMULATION PROCEDURE:
1. Double click on Xilinx ISE12.1i icon on the desktop.
2. Create a new project by clicking file->new project.

3. Change the family to Spartan3E, device to XC3S500E, package to FT256 and speed to -4.

4. Now choose Verilog module in new source and give the same filename. Enter the input and output
ports.
5. Select the file and type the program and save. Select synthesize XST ->Check syntax

6. Go to behavioral simulation select the filename and then select Modelsim simulator.
 7. Open the wave window and force the inputs and start the simulation using RUN icon for the
output.

TESTBENCH PROCEDURE:
1. Up to check syntax same procedure
2. Select the Verilog file->right click->select new source->Verilog module-> filename
3. Type the test bench program-> Select synthesize XST ->Check syntax
4. Go to behavioral simulation select the test bench filename and then select Modelsim simulator.
5. Without forcing the inputs the simulation waveform is obtained.
Spartan3E kit procedure:
1. The same procedure is repeated till check syntax.
2. Now select the Verilog file->right click->new source->implementation constraints file.
 3. Give a new filename and click until finish.
4. A ucf file is created (user constraints file) and select the ucf file
Select user constraints->assign package pins->Xilinx PACE window is opened. Enter the pins numbers
and save it.
 5. Select the Verilog file. Select implement design->Translate->Map->Place and Route

6. Select Generate programming file->Configure device (iMPACT)

7. Configure window opens click finish. Switch on the kit. Select the bit file
8. Select the device-> right click ->select program->ok

9. Program will get downloaded to the kit and for the corresponding input output is taken
PROGRAM FOR BASIC GATES USING GATE LEVEL MODELING:

AND GATE: BUF GATE:

module and1(c, a, b); module buf1(y, a)

output c; output c;
input a; input a;
input b; buf(c,a);
and(c,a,b); end module
endmodule

OR GATE XOR GATE:

module or1(c, a, b); module xor1(c, a, b);

output c; output c;
input a; input a;
input b; input b;
or(c,a,b); xor(c,a,b);
endmodule endmodule

NOT GATE: XNOR GATE:

module not1(y, a); module xnor1(c,a,b);

output y; output c;
input a; input a;
not(y,a); input b;
endmodule xnor(c,a,b);
endmodule

NAND GATE:
module nand1(c, a, b);
output c;
input a;
input b;
nand(c,a,b);
endmodule

NOR GATE:
module nor1(c, a, b);
output c;
input a;
input b;
nor(c,a,b);
endmodule
PROGRAM FOR BASIC GATES USING DATA FLOW MODELING:

AND GATE: BUF GATE:

module and1(c, a, b); module buf1(y, a);

output c; output c;
input a; input a;
input b; assign c=a;
assign c=a&b; end module
endmodule

OR GATE: XOR GATE:

module or1(c, a, b); module xor1(c, a, b);

output c; output c;
input a; input a;
input b; input b;
assign c=a|b; assign c=a^b;
endmodule endmodule

NOT GATE: XNOR GATE:

module not1(y, a); module xnor1(c,a,b);

output y; output c;
input a; input a;
assign c=~a; input b;
endmodule assign c=a~^b;
endmodule
NAND GATE:
module nand1(c, a, b);
output c;
input a;
input b;
assign c=a~&b;
endmodule

NOR GATE:
module nor1(c, a, b);
output c;
input a;
input b;
assign c=a~|b;
endmodule

TEST BENCH PROGRAM:

AND GATE: NAND GATE:
module testbench(); module testbench();
reg a,b; reg a,b;
wire c; wire c;
and1 x1(c,a,b); nand1 x1(c,a,b);
initial I nitial
begin begin
a=0; b=0; a=0; b=0;
#10 a=0; b=1; #10 a=0; b=1;
#10 a=1; b=0; #10 a=1; b=0;
#10 a=1; b=1; #10 a=1; b=1;
end end
initial initial
$monitor($time,"a=%b\t b=%b\t c=%b\t",a,b,c); $monitor($time,"a=%b\t b=%b\t c=%b\t",a,b,c);
Initial initial
#60 $finish; #60 $finish;
endmodule endmodule

OR GATE: NOR GATE:

module testbench(); module testbench();
reg a,b; reg a,b;
wire c; wire c;
or1 x1(c,a,b); nor1 x1(c,a,b);
initial initial
begin begin
a=0; b=0; a=0; b=0;
#10 a=0; b=1; #10 a=0; b=1;
#10 a=1; b=0; #10 a=1; b=0;
#10 a=1; b=1; #10 a=1; b=1;
end end
initial initial
$monitor($time,"a=%b\t b=%b\t c=%b\t",a,b,c); $monitor($time,"a=%b\t b=%b\t c=%b\t",a,b,c);
Initial initial
#60 $finish; #60 $finish;
endmodule endmodule

NOT GATE: BUF GATE:

module testbench(); module testbench();
reg a; reg a;
wire c; wire c;
not11 x1(c,a); buf11 x1(c,a);
initial initial
begin begin
a=0; a=0;
#10 a=0; #10 a=0;
#10 a=1; #10 a=1;
end end
initial initial
$monitor($time,"a=%b\t c=%b\t",a,c); $monitor($time,"a=%b\t c=%b\t",a,c);
Initial initial
#60 $finish; #60 $finish;
endmodule endmodule

XOR GATE: XNOR GATE:

module testbench(); module testbench();
reg a,b; reg a,b;
wire c; wire c;
xor1 x1(c,a,b); xnor1 x1(c,a,b);
initial initial
begin begin
a=0; b=0; a=0; b=0;
#10 a=0; b=1; #10 a=0; b=1;
#10 a=1; b=0; #10 a=1; b=0;
#10 a=1; b=1; #10 a=1; b=1;
end end
initial initial
$monitor($time,"a=%b\t b=%b\t c=%b\t",a,b,c); $monitor($time,"a=%b\t b=%b\t c=%b\
t",a,b,c);
Initial initial
#60 $finish; #60 $finish;
endmodule endmodule

OUPUT WAVEFORM:
AND GATE:
 OR GATE:

NOT GATE:

NAND GATE:

NOR GATE:

XOR GATE:

XNOR GATE:

BUF GATE:

RESULT:
Thus, the CMOS basic gates was designed using micro wind and thereby performed the automatic layout
compaction.
Exp. No.: DESIGN AND SIMULATE A CMOS BASIC GATES GENERATE
MANUAL/AUTOMATIC LAYOUT.

AIM:

To design and simulate the CMOS basic gates using DSCH and micro wind.
TOOLS REQUIRED:

 Microwind DSCH
 Microwind 2.0

PROCEDURE:
1. Open DSCH 2 and create a new file
2. Using symbol library drag and drop the circuit elements on the workspace
3. Make the circuit connections using “add a line”
4. Use button as input for enable and light as output
5. Save and simulate the design, simulation control can be adjusted for operating speed
6. View the timing diagram for functional verification
7. From the file menu use “make Verilog file” for the schematic and save the file, this is used to
generate the layout
8. Observe the DC, transient responses
9. Open Micro wind 2.0 and create a new file.
10. From menu-compile-compile Verilog file and select the Verilog file created for the design
- Generate and back to editor, the layout will be created automatically

CMOS NAND
GATE
SCHEMATIC
LAYOUT GENERATION

OUTPUT WAVEFORM

CMOS NOR GATE

SCHEMATIC
LAYOUT GENERATION

OUTPUT WAVEFORM
 RESULT:
Thus, the CMOS basic gates was designed using micro wind and thereby performed the automatic layout
compaction.
Exp. No.: Design and simulation of Ripple Carry Adder and Carry Look-Ahead Adder using
Verilog/VHDL.

AIM:
To using the Design and simulation of Ripple Carry Adder and Carry
Look-Ahead Adder using Verilog/VHDL in Xilinx ISE12.1i software
tool.

APPARATUS REQUIRED:
 Pc With Windows Xp.
 Xilinx 12.1 Software
 Fpga-Spartan-3 Kit
 Parallel to JTAG Cable

PROCEDURE:
1. Start the Xilinx ISE by using Start>Program files> Xilinx ISE>project
navigator
2. Click File>New Project
3. Enter the Project Name and select the location then click next
4. Select the Device and other category and click next twice and finish.
5. Click on the symbol of FPGA device and then right click>click on new
source.
6. Select the Verilog Module and give the filename>click next and define
ports>click next and finish.
7. Type the Verilog Code in Verilog Editor.
8. Run the Check syntax>Process window >synthesize>double click
check syntax. If any errors found, then remove the errors with proper syntax
&coding.
9. Click on the symbol of FPGA device and then right click>click on new
source.
10. Select the Test Bench Waveform and give the filename>select entity
click next and finish.
11. Select the desired parameters for simulating your design. In this case
combinational circuit and simulation time click [Link] all input signal
using just click on graph and save file.
12. From the source process window. Click Behavioral simulation from
drop-down menu
13. Select the test bench file (. tbw) and click process button>double click
the Simulation Behavioral Model
14. Verify your design in wave window by seeing behavior of output
signal with respect to input signal.
15. To assign package pins using corresponding CPLD manual via using
constraint.
16. Assign package pins.
17. The pace file opened and give the pin details.
 18. Go Implement design and generate the programming file and
configure the device (impact).
19. In configure device choose JTAG options and add the Xilinx device in
boundary scan and download the program and execute successfully.
THEORY :

 Ripple Carry Adder (RCA):

Carry propagates sequentially from LSB → MSB.
 Carry Look-Ahead Adder (CLA):
Uses generate (G) and propagate (P) signals.

PROGRAM CODE :

module ripple_carry_adder (
input [3:0] A, B,
input Cin,
output [3:0] Sum,
output Cout
);

wire c1, c2, c3;

assign {c1, Sum[0]} = A[0] + B[0] + Cin;

assign {c2, Sum[1]} = A[1] + B[1] + c1;
assign {c3, Sum[2]} = A[2] + B[2] + c2;
assign {Cout, Sum[3]} = A[3] + B[3] + c3;

endmodule
PROGRAM CODE :

module carry_lookahead_adder (
input [3:0] A, B,
input Cin,
output [3:0] Sum,
output Cout
);

wire [3:0] P, G;
wire C1, C2, C3;

assign P = A ^ B;
assign G = A & B;

assign C1 = G[0] | (P[0] & Cin);

assign C2 = G[1] | (P[1] & C1);
assign C3 = G[2] | (P[2] & C2);
assign Cout = G[3] | (P[3] & C3);

assign Sum[0] = P[0] ^ Cin;

assign Sum[1] = P[1] ^ C1;
assign Sum[2] = P[2] ^ C2;
assign Sum[3] = P[3] ^ C3;

endmodule
 RESULT:

Thus, the simulation of basic combinational and sequential circuits using Verilog
HDL was performed and output was verified using XILINX FPGA

Exp. No.: SRAM cell design and simulation using Verilog.

AIM:
To using the Design and simulation of using SRAM cell
Verilog/VHDL in Xilinx ISE12.1i software tool.

APPARATUS REQUIRED:
 Pc With Windows Xp.
 Xilinx 12.1 Software
 Fpga-Spartan-3 Kit
 Parallel to JTAG Cable

PROCEDURE:
1. Start the Xilinx ISE by using Start>Program files> Xilinx ISE>project
navigator
2. Click File>New Project
3. Enter the Project Name and select the location then click next
4. Select the Device and other category and click next twice and finish.
 5. Click on the symbol of FPGA device and then right click>click on new
source.
6. Select the Verilog Module and give the filename>click next and define
ports>click next and finish.
7. Type the Verilog Code in Verilog Editor.
8. Run the Check syntax>Process window >synthesize>double click
check syntax. If any errors found, then remove the errors with proper syntax
&coding.
9. Click on the symbol of FPGA device and then right click>click on new
source.
10. Select the Test Bench Waveform and give the filename>select entity
click next and finish.
11. Select the desired parameters for simulating your design. In this case
combinational circuit and simulation time click [Link] all input signal
using just click on graph and save file.
12. From the source process window. Click Behavioral simulation from
drop-down menu
13. Select the test bench file (. tbw) and click process button>double click
the Simulation Behavioral Model
14. Verify your design in wave window by seeing behavior of output
signal with respect to input signal.
15. To assign package pins using corresponding CPLD manual via using
constraint.
16. Assign package pins.
17. The pace file opened and give the pin details.
18. Go Implement design and generate the programming file and
configure the device (impact).
19. In configure device choose JTAG options and add the Xilinx device in
boundary scan and download the program and execute successfully.

PROGRAM CODE :

module sram_cell (
input wire WL, // Word Line
input wire BL, // Bit Line
input wire BL_bar, // Complement Bit Line
input wire write_enable,
output reg Q,
output wire Q_bar
);

assign Q_bar = ~Q;

// SRAM behavior
always @(*) begin
if (WL) begin
 if (write_enable) begin
// Write operation
Q = BL;
end
// Read is implicit (Q drives output)
end
end

endmodule
 RESULT:

Thus, the simulation of basic combinational and sequential circuits using Verilog
HDL was performed and output was verified using XILINX FPGA

Exp. No.: Low power analysis for arithmetic circuits and memory designs using
Verilog/VHDL.

AIM:
To using the Design and simulation of using SRAM cell
Verilog/VHDL in Xilinx ISE12.1i software tool.

APPARATUS REQUIRED:
 Pc With Windows Xp.
 Xilinx 12.1 Software
 Fpga-Spartan-3 Kit
 Parallel to JTAG Cable

PROCEDURE:
1. Start the Xilinx ISE by using Start>Program files> Xilinx ISE>project
navigator
2. Click File>New Project
 3. Enter the Project Name and select the location then click next
4. Select the Device and other category and click next twice and finish.
5. Click on the symbol of FPGA device and then right click>click on new
source.
6. Select the Verilog Module and give the filename>click next and define
ports>click next and finish.
7. Type the Verilog Code in Verilog Editor.
8. Run the Check syntax>Process window >synthesize>double click
check syntax. If any errors found, then remove the errors with proper syntax
&coding.
9. Click on the symbol of FPGA device and then right click>click on new
source.
10. Select the Test Bench Waveform and give the filename>select entity
click next and finish.
11. Select the desired parameters for simulating your design. In this case
combinational circuit and simulation time click [Link] all input signal
using just click on graph and save file.
12. From the source process window. Click Behavioral simulation from
drop-down menu
13. Select the test bench file (. tbw) and click process button>double click
the Simulation Behavioral Model
14. Verify your design in wave window by seeing behavior of output
signal with respect to input signal.
15. To assign package pins using corresponding CPLD manual via using
constraint.
16. Assign package pins.
17. The pace file opened and give the pin details.
18. Go Implement design and generate the programming file and
configure the device (impact).
19. In configure device choose JTAG options and add the Xilinx device in
boundary scan and download the program and execute successfully.

PROGRAM CODE :

module low_power_adder (
input clk,
input enable,
input [7:0] A, B,
output reg [8:0] SUM
);

reg gated_clk;

// Clock gating
always @(*) begin
gated_clk = clk & enable;
end
always @(posedge gated_clk) begin
SUM <= A + B;
end

endmodule

Output :
RESULT:

Thus, the simulation of basic combinational and sequential circuits using Verilog
HDL was performed and output was verified using XILINX FPGA