Chapter 2: Instruction Set 8086/88 Processor

 Major Instruction Groups Of 8086/88 Processor:

1. Data Transfer Instructions
2. String Instructions
3. Logical Instruction
4. Shift and rotate Instruction
5. Arithmetic Instruction
6. Branch Instruction
7. Stack related instruction
8. Processor control Instruction
Data Transfer Instructions:
The primary function of a data transfer operation is to copy data from a
"source" location to another location known as the "destination". This is
represented by the notation:
[Destination] ← [Source]
Types of Data Transfer:
The process includes several specific types of movement within the hardware
architecture:

1. Register to register transfer: These instructions copy data between

internal processor registers.
A. Matching Sizes: A critical rule is that both registers must be of the
same size.
a. MOV AH, BL: Copies an 8-bit value from the BL register to the
AH register.
b. MOV AX, BX: Copies a 16-bit value from the BX register to the
AX register.
B. Invalid Transfers: Moving data between registers of different sizes is
not allowed (e.g., MOV BX, AL or MOV AL, BX).

2. Immediate data to register: Immediate data refers to a constant value

defined directly within the instruction.
A. 8-bit Immediate: MOV AL, 10 copies the 8-bit value '10' into the AL
register.
B. 16-bit Immediate: MOV BX, 1234 copies the 16-bit value '1234' into
the BX register.
  Internally, this splits the value: the high-order byte (12) is
stored in the BH-register, and the low-order byte (34) is stored
in the BL-register.

3. Register to memory (or vice versa): Moving data from a register to a

memory location or retrieving data from memory into a register.

A. Register to Memory (Indirect Addressing): In indirect addressing, a

register (like SI or BX) acts as a pointer containing the offset address
of the data in memory.
a. Memory to Register (8-bit): MOV AL, [SI] copies 8-bit data from
the memory location at address DS:[SI] into AL.
b. Memory to Register (16-bit): MOV BX, [SI] copies 16-bit data from
two consecutive memory locations.
 BL ← Data from address DS:*SI].
 BH ← Data from address DS:*SI + 1+.
c. Register to Memory: MOV [BX], AL copies 8-bit data from the AL
register to the memory address specified by DS:[BX].

B. Register to Memory (Direct Addressing): In direct addressing, the

memory address is specified numerically within the instruction.
a. 8-bit Transfer: MOV BL, [1000] copies 8-bit data from the address
DS:[1000] into the BL register.
b. 16-bit Transfer: MOV BX, [1000] retrieves a word from two
addresses.
 BL ← Data from DS:*1000+.
 BH ← Data from DS:*1001+.
c. Storing to Memory: MOV [2000], CL copies the 8-bit contents of
CL into the memory location at address DS:[2000].

4. Port and Accumulator: Transferring data between input/output ports

and the accumulator register (AL or AX).

A. Data Exchange Instructions (XCHG): The XCHG instruction is used to

swap the contents of two locations. Unlike MOV, which copies data,
XCHG performs a bidirectional transfer.
a. Permitted Exchanges:
 Two registers of equal size: e.g., XCHG BL, CL swaps 8-bit data
between these two registers.
  One register and one memory location: e.g., XCHG AL, [1000]
swaps the 8-bit contents of the accumulator with the data at
memory address DS:[1000].
b. 16-bit Exchange: XCHG [2000], BX swaps the 16-bit data in the BX
register with the data across two consecutive memory locations at
DS:[2000] and DS:[2001].

B. I/O Instructions with Direct 8-bit Port Address: These instructions

facilitate communication with external hardware using a specific 8-bit
port address.
a. Reading (IN):
 IN AL, 27H: Reads 8-bit data from a single input port at
address 27H into the AL register.
 IN AX, 27H: Reads 16-bit data from two consecutive input
ports; address 27H goes to AL, and 28H goes to AH.
b. Writing (OUT):
 OUT 27H, AL: Writes the 8-bit data from AL to the output
port at address 27H.
 OUT 27H, AX: Writes 16-bit data from AX to two
consecutive output ports (27H and 28H).

C. I/O Instructions with Indirect 16-bit Port Address: When the port
address is larger than 8 bits, it must be stored in the DX register.
a. Reading (IN):
 IN AL, DX: Reads 8-bit data from the port addressed by the
contents of DX into AL.
 IN AX, DX: Reads 16-bit data from the ports addressed by
DX (into AL) and DX (into AH).
b. Writing (OUT):
 OUT DX, AL: Writes the 8-bit data from AL to the output
port address stored in DX.
 OUT DX, AX: Writes the 16-bit data from AX to two
consecutive output ports starting at the address in DX.
String Instructions:
There are five main string instructions, each available in byte (ending in B) and
word (ending in W) variations.
String operations utilize specific registers as pointers:
SI (Source Index) points to the source string in the Data Segment (DS), and DI
(Destination Index) points to the destination string in the Extra Segment (ES).

1. LODSB/LODSW: Loads a string byte/word from DS:SI into the

accumulator (AL/AX).

2. STOSB/STOSW: Stores a string byte/word from the accumulator (AL/AX)

into ES:DI.

3. MOVSB/MOVSW: Moves a string byte/word from DS:SI to ES:DI

(effectively a combination of LODS and STOS).
4. SCASB/SCASW: Scans a string byte/word by subtracting the value at
ES:DI from the accumulator and updating flags.

5. CMPSB/CMPSW: Compares two strings by subtracting the byte/word at

ES:DI from the byte/word at DS:SI and updating flags.

6. Repeat Prefixes:
String instructions are typically used with a prefix to repeat the
operation across an entire block of data. The number of repetitions is
defined by a count stored in the CX register.
Logical Instructions:
Logical instructions are used to perform bitwise operations on either 8-bit or
16-bit data. Unlike some arithmetic instructions, the result storage for logical
operations is not restricted to the accumulator (AL/AX); results can be stored
in any General Purpose Register (GPR) or memory location. Operands can be
sourced from GPRs, memory, or immediate data.

Key Logical Operations:

1. NOT: Inverts every bit of the operand (One's complement).

 Example: NOT BL results in BL←∼BL.

2. AND: Performs a bitwise logical AND operation.

 Example (Register to Register): AND CX, DX (CX←CX∧DX).
 Example (Immediate to Register): AND BX, 1000 (BX←BX∧1000).
 Example (Memory to Register): AND BL, [1000]
(BL←BL∧DS:[1000]).

3. OR & XOR: The processor also supports standard bitwise logical OR and
Exclusive OR operations.

4. TEST: This instruction is similar to AND, but with one critical difference:
the result of the operation is not stored. It is primarily used to update
the processor flags (like the Zero Flag) to check the status of specific bits.
Shift and Rotate Instruction:
This slide introduces the fundamental difference between shifting and rotating
bits within a register.
 Shift Operations: Bits that are moved past the end of the register "fall
off".
 Rotate Operations: Bits that are moved out of one end "wrap around"
to the other end of the register.
 Execution: These can be performed on 8-bit or 16-bit registers. The
shift/rotate can be by a single bit or multiple bits, with the count
specified in the CL register.
 Types of Shifts:
a. Arithmetic Shift: Considers the sign bit during the shift (SAL &
SAR).
b. Logical Shift: Shifts data without considering the sign bit (SHL &
SHR).

Templates of Data Shift Operations:

This visual guide shows the bit-level movement for different shift types.

1. SAL/SHL (Shift Arithmetic Left / Shift Logical Left): Bits move toward the
Most Significant Bit (MSB). The MSB moves into the Carry Flag (CF), and
a "0" is shifted into the Least Significant Bit (LSB).

2. SHR (Shift Logical Right): Bits move toward the LSB. The LSB moves into
the Carry Flag, and a "0" is shifted into the MSB.

3. SAR (Shift Arithmetic Right): Bits move toward the LSB, and the LSB
enters the Carry Flag. Crucially, the sign bit is maintained by being
copied back into itself as it shifts right.
Shift Arithmetic Right (SAR) Operation Examples:
1. Example 1 (Negative Number): A 4-bit value 1010 (starting with 1)
becomes 1101 after SAR. The outgoing bit is '0', but the leading '1' is
preserved.

2. Example 2 (Negative Number): A 6-bit value 101101 becomes 110110

after SAR. The leading '1' is maintained.

3. Example 3 (Positive Number): A 6-bit value 001000 (starting with 0)

becomes 000100 after SAR. The leading '0' is preserved.

Templates of Data Rotate Operations:

This illustrates the "wrap around" nature of rotate instructions.
1. ROL (Rotate Left): The MSB wraps around to the LSB and is also copied
into the Carry Flag.

2. ROR (Rotate Right): The LSB wraps around to the MSB and is also copied
into the Carry Flag.

3. RCL (Rotate Left through Carry): The MSB goes into the Carry Flag, and
the previous value of the Carry Flag enters the LSB.
 4. RCR (Rotate Right through Carry): The LSB goes into the Carry Flag, and
the previous value of the Carry Flag enters the MSB.

Rotate Instructions of Intel 8086/88 Processor:

This summary slide details the application and syntax of rotate instructions.

1. Versatility: These can rotate 8-bit or 16-bit data from any register.

2. Rotate Through Carry:

 RCR BL, 01: Rotates the BL register right by 1 bit through the carry
flag.
 RCL BX, CL: Rotates the BX register left through the carry flag by
the count stored in CL.

3. Rotate Without Carry:
 ROR AX, 01: Rotates the AX register right by 1 bit.
 ROL BL, CL: Rotates the BL register left by the count stored in CL.

Arithmetic Instructions:
Overview of Arithmetic Instructions:
The processor's arithmetic set provides several key functionalities:

1. Fundamental Operations: Includes Addition, Subtraction, Multiplication,

and Division.

2. Register Modification: Specialized instructions for incrementing or

decrementing values by one.

3. Data Comparison: Comparing values without altering them, which

updates the processor flags.

4. Specialized Formatting: Includes manipulation of BCD numbers and sign

extension for signed division.
Addition and Subtraction:
These instructions handle basic math between registers, immediate values,
and memory.

1. Addition (ADD & ADC):

o ADD: Standard addition where BL ← BL + CL.
o ADC (Add with Carry): Includes the Carry flag (Cy bit) in the
calculation, such as BL ← BL + CL + Cy bit. This is essential for
multi-word mathematical operations.

2. Subtraction (SUB & SBB):

o SUB: Basic subtraction, such as BX ← BX - CX.
o SBB (Subtract with Borrow): Subtracts the Carry flag from the
result, such as AX ← AX - CX - Cy bit.

Increment, Decrement, and Compare:

These are efficient instructions for loop control and decision-making.

1. Increment (INC) and Decrement (DEC):

o INC BL adds one to the register (BL ← BL + 01).
o DEC BL subtracts one from the register (BL ← BL - 01).

2. Data Compare (CMP):

o The CMP instruction performs a subtraction internally (e.g., AL -
BL) but does not store the result.
o Its primary purpose is to update processor flags to indicate if the
values were equal, or if one was greater than the other.

Multiplication and Division:

Multiplication and division vary significantly based on the bit-size of the
operands.

1. Multiplication (MUL):
o 8-bit: MUL BL results in a 16-bit product stored in the AX register
(AX ← AL × BL).
o 16-bit: MUL BX results in a 32-bit product stored across two
registers (DX:AX ← AX × BX).
 2. Division (DIV):
o 16-bit by 8-bit: Unsigned (AX) ÷ (BL) stores the quotient in AL and
the remainder in AH.
o 32-bit by 16-bit: Unsigned (DX:AX) ÷ (BX) stores the quotient in AX
and the remainder in DX.

3. Signed Operations: IMUL and IDIV are used specifically for signed
numbers, where the result also retains its mathematical sign.

BCD and Sign Extension Instructions:

Specialized instructions adjust binary results into formats human-readable as
decimal or prepare data for division.

1. Packed BCD (DAA & DAS): These adjust the result in the AL register after
addition (DAA) or subtraction (DAS). If a nibble is greater than '9', '6' is
added or subtracted to correct the decimal representation.

2. Unpacked BCD (AAA, AAS, AAM, AAD):

o Used for numbers stored as one decimal digit per byte.
o AAA and AAS adjust addition/subtraction results.
o AAM adjusts multiplication, while AAD must be used before a
division instruction to convert unpacked BCD into a hex value the
processor can divide.
 3. Sign Extension (CBW & CWD):
o These are used to extend the sign bit before performing signed
division.

o CBW (Convert Byte to Word): If the highest bit of AL is 1

(negative), AH is filled with 1s to maintain the negative value in
the 16-bit AX register.

o CWD (Convert Word to Double Word): Operates similarly,

extending the sign of AX into the DX register.

Branching Instructions :
Branching instructions change the sequence of program execution. They are
essential for creating loops, decision-making structures, and modular code.

1. Types of Branching:
The 8086 supports three primary branching methods:
 Jump instructions: Transfers control to another part of the program.
 Subroutine CALL instructions: Executes a named procedure and then
returns.
 LOOP instructions: Performs repetitive execution based on a counter.
Note: The processor supports only unconditional CALL and return instructions.

2. Conditional Jumps:
There are 18 conditional jump instructions that trigger based on the state of
processor flags after an ALU operation:
 After Signed Operations: JG (Greater), JGE (Greater or Equal), JL (Less),
JLE (Less or Equal), JO (Overflow), and JS (Sign).
 After Unsigned Operations: JA (Above), JAE (Above or Equal), JB
(Below), and JBE (Below or Equal).
 General Flags: JC (Carry), JZ/JE (Zero/Equal), and JP/JPE (Parity).
3. Jump Concepts: Intra-segment vs. Inter-segment :

 Near jump: Uses a 16-bit signed offset (range: −32 KB to +32 KB).
 Short jump: Uses an 8-bit signed offset (range: −128 to +127 locations).
4. Subroutine CALL and RET:
A CALL is used to execute a block of code (subroutine) and return to the next
instruction in the main program.
 Near CALL: Calls a subroutine in the same segment; stores the IP on the
stack as the return address.
 Far CALL: Calls a subroutine in a different segment; stores both CS and IP
on the stack.
 Execution Steps:
1. Processor copies the "return address" onto the stack.
2. IP is loaded with the subroutine's offset.
3. Subroutine executes until the RET instruction is reached.
4. Processor retrieves the "return address" from the stack and
reloads it into IP.

5. LOOP Instructions:
Loops use the CX register as a hardware counter.
 LOOP next: Decrements CX; if CX≠0, it jumps to the label.
 LOOPZ/LOOPE: Decrements CX; jumps if CX≠0 AND ZF=1.
 LOOPNZ/LOOPNE: Decrements CX; jumps if CX≠0 AND ZF=0.
 JCXZ: Jumps only if the CX register is already zero
Stack Related Instructions (PUSH & POP):
The stack is a "Last-In-First-Out" (LIFO) memory structure used for temporary
data storage. These instructions manage 16-bit data transfers to and from the
stack.

 PUSH BX: This instruction "pushes" 16-bit data from the BX register onto
the top of the stack.
o The Stack Pointer (SP) is decremented by 1 (SP←SP−1).
o The high byte of BX (BH) is stored at the memory location
addressed by SS:[SP].
o The SP is decremented again by 1 (SP←SP−1).
o The low byte of BX (BL) is stored at the new memory location
addressed by SS:[SP].

 POP BX: This instruction retrieves 16-bit data from the top of the stack
and stores it back into the BX register.
o The operation is the exact opposite of the PUSH instruction.

Processor Control Instructions:

These instructions manually manipulate flags or control processor behavior.
 Flag Control: STC (Set Carry), CLC (Clear Carry), STD (Set Direction), CLD
(Clear Direction), STI (Set Interrupt), and CLI (Clear Interrupt).
 Prefixes: LOCK (locks the bus), ESC (escape to co-processor), and WAIT
(waits for a signal).

 Addressing Modes (Method to Refer to Data/Operands):

Addressing modes are the various ways a processor can specify the location of
an operand (data) in an instruction.

The 8086 supports seven different modes:

1. Register Addressing Mode
 Concept: The data or operands are located directly within the
processor's internal registers.
 Rule: The specific register must be named in the instruction.
 Examples: MOV AX, BX, ADD CL, DL, and AND BL, CL.
2. Immediate Addressing Mode
 Concept: The data (operand) is defined directly within the instruction
itself rather than in a register or memory location.
 Examples: MOV AL, 12, ADD DL, 80, and MOV BX, 1234.

3. Direct Addressing Mode

 Concept: The 16-bit memory address or 8-bit I/O port address of the
operand is specified directly in the instruction.
 Note: In the 8086, the memory address is treated as an offset from the
data segment.
 Examples: MOV AL, [1000], ADD [2000], AX, and IN AL, 40.

4. Indirect Addressing Mode

 Concept: The address of the operand is not written in the instruction but
is stored in a "base" or "index" register.
 Registers Used: BX, BP, SI, or DI.
 Note: Indirect I/O port addressing specifically uses the DX register.
 Examples: MOV CL, [BX] (where CL gets data from the address in BX) and
IN AL, DX.

5. Base Relative Addressing Mode

 Concept: The effective address (offset) is calculated by adding the
contents of a base register (BX or BP) to an 8-bit or 16-bit displacement
value provided in the instruction.
 Example: MOV AL, [BX + 4] calculates the address by adding 4 to
whatever value is currently in the BX register.

6. Base Plus Index Addressing Mode

 Concept: The offset address is calculated by adding the contents of a
base register (BX or BP) to an index register (SI or DI).
 Example: MOV AL, [BX + SI].

7. Base Relative Plus Index Addressing Mode

 Concept: This is the most complex mode. The address is calculated by
adding a base register, an index register, and a numerical displacement
value.
 Example: MOV AL, [BX + SI + 22].
Assembler Directives:
Assembler directives are "pseudo-instructions" that provide instructions to the
assembler software but do not generate actual machine executable code.

General Overview
 Directives give "direction" to the assembler during the translation
process.
 There are five main types: Data definition, Program organization,
Procedure definition, Macro definition, and Data control directives.

1. Data Definition & Storage Allocation Directives:

These directives allow the programmer to define variables and set aside
memory space:
 DB (Define Byte): Defines an 8-bit variable.
o Syntax: Variable-name DB Value.
o Example: Number DB 20 or Array1 DB 100 DUP (0) (creates
an array of 100 bytes, all initialized to zero).
 DW (Define Word): Defines a 16-bit variable.
 DD (Define Double-word): Defines a 32-bit variable.
 DQ (Define Quad-word): Defines a 64-bit variable.
 DT (Define Ten-byte): Defines an 80-bit variable.

2. Constant and Location Directives

 EQU (Equate to): This directive assigns a constant value to a symbol.
The macro-assembler replaces every occurrence of that symbol with
its value during assembly.
o Syntax: Symbol-name EQU Value.
o Example: PI EQU 3.14.
 ORG (Originate): This assigns a specific value to the location counter,
placing the machine code at that specific location after assembly.
o Syntax: ORG $+ Numerical-value.
o Example: ORG 1000H.

3. Program Organization Directives

These define the logical structure of the assembly program.
 ASSUME: Tells the assembler which logical name belongs to which
segment register (e.g., Assume CS: Code, DS: Data).
 SEGMENT / ENDS: These markers indicate the beginning and end
of a logical segment.
  END: This directive marks the physical end of the entire program.

4. Procedure and Macro Directives

 PROC / ENDP: Used to define a procedure (subroutine). The PROC
directive must specify the type as either near or far.
o Syntax: Procedure-name PROC {Near/Far} followed by ENDP at
the end.
 MACRO / ENDM: Defines a macro, which consists of a name followed
by the keyword and any arguments.
o Syntax: Macro-name MACRO [Arguments] followed by ENDM.

5. Data Control Directives

 PUBLIC: Informs the assembler that a specific variable or segment is
global and can be accessed from any other module.
 PTR: Indicates the type of memory access required, such as Byte,
Word, or Dword (e.g., JMP Dword PTR [BX]).

Mixed Language Programming:

Mixed language programming refers to the practice where one program calls
another program that is written in a different programming language. This
approach is particularly useful when certain algorithms or functionalities can
be described more naturally or efficiently in a specific language. Instead of
compiling all source programs with the same compiler, different compilers or
assemblers are utilized according to the languages involved in the project. The
process typically involves calling a procedure or subroutine written in a
language distinct from that of the main program.

Methods of Mixed Language Programming

There are two primary methods for implementing mixed language
programming:

1. Linked Assembly:
This method involves writing routines in assembly language, which are
then separately assembled by a macro-assembler (like MASM for
Microsoft C). These assembled modules are subsequently linked with
compiled modules from the main program's language (e.g., C modules)
by a linker to produce the final executable file.
2. In-line Assembly:

In-line assembly is a powerful feature, particularly preferred under

specific circumstances:
 Limited Assembly Instructions: It is most advantageous when the
number of assembly language instructions required is relatively small
compared to the overall C code. This keeps the code manageable and
avoids the overhead of separate assembly and linking processes.
 Port Address Access: In-line assembly is highly effective for accessing
port addresses. This operation is often quicker and simpler to implement
directly in assembly language compared to its equivalent in C, offering
better control and performance for hardware interactions.
Advantages of In-line Assembly
Utilizing in-line assembly offers several benefits:
 Quick Compilation: Since there is no need for a separate assembler, the
compilation process is generally faster as the C compiler handles both C
and embedded assembly code in one go.
 No Linking Required: A significant advantage is that in-line assembly
typically eliminates the need for a separate linking step. The compilation
process directly generates a single object code, which is itself the
executable code, simplifying the build process.