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MICROCONTROLLERS AND MICROPROCESSORS

1. 8051 Microcontroller Architecture
The 8051 microcontroller is an 8-bit microcontroller, meaning it can process 8 bits of data at
a time. It has several integrated components, making it a powerful choice for embedded
applications.
1. Block Diagram of 8051 Architecture
The 8051 microcontroller consists of the following major components:
• Central Processing Unit (CPU)
• Random Access Memory (RAM)
• Read-Only Memory (ROM)
• I/O Ports
• Timers and Counters
• Serial Communication (UART)
• Interrupts
• Special Function Registers (SFRs)

2. Components of 8051 Microcontroller

(A) Central Processing Unit (CPU)
• The CPU is the heart of the 8051 microcontroller.
• It fetches, decodes, and executes instructions.
• The CPU controls all other peripherals and operations of the system.
(B) Memory Organization
The 8051 has two types of memory:
1. Program Memory (ROM)
o The 8051 has 4KB of on-chip ROM for storing program code.
o It is a non-volatile memory (retains data even when power is off).
o External memory can be added (up to 64KB).
2. Data Memory (RAM)
o The 8051 has 128 bytes of internal RAM.
o It is divided into three areas:

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▪ 32 General-Purpose Registers (0-31)
▪ Bit-Addressable Area (32-47)
▪ General-Purpose Memory and Stack (48-127)
3. Special Function Registers (SFR)
o These are dedicated memory locations used to control different parts of the
microcontroller.
o Example registers: ACC (Accumulator), B Register, PSW (Program Status
Word), DPTR (Data Pointer), etc.

(C) Input/Output (I/O) Ports

The 8051 has four 8-bit I/O ports:
• Port 0 (P0): Dual-purpose, can be used as an I/O port or as address/data lines.
• Port 1 (P1): A dedicated I/O port.
• Port 2 (P2): Used for higher address bytes when accessing external memory.
• Port 3 (P3): Dual-purpose, includes control signals for serial communication and
interrupts.

(D) Timers and Counters

The 8051 has two 16-bit timers/counters (Timer 0 and Timer 1), which are used for:
• Delays
• Counting external pulses
• Measuring time intervals
• Baud rate generation for serial communication
Each timer can operate in different modes, allowing flexibility in applications.

(E) Interrupts
Interrupts allow the 8051 to pause execution of the main program and execute a separate
function when an event occurs.
There are five interrupts in the 8051:
1. External Interrupt 0 (INT0)
2. External Interrupt 1 (INT1)

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3. Timer 0 Overflow Interrupt (TF0)
4. Timer 1 Overflow Interrupt (TF1)
5. Serial Communication Interrupt (RI/TI)
Interrupts help handle events like button presses, data reception, or timer overflow
without continuously checking conditions in a loop.

(F) Serial Communication (UART)

The 8051 has a built-in UART (Universal Asynchronous Receiver Transmitter) for serial
communication.
• Tx (Transmit) and Rx (Receive) pins are available on Port 3.
• Supports full-duplex communication (simultaneous send and receive).
• Used for communication with devices like PCs, GSM modules, Bluetooth, etc.

(G) Oscillator and Clock

• The 8051 requires an external crystal oscillator (typically 11.0592 MHz).
• The oscillator determines the instruction execution speed.
• A machine cycle consists of 12 clock cycles.

3. Pin Diagram of 8051

The 8051 has 40 pins, which include:
• Vcc (Pin 40): Power supply (+5V).
• GND (Pin 20): Ground.
• XTAL1, XTAL2 (Pins 18, 19): Crystal oscillator connection.
• RST (Pin 9): Reset pin (active HIGH).
• EA (Pin 31): External Access (used for external memory).
• ALE (Pin 30): Address Latch Enable.
• PSEN (Pin 29): Program Store Enable (for external ROM).

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4. Instruction Set of 8051
The 8051 instruction set consists of three main types:
1. Data Transfer Instructions
o MOV A, #55H → Move 55H into accumulator.
o MOV R0, A → Move contents of accumulator to R0.
2. Arithmetic Instructions
o ADD A, R1 → Add register R1 to accumulator.
o SUBB A, #02H → Subtract immediate value 02H from accumulator.
3. Logical Instructions
o ANL A, R2 → AND operation between accumulator and R2.
o ORL A, #0F → OR operation between accumulator and immediate value.
4. Branching Instructions
o SJMP LABEL → Short jump to LABEL.
o CJNE A, #10H, LABEL → Compare A with 10H, jump to LABEL if not equal.

5. Applications of 8051 Microcontroller

The 8051 is widely used in embedded systems due to its simplicity and versatility. Some
applications include:
• Home automation (smart locks, temperature control).
• Industrial control systems (motor control, robotics).
• Medical devices (heart rate monitors, glucometers).
• Automobile systems (anti-lock braking, fuel injection).
• Consumer electronics (microwaves, washing machines).

2. Instruction Set of 8051 Microcontroller

The 8051 microcontroller instruction set is classified into different categories based on
functionality. These instructions help in performing various operations like data transfer,
arithmetic operations, logical operations, branching, and bit manipulation.
Overview of 8051 Instruction Set
• The 8051 is an 8-bit microcontroller, meaning most instructions operate on 8-bit
data.

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• It has 255 instructions, each requiring 1 to 3 bytes.
• Instructions take 1 to 2 machine cycles to execute.

1. Classification of 8051 Instructions

The instructions in the 8051 microcontroller are categorized into five major groups:

Instruction Type Function

Data Transfer Instructions Move data between registers, memory, or I/O ports.

Arithmetic Instructions Perform addition, subtraction, multiplication, and

division.

Logical Instructions Perform bitwise AND, OR, XOR, and rotate operations.

Branching Instructions Control the flow of execution (jumps, calls, returns).

Bit Manipulation Instructions Set, clear, or test specific bits.

2. Data Transfer Instructions

These instructions are used to transfer data between registers, memory locations, and
ports.
General Format:
MOV destination, source
This moves data from the source operand to the destination operand.

Mnemonic Description Example

MOV A, Rn Move register Rn to the accumulator MOV A, R0

MOV A, #data Load immediate data into A MOV A, #0Fh

MOV Rn, A Move A to register Rn MOV R2, A

MOV Rn, #data Load immediate data into Rn MOV R3, #25H

MOV A, @Ri Move indirect memory to A MOV A, @R1

MOV @Ri, A Move A to indirect memory MOV @R0, A

MOV DPTR, #data16 Load immediate 16-bit data into DPTR MOV DPTR, #1234H

MOVX A, @DPTR Move external memory to A MOVX A, @DPTR

MOVX @DPTR, A Move A to external memory MOVX @DPTR, A

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Examples:
MOV A, #25H ; Load 25H into accumulator
MOV R1, A ; Move contents of A to register R1
MOV @R0, A ; Move A to address pointed by R0
MOV DPTR, #5000H ; Load DPTR with address 5000H

3. Arithmetic Instructions
These instructions perform addition, subtraction, multiplication, and division.

Mnemonic Description Example

ADD A, Rn Add register Rn to A ADD A, R3

ADD A, #data Add immediate data to A ADD A, #0AH

SUBB A, Rn Subtract register Rn from A with borrow SUBB A, R0

SUBB A, Subtract immediate data from A with borrow SUBB A,

#data #05H

INC A Increment A by 1 INC A

INC Rn Increment register Rn by 1 INC R2

INC DPTR Increment DPTR by 1 INC DPTR

DEC A Decrement A by 1 DEC A

DEC Rn Decrement register Rn by 1 DEC R1

MUL AB Multiply A and B, store result in A (low byte) and B (high MUL AB
byte)

DIV AB Divide A by B, quotient in A, remainder in B DIV AB

Examples:
MOV A, #10H ; Load 10H into accumulator
MOV R1, #05H ; Load 05H into R1
ADD A, R1 ; A = A + R1 (10H + 05H = 15H)
MUL AB ; Multiply A and B
DIV AB ; Divide A by B

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4. Logical Instructions
These instructions perform bitwise AND, OR, XOR, complement, and rotate operations.

Mnemonic Description Example

ANL A, Rn AND A with Rn ANL A, R3

ANL A, #data AND A with immediate data ANL A, #0Fh

ORL A, Rn OR A with Rn ORL A, R5

ORL A, #data OR A with immediate data ORL A, #F0h

XRL A, Rn XOR A with Rn XRL A, R7

XRL A, #data XOR A with immediate data XRL A, #0Ah

CPL A Complement A CPL A

CLR A Clear A CLR A

RL A Rotate A left RL A

RLC A Rotate A left through carry RLC A

RR A Rotate A right RR A

RRC A Rotate A right through carry RRC A

Examples:
MOV A, #55H ; Load 55H into accumulator
ANL A, #0FH ; AND operation with 0FH
ORL A, #F0H ; OR operation with F0H
XRL A, #AAH ; XOR operation with AAH

5. Branching Instructions
These instructions control program flow using jumps and calls.

Mnemonic Description Example

SJMP label Short jump (within 256 bytes) SJMP LOOP

LJMP address Long jump (anywhere in memory) LJMP START

AJMP address Absolute jump (within 2KB) AJMP SUBROUTINE

JZ label Jump if A is zero JZ END

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JNZ label Jump if A is not zero JNZ LOOP

CJNE A, #data, label Compare A and jump if not equal CJNE A, #10H, SKIP

DJNZ Rn, label Decrement Rn and jump if not zero DJNZ R3, LOOP

CALL address Call subroutine CALL DELAY

RET Return from subroutine RET

Examples:
MOV A, #00H
JZ END ; Jump to END if A is 0
MOV R1, #10H
DJNZ R1, LOOP ; Decrement R1 and jump to LOOP if not zero

6. Bit Manipulation Instructions

These instructions manipulate individual bits.

Mnemonic Description Example

SETB bit Set a bit to 1 SETB P1.0

CLR bit Clear a bit (set to 0) CLR P1.0

CPL bit Complement a bit CPL P1.0

JBC bit, label Jump if bit is 1 and clear it JBC P1.1, LOOP

3. Subroutines in 8051 Microcontroller

1. What is a Subroutine?
A subroutine (also called a function or procedure) is a block of code that performs a specific
task and can be called from different parts of a program. It helps in code reusability,
modular programming, and efficient memory usage.
Key Features of Subroutines
• Saves memory by avoiding code duplication.
• Makes programs more readable and maintainable.
• Allows structured programming.
• Uses stack memory to store return addresses.

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2. How Subroutines Work in 8051
The 8051 microcontroller uses two instructions to handle subroutines:
1. CALL (Call Subroutine)
2. RET (Return from Subroutine)
When a subroutine is called:
• The address of the next instruction (after the call) is pushed onto the stack.
• Control jumps to the subroutine location.
• After execution, the RET instruction is used to return to the main program.
• The return address is popped from the stack, and execution continues.

3. CALL Instructions (Types of Calls in 8051)

(A) ACALL (Absolute Call)
• Calls a subroutine within a 2KB address range.
• Uses an 11-bit address (the higher 5 bits remain unchanged).
• Takes 2 bytes (1st byte for instruction, 2nd byte for address).
Syntax & Example:
ACALL DELAY ; Calls DELAY subroutine

(B) LCALL (Long Call)

• Calls a subroutine anywhere in the 64KB address range.
• Uses a 16-bit address (full address is specified).
• Takes 3 bytes (1st byte for instruction, 2 bytes for address).
Syntax & Example:
LCALL DELAY ; Calls DELAY subroutine

4. RET Instruction (Return from Subroutine)

• RET (Return) is used to return from a subroutine.
• It pops the return address from the stack and jumps back.

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Syntax & Example:
RET ; Return to the main program

5. Example: Subroutine for Delay

(A) Using ACALL
ORG 0000H ; Start address
MOV P1, #0FFH ; Set Port 1 as output
ACALL DELAY ; Call delay subroutine
CLR P1.0 ; Clear bit P1.0
ACALL DELAY ; Call delay again
SETB P1.0 ; Set bit P1.0
SJMP $ ; Infinite loop
DELAY:
MOV R7, #255 ; Load R7 with 255
LOOP1:
MOV R6, #255 ; Load R6 with 255
LOOP2:
DJNZ R6, LOOP2 ; Decrement R6 until 0
DJNZ R7, LOOP1 ; Decrement R7 until 0
RET ; Return from subroutine
END
Explanation:
• The main program sets P1.0 high and calls DELAY.
• The DELAY subroutine creates a time delay using loops.
• RET brings control back to the main program.

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(B) Using LCALL
ORG 0000H
MOV P2, #0AAH ; Send 0AAH to Port 2
LCALL TOGGLE ; Call TOGGLE subroutine
SJMP $ ; Infinite loop
TOGGLE:
CPL P2 ; Complement (toggle) Port 2
RET ; Return to main program
END
Explanation:
• MOV P2, #0AAH loads Port 2.
• LCALL TOGGLE calls the TOGGLE subroutine.
• CPL P2 toggles all bits of Port 2.
• RET returns execution to the main program.

6. How Stack is Used in Subroutines

• The stack stores return addresses when a subroutine is called.
• The SP (Stack Pointer) keeps track of the top of the stack.
• Each CALL pushes the return address onto the stack.
• Each RET pops the return address and resumes execution.
Example: How Stack Works
ORG 0000H
MOV SP, #30H ; Initialize Stack Pointer
LCALL SUB1 ; Call SUB1
SJMP $ ; Infinite loop
SUB1:
LCALL SUB2 ; Call SUB2 from SUB1
RET ; Return to main program

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SUB2:
RET ; Return to SUB1
END
Stack Operations:
1. LCALL SUB1 → Pushes return address onto the stack.
2. LCALL SUB2 → Pushes another return address onto the stack.
3. RET in SUB2 → Pops stack to return to SUB1.
4. RET in SUB1 → Pops stack to return to the main program.

7. Difference Between ACALL and LCALL

Feature ACALL LCALL

Addressing Uses 11-bit address Uses full 16-bit address

Range Calls within 2KB Calls anywhere in 64KB

Instruction Size 2 bytes 3 bytes

Execution Time Faster Slower

8. Nested Subroutines
A nested subroutine is when a subroutine calls another subroutine before returning.
Example of Nested Subroutines
ORG 0000H
LCALL FUNCTION1 ; Call FUNCTION1
SJMP $ ; Infinite loop
FUNCTION1:
LCALL FUNCTION2 ; Call FUNCTION2 from FUNCTION1
RET ; Return to main program
FUNCTION2:
NOP ; Do nothing
RET ; Return to FUNCTION1
END

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Execution Flow:
1. LCALL FUNCTION1 → Goes to FUNCTION1.
2. LCALL FUNCTION2 → Goes to FUNCTION2.
3. RET in FUNCTION2 → Returns to FUNCTION1.
4. RET in FUNCTION1 → Returns to the main program.

9. Recursion in 8051 (Not Recommended)

• Recursion is when a function calls itself.
• 8051 does not support recursion efficiently due to limited stack space (only 128
bytes of RAM).
• Recursion can lead to stack overflow.

10. Applications of Subroutines in 8051

1. Delays (for blinking LEDs, timing operations).
2. Serial Communication (sending/receiving data).
3. Mathematical Operations (multiplication, division).
4. Interrupt Service Routines (ISRs).
5. Motor Control Algorithms (PWM, stepper motor control).

4. Use of Input and Output Machine-Related Statements in 8051 Microcontroller

1. Introduction
Input and Output (I/O) operations are essential for interfacing the 8051 microcontroller
with external devices like LEDs, switches, motors, sensors, displays, and communication
modules.
Key Features of 8051 I/O Handling:
• Four 8-bit ports (P0, P1, P2, P3) for input/output.
• Each port has 8 pins (total of 32 I/O lines).
• Ports can function as digital I/O or special function ports.
• I/O operations are controlled via machine-level instructions.

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2. 8051 I/O Port Architecture

Port Type Function

P0 (Port 0) Bidirectional Open-drain, used for address/data multiplexing in

external memory.

P1 (Port 1) Bidirectional General-purpose I/O, no alternate functions.

P2 (Port 2) Bidirectional Used as higher address byte in external memory access.

P3 (Port 3) Bidirectional Special function pins (Serial, Interrupts, Timer,

Read/Write).

3. Input/Output Instructions in 8051

(A) Writing to an Output Port
To send data to a port (set it as output), we use:
MOV P1, #data ; Move immediate data to port
Example: Send 0xFF to Port 1 (turn all pins high)
MOV P1, #0FFH ; Set all P1 pins HIGH
Example: Blink an LED connected to P2.0
SETB P2.0 ; Turn LED ON
CLR P2.0 ; Turn LED OFF

(B) Reading from an Input Port

To read data from a port (set it as input), we use:
MOV A, P1 ; Move port data to accumulator
Example: Read a switch state from P3.2
MOV A, P3 ; Read all pins of Port 3
JB P3.2, LABEL ; Jump if P3.2 is HIGH

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(C) Bit-Level I/O Instructions
8051 allows bit manipulation, useful for controlling individual port pins.

Instruction Description Example

SETB bit Set bit (1) SETB P1.0 (P1.0 = 1)

CLR bit Clear bit (0) CLR P1.0 (P1.0 = 0)

CPL bit Complement bit CPL P1.1 (Toggle P1.1)

JB bit, label Jump if bit is 1 JB P3.0, SKIP

JNB bit, label Jump if bit is 0 JNB P3.1, SKIP

Example: Toggle P2.3 continuously

CPL P2.3 ; Toggle P2.3
SJMP $ ; Infinite loop

4. I/O Machine-Level Operations (With Examples)

(A) Controlling an LED (Output)
LED at P1.0 blinks continuously
AGAIN:
SETB P1.0 ; Turn LED ON
ACALL DELAY ; Call delay subroutine
CLR P1.0 ; Turn LED OFF
ACALL DELAY ; Call delay subroutine
SJMP AGAIN ; Repeat forever

(B) Reading a Push Button (Input)

If switch at P3.2 is pressed, turn ON LED at P1.0
AGAIN:
JB P3.2, AGAIN ; Wait until switch is pressed
SETB P1.0 ; Turn LED ON
SJMP AGAIN ; Loop forever

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(C) Sending Data to an External Device
Send 0x55 to Port 0
MOV P0, #55H ; Send 55H to Port 0

(D) Receiving Data from a Sensor

Read temperature sensor value from Port 2
MOV A, P2 ; Read sensor data into A

(E) Using Port 3 Special Functions

Pin Alternate Function

P3.0 (RXD) Serial Receive

P3.1 (TXD) Serial Transmit

P3.2 (INT0) External Interrupt 0

P3.3 (INT1) External Interrupt 1

P3.4 (T0) Timer 0 Input

P3.5 (T1) Timer 1 Input

P3.6 (WR) External Write

P3.7 (RD) External Read

Example: Enable Serial Communication (TXD/RXD on P3.0, P3.1)

MOV SCON, #50H ; Configure serial mode
MOV TH1, #0FDH ; Set baud rate
SETB TR1 ; Start Timer 1
MOV SBUF, #’A’ ; Send ‘A’ to serial port

5. Summary
MOV Pn, #data → Write to a port
MOV A, Pn → Read from a port
SETB / CLR / CPL → Control individual bits
JB / JNB → Conditional jumps based on input

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5. Time Delay Program in 8051 Microcontroller
1. Introduction to Time Delay in 8051
A time delay is a pause in program execution for a specific duration, commonly used for LED
blinking, motor control, and serial communication timing. The 8051 microcontroller
generates delays using loops and timers.

2. Methods to Generate Delay in 8051

(A) Software Delay (Using Loops)
• Simple loops with decrement instructions (DJNZ).
• Less precise, affected by clock cycles and execution time.
• Suitable for short delays.
(B) Timer-Based Delay (Using Timer 0/1)
• Uses Timer Registers (THx, TLx).
• More accurate than software loops.
• Suitable for long and precise delays.

3. Software Delay (Using Loops)

A loop-based delay uses registers to count down, pausing execution.
Example: Delay Using Nested Loops
ORG 0000H ; Start of program
AGAIN:
SETB P1.0 ; Turn ON LED
ACALL DELAY ; Call delay subroutine
CLR P1.0 ; Turn OFF LED
ACALL DELAY ; Call delay subroutine
SJMP AGAIN ; Repeat forever
DELAY:
MOV R7, #255 ; Load R7 with 255
LOOP1:
MOV R6, #255 ; Load R6 with 255

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LOOP2:
DJNZ R6, LOOP2 ; Decrement R6 until 0
DJNZ R7, LOOP1 ; Decrement R7 until 0
RET ; Return to main program
END
Explanation:
1. SETB P1.0 turns ON the LED.
2. ACALL DELAY calls a delay function.
3. CLR P1.0 turns OFF the LED.
4. ACALL DELAY adds another delay.
5. Nested loops count down to create a delay.

4. Timer-Based Delay in 8051

Timers count clock cycles to create an accurate delay.
(A) Timer Registers in 8051

Timer Registers Used 16-bit Mode

Timer 0 TH0, TL0 Yes

Timer 1 TH1, TL1 Yes

(B) Timer Control Register (TMOD)

Bit Function

Bit 7-4 Timer 1 Mode (Upper 4 bits)

Bit 3-0 Timer 0 Mode (Lower 4 bits)

Mode 0 (00) 13-bit Timer

Mode 1 (01) 16-bit Timer

Mode 2 (10) 8-bit Auto Reload

Mode 3 (11) Split Timer

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Example: Delay Using Timer 0 (16-bit Mode)
ORG 0000H
MOV TMOD, #01H ; Set Timer 0 to 16-bit mode
AGAIN:
SETB P1.0 ; Turn ON LED
ACALL DELAY ; Call Timer-based delay
CLR P1.0 ; Turn OFF LED
ACALL DELAY ; Call Timer-based delay
SJMP AGAIN ; Repeat forever
DELAY:
MOV TH0, #0FDH ; Load high byte
MOV TL0, #0A0H ; Load low byte (50ms delay)
SETB TR0 ; Start Timer 0
WAIT:
JNB TF0, WAIT ; Wait until overflow
CLR TR0 ; Stop Timer
CLR TF0 ; Reset Timer Flag
RET ; Return to main program
END
Explanation:
1. MOV TMOD, #01H → Configures Timer 0 as a 16-bit timer.
2. MOV TH0, #0FDH and MOV TL0, #0A0H → Load timer registers.
3. SETB TR0 → Starts the timer.
4. JNB TF0, WAIT → Waits until the timer overflows.
5. CLR TR0 & CLR TF0 → Stops and resets the timer.
6. RET → Returns to the main program.

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5. Timer Calculation for Delay
The delay time depends on:
• Crystal frequency (11.0592 MHz)
• Timer mode (16-bit/8-bit)
• Timer register values (THx, TLx)
Formula to Calculate Delay

6. Comparison of Methods

Method Precision Complexity Application

Loop-Based Low Simple LED blinking, small delays

Timer-Based High More Complex Precise delays, motor control

6. Assembler Directives and Peripheral ICs in 8051

1. Introduction
Assembler directives are special instructions used by the assembler to guide how the code
should be assembled.
These directives do not generate machine code but help in memory allocation, defining
constants, labels, and organizing the program.
Peripheral ICs are external components that work with the 8051 microcontroller for various
functions like display, motor control, communication, memory interfacing, etc.

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2. Assembler Directives in 8051
Assembler directives are categorized based on their function:
(A) Data Definition Directives

Directive Description Example

ORG Set program origin (starting address) ORG 0000H

DB (Define Byte) Defines a byte value DATA DB 55H

DW (Define Word) Defines a word (16-bit) NUM DW 1234H

EQU (Equate) Assigns a constant value to a label COUNT EQU 0AH

SET Similar to EQU but can be redefined BAUDRATE SET 9600

Example: Defining Data

ORG 0000H ; Set start address
DATA DB 55H ; Store 55H at current memory location

(B) Code Organization Directives

Directive Description Example

END Marks end of source code END

SEGMENT Defines a segment in memory CODE SEGMENT

ASSUME Assigns segment registers to specific segments ASSUME CS:CODE

Example: Marking the End of Code

MOV A, #0FFH ; Load A with FFH
END ; End of program

(C) Storage and Memory Allocation Directives

Directive Description Example

DS (Define Storage) Reserves memory space BUFFER DS 20H (Reserves 32 bytes)

RS (Register Storage) Used in RAM allocation TEMP RS 1

Example: Defining RAM Storage

ORG 30H ; RAM memory start
VAR1 DS 1 ; Reserve 1 byte

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VAR2 DS 2 ; Reserve 2 bytes

(D) Conditional Assembly Directives

Directive Description Example

IF / ELSE / ENDIF Used for conditional assembly IF DEBUG=1

MACRO / ENDM Defines reusable macros MACRO DELAY

Example: Using a Macro

DELAY MACRO ; Define macro
MOV R7, #255
DJNZ R7, $
ENDM

3. Peripheral ICs and Their Interfacing

Peripheral ICs extend the capabilities of 8051 microcontroller by handling I/O, memory,
communication, and control applications.
(A) Common Peripheral ICs

IC Function

8255 (Programmable Peripheral Interface) Parallel port expansion

8251 (USART) Serial communication

8259 (Interrupt Controller) Handles multiple interrupts

8279 (Keyboard/Display Controller) Interfaces keypad and 7-segment display

ADC0804 (Analog to Digital Converter) Converts analog signals to digital

DAC0808 (Digital to Analog Converter) Converts digital signals to analog

EEPROM (AT24C02, AT24C04) Non-volatile memory storage

LM35 (Temperature Sensor) Measures temperature

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4. Interfacing Peripheral ICs with 8051
(A) Interfacing 8255 (Programmable Peripheral Interface)
• Expands I/O ports using three 8-bit ports (Port A, B, C).
• Controlled using the Control Register.
Example: Writing Data to 8255 Port A
MOV DPTR, #6000H ; Load address of 8255
MOV A, #80H ; Set Port A as output
MOVX @DPTR, A ; Write to Control Register
MOV A, #0FFH ; Data to be sent
MOVX @DPTR, A ; Send data to Port A

(B) Interfacing ADC0804 (Analog to Digital Converter)

• Converts analog input (0-5V) to 8-bit digital output.
• Requires START and EOC (End of Conversion) signals.
Example: Reading from ADC0804
SETB P3.3 ; Start conversion
CLR P3.3 ; Clear start bit
WAIT: JB P3.2, WAIT ; Wait for conversion to complete
MOV A, P1 ; Read digital value from ADC

(C) Interfacing EEPROM (AT24C02) Using I2C

• Uses SDA (Data) and SCL (Clock) pins for communication.
• Stores data permanently.
Example: Writing to EEPROM
MOV A, #50H ; EEPROM address
MOV DPTR, #100H ; Data location
MOVX @DPTR, A ; Write data to EEPROM

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7. 8086 Microprocessor Architecture
1. Introduction
The Intel 8086 is a 16-bit microprocessor introduced in 1978. It is widely known for its role
in the development of x86 architecture. The 8086 is a 16-bit processor, meaning it can
handle data 16 bits wide and processes 16 bits at a time. It was designed for high-
performance computing tasks and had significant influence on modern microprocessor
architecture.

2. 8086 Architecture Overview

The 8086 microprocessor has a 16-bit data bus, a 20-bit address bus, and a segmented
memory model, which allows it to access up to 1MB of memory (2^20 addressable memory
locations). The architecture consists of several functional units and components that work
together for effective processing.
Key Features:
• 16-bit word length.
• 20-bit address bus for accessing 1MB memory.
• Segmented memory model.
• Two operating modes: Minimum mode (single processor) and Maximum mode
(multiprocessor).
• Support for both 16-bit and 8-bit operations.
• Clock speed of 5 MHz to 10 MHz.

3. Functional Units of 8086 Architecture

(A) Arithmetic and Logic Unit (ALU)
• The ALU performs all arithmetic and logical operations, such as addition,
subtraction, AND, OR, etc..
• It works with the data registers and provides results that are stored in registers or
memory.
(B) Register Set
The 8086 contains a set of 14 registers that include general-purpose and special-purpose
registers.
1. General-Purpose Registers (16 bits each)
These are used for data manipulation, address calculations, and temporary storage.

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• AX (Accumulator Register): Often used in arithmetic and I/O operations.
• BX (Base Register): Used for addressing in data segment operations.
• CX (Count Register): Used in loop control, string operations.
• DX (Data Register): Used for I/O operations and as a secondary accumulator.
2. Segment Registers (16 bits each)
Used to hold the segment base addresses for accessing memory in the segmented memory
model.
• CS (Code Segment): Points to the code segment, where the program code is stored.
• DS (Data Segment): Points to the data segment, where variables and arrays are
stored.
• SS (Stack Segment): Points to the stack segment, used for storing temporary data
and function calls.
• ES (Extra Segment): Typically used for extra data storage during string operations.
3. Pointer and Index Registers (16 bits each)
These registers hold addresses of data in memory.
• SP (Stack Pointer): Points to the top of the stack.
• BP (Base Pointer): Used to access data on the stack.
• SI (Source Index): Used in string operations as the source address.
• DI (Destination Index): Used in string operations as the destination address.
4. Flag Register (16 bits)
The Flag Register contains status flags that are updated after every ALU operation. It
includes the following bits:
• Sign Flag (SF): Set if the result of the operation is negative.
• Zero Flag (ZF): Set if the result of the operation is zero.
• Auxiliary Carry Flag (AF): Set if there was a carry from bit 3 in a binary addition.
• Carry Flag (CF): Set if there was a carry in an arithmetic operation.
• Parity Flag (PF): Set if the result has an even number of 1's.
• Overflow Flag (OF): Set if there was a signed overflow during an operation.

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4. 8086 Architecture Blocks
(A) Bus Interface Unit (BIU)
The BIU handles all data transfers to and from memory. It interfaces with the system's
external components and memory by providing the address bus, data bus, and control
signals.
• Instruction Fetch: Fetches the instructions from memory.
• Address Generation: Uses segment registers and offsets to generate physical
addresses.
• Memory Read/Write: Controls memory operations by sending read or write signals.
Components of the BIU:
• Instruction Queue: The 8086 has a 6-byte instruction queue that fetches instructions
in advance to allow pipelining and faster processing. This helps in prefetching
instructions while others are being executed.
• Segment Registers: Contains CS, DS, SS, and ES.
• Physical Address Calculation: Combines segment address and offset address to
generate a 20-bit physical address.
(B) Execution Unit (EU)
The Execution Unit executes the instructions provided by the BIU. It contains the ALU and
the registers used for processing. It is responsible for processing data, controlling flags, and
performing operations.
Components of the EU:
• ALU: Performs arithmetic and logical operations.
• Registers: Holds data and performs calculations.
• Control Unit: Decodes and executes instructions.

5. Addressing Modes in 8086

The 8086 supports several addressing modes to provide flexibility in accessing memory.
Some of the key addressing modes are:
• Immediate Addressing: The operand is a constant (e.g., MOV AX, 55H).
• Register Addressing: The operand is stored in a register (e.g., MOV AX, BX).
• Direct Addressing: The operand is a memory location specified by an address (e.g.,
MOV AX, [2000H]).

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• Indirect Addressing: The operand is at an address stored in a register (e.g., MOV AX,
[BX]).
• Indexed Addressing: Combines a base register (like BX) and an index register (like SI)
to form an address (e.g., MOV AX, [BX + SI]).
• Relative Addressing: Used in branch instructions, the address is determined relative
to the current instruction pointer.

6. Instruction Set of 8086

The 8086 instruction set is divided into several categories:
1. Data Transfer Instructions: Moves data between registers, memory, and I/O.
o Examples: MOV, PUSH, POP, XCHG.
2. Arithmetic Instructions: Perform arithmetic operations like addition, subtraction, etc.
o Examples: ADD, SUB, MUL, DIV.
3. Control Flow Instructions: Used for loops, conditionals, and branching.
o Examples: JMP, CALL, RET, LOOP.
4. Logical Instructions: Perform logical operations (AND, OR, NOT, etc.).
o Examples: AND, OR, XOR, NOT.
5. String Instructions: Used for operations on strings (e.g., move, compare, scan).
o Examples: MOVS, CMPS, SCAS.
6. Comparison Instructions: Compare two values and set flags accordingly.
o Examples: CMP, TEST.

7. Pin Configuration of 8086

The 8086 microprocessor has a 40-pin package. The key pins include:
• Address Pins (A0-A19): 20 address lines for accessing memory.
• Data Pins (D0-D15): 16 data lines for data transfer.
• Control Pins: Include signals like M/IO, RD, WR, ALE, etc.
• Interrupt Pins: Includes INTA, INTR, and NMI for interrupt handling.
• Clock Pin (CLK): Provides clock signal for the operation.

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8. 8086 Instruction Set
The 8086 microprocessor has a comprehensive instruction set that can be categorized
based on their functionality. These instructions help the microprocessor to perform a wide
range of operations such as data transfer, arithmetic and logical operations, branching,
string manipulation, and control. The instructions in the 8086 can operate on 16-bit
registers, memory, and input/output ports.

1. Instruction Categories
The 8086 instruction set is divided into several key categories based on their operations:
1. Data Transfer Instructions
These instructions are used to transfer data between registers, memory, and I/O ports.

Instruction Description Example

MOV Move data from source to MOV AX, 50H (Move the value 50H into AX)
destination

PUSH Push data onto the stack PUSH AX (Push the value in AX to the stack)

POP Pop data from the stack POP AX (Pop the top value from the stack
into AX)

XCHG Exchange values between XCHG AX, BX (Exchange the values in AX and
two operands BX)

IN Input data from an I/O port IN AL, 60H (Read data from port 60H into AL)

OUT Output data to an I/O port OUT 60H, AL (Send the value in AL to port
60H)

2. Arithmetic Instructions
These instructions perform arithmetic operations such as addition, subtraction,
multiplication, and division.

Instruction Description Example

ADD Add two operands and store the ADD AX, BX (AX = AX + BX)
result

SUB Subtract one operand from SUB AX, 5 (AX = AX - 5)

another

INC Increment an operand by 1 INC AX (AX = AX + 1)

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DEC Decrement an operand by 1 DEC BX (BX = BX - 1)

MUL Multiply unsigned operands MUL BX (AX = AX * BX)

IMUL Multiply signed operands IMUL BX (AX = AX * BX, signed

multiplication)

DIV Divide unsigned operands DIV BX (AX = AX / BX, result stored in

AX)

IDIV Divide signed operands IDIV BX (AX = AX / BX, signed division)

NEG Negate an operand NEG AX (AX = -AX)

3. Logical Instructions
These instructions perform logical operations like AND, OR, XOR, etc.

Instruction Description Example

AND Perform bitwise AND between two AND AX, BX (AX = AX AND BX)
operands

OR Perform bitwise OR between two OR AX, 1 (AX = AX OR 1)

operands

XOR Perform bitwise XOR between two XOR AX, BX (AX = AX XOR BX)
operands

NOT Perform bitwise NOT (invert bits) NOT AX (AX = NOT AX)

TEST Perform bitwise AND and set flags based TEST AX, BX (Sets flags based on
on the result AX AND BX)

4. Comparison Instructions
Comparison instructions compare two operands by subtracting them, and set the flags
accordingly.

Instruction Description Example

CMP Compare two operands by CMP AX, BX (Compares AX and BX by

subtracting them performing AX - BX)

CMPS Compare two strings CMPS (Compare bytes or words pointed

to by SI and DI)

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5. Control Transfer Instructions
These instructions alter the flow of program execution.

Instruction Description Example

JMP Unconditional jump to a JMP 1000H (Jump to address 1000H)

specified address

CALL Call a procedure or subroutine CALL 2000H (Call subroutine at address

2000H)

RET Return from a procedure or RET (Return from the current subroutine)
subroutine

JZ Jump if zero flag is set (if result JZ 2000H (Jump to 2000H if the zero flag is
of previous operation was zero) set)

JNZ Jump if zero flag is not set JNZ 2000H (Jump to 2000H if the zero flag
is not set)

JC Jump if carry flag is set JC 3000H (Jump to 3000H if carry flag is

set)

JNC Jump if carry flag is not set JNC 3000H (Jump to 3000H if carry flag is
not set)

JO Jump if overflow flag is set JO 4000H (Jump to 4000H if overflow flag

is set)

JNO Jump if overflow flag is not set JNO 4000H (Jump to 4000H if overflow
flag is not set)

6. String Instructions
These instructions are used for string manipulation (e.g., moving, comparing, and scanning
data in memory).

Instruction Description Example

MOVS Move data from source string to MOVS (Moves data from DS:SI to
destination string ES:DI)

CMPS Compare two strings CMPS (Compares the source and

destination strings)

SCAS Scan a string for a particular byte or SCAS (Compares AL with the byte
word at ES:DI)

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LODS Load data from the source string to the LODS (Loads data from DS:SI to AL
accumulator or AX)

STOS Store data from the accumulator into STOS (Stores data from AL or AX to
the destination string ES:DI)

7. Shift and Rotate Instructions

Shift and rotate instructions are used to manipulate the bits of a register or memory
operand.

Instruction Description Example

SHL (SAL) Shift left (arithmetic left) SHL AX, 1 (Shift AX left by 1 bit)

SHR Shift right (logical right) SHR AX, 1 (Shift AX right by 1 bit)

SAL Shift left (arithmetic shift left, same SAL AX, 1 (Shift AX left by 1 bit)
as SHL)

SAR Shift right (arithmetic shift right) SAR AX, 1 (Shift AX right by 1 bit,
preserve sign)

ROL Rotate left ROL AX, 1 (Rotate AX left by 1 bit)

ROR Rotate right ROR AX, 1 (Rotate AX right by 1 bit)

8. Interrupt Instructions
These instructions handle interrupts for hardware and software events.

Instruction Description Example

INT Software interrupt INT 21H (Invoke software interrupt 21H)

INTO Interrupt on overflow INTO (Triggers interrupt if overflow flag is set)

IRET Return from interrupt IRET (Return from interrupt service routine)

9. Features of the Pentium and Its Derivatives

The Pentium microprocessor family, introduced by Intel in 1993, revolutionized the
computing world with its advanced architecture, high performance, and enhanced
capabilities compared to previous processors like the 386 and 486. Since its introduction,
Pentium processors have evolved into multiple derivatives, with each generation bringing
improvements in performance, energy efficiency, and new features to keep pace with
modern computing demands.

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1. Pentium (Original) Features
The original Pentium processor, introduced in 1993, was the first to feature dual pipelines, a
key innovation that allowed it to execute two instructions per clock cycle. Here are some key
features:
Key Features of the Pentium Processor:
1. Dual-Pipelined Architecture:
o The original Pentium introduced superscalar architecture, allowing the
processor to execute two instructions simultaneously in parallel, effectively
increasing throughput.
o It had two execution units: one for integer operations and another for
floating-point operations.
2. Clock Speed:
o Initially available in clock speeds of 60 MHz, 66 MHz, and later higher speeds
(up to 200 MHz in some early models).
3. 32-bit Data Bus:
o The Pentium had a 32-bit data bus, meaning it could handle 32 bits of data at
a time, making it significantly faster than its predecessors (the 486 with a 32-
bit internal architecture but a 16-bit data bus).
4. 32-bit and 64-bit Support:
o The Pentium was designed to support 32-bit processing (addressing and
instructions). It could address up to 4 GB of memory, but the processor could
also handle some 64-bit operations for certain tasks, such as floating-point
calculations.
5. Floating-Point Unit (FPU):
o A dedicated FPU was included, which allowed for better performance in
handling complex mathematical computations (important for scientific,
engineering, and graphics applications).
6. MMX Technology:
o Some Pentium processors included MMX (Multimedia Extensions), a set of
instructions that enhanced performance for multimedia applications (audio,
video, and graphics). This allowed for more efficient multimedia data
processing.

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7. Cache Memory:
o The original Pentium supported 8 KB L1 cache to speed up access to
frequently used data, reducing the time it took to fetch information from the
main memory.
8. Pipeline Depth:
o The original Pentium processor had a 5-stage pipeline to break down the
execution of instructions into smaller stages, improving the throughput and
reducing delays between executing instructions.

2. Pentium MMX
Released in 1996, the Pentium MMX was an enhancement of the original Pentium,
specifically designed to improve performance in multimedia applications. MMX instructions
provided a significant boost for multimedia workloads.
Key Features of Pentium MMX:
1. MMX Technology:
o The MMX (Multimedia Extensions) instructions allowed the processor to
handle SIMD (Single Instruction, Multiple Data) operations, enabling faster
processing of multimedia data.
o This technology provided hardware acceleration for tasks such as image
processing, audio decoding, and 3D graphics rendering.
2. Improved Performance:
o Enhanced integer processing for multimedia tasks.
o Up to 32 MMX instructions were added to the Pentium, including operations
for video compression, audio manipulation, and graphic rendering.
3. Increased Clock Speeds:
o The Pentium MMX was available in higher clock speeds (up to 233 MHz),
offering a performance boost for certain types of applications.

3. Pentium Pro
Introduced in 1995, the Pentium Pro was aimed at the high-performance workstation and
server markets. It featured an advanced superscalar architecture and out-of-order
execution, which set it apart from the original Pentium.

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Key Features of Pentium Pro:
1. Advanced Superscalar Architecture:
o The Pentium Pro was designed to execute multiple instructions per clock
cycle. It had dual pipelines and could execute instructions in out-of-order
execution to optimize performance.
2. Out-of-Order Execution:
o The Pentium Pro could execute instructions out of order based on the
availability of resources, which helped improve performance by filling idle
execution units.
3. Enhanced L2 Cache:
o The Pentium Pro supported an external L2 cache (256 KB to 1 MB), which
greatly improved performance in tasks that required frequent access to
memory.
4. 64-bit Addressing:
o Although it was marketed as a 32-bit processor, the Pentium Pro had 64-bit
internal registers, allowing it to process 64-bit data internally, making it more
powerful for certain scientific and engineering applications.

4. Pentium II
The Pentium II, launched in 1997, was a significant advancement, especially in terms of
multimedia performance, and it was based on the Pentium Pro core with improvements to
meet the needs of the consumer market.
Key Features of Pentium II:
1. Slot 1 Design:
o Unlike its predecessors, the Pentium II used the Slot 1 interface, which
allowed for easy installation on motherboards, with a separate slot for the
processor and cache.
2. MMX Technology:
o Included MMX technology for multimedia performance, improving tasks like
video encoding and decoding.
3. Multimedia Instructions:
o Introduced SIMD instructions for better graphics, 3D rendering, and
multimedia applications.

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4. L2 Cache:
o Integrated 512 KB to 1 MB of L2 cache on the processor, providing faster
access to data for applications.
5. Higher Clock Speeds:
o The Pentium II reached up to 450 MHz in later stages, offering better overall
performance compared to its predecessors.

5. Pentium III
The Pentium III processor, released in 1999, brought further improvements in performance,
especially in terms of speed, multimedia capabilities, and the use of advanced technologies.
Key Features of Pentium III:
1. SSE (Streaming SIMD Extensions):
o Introduced the SSE instruction set, which provided hardware acceleration for
multimedia and 3D graphics.
o SSE was a key improvement over MMX, offering improved floating-point
performance for multimedia applications.
2. Clock Speeds:
o The Pentium III was available in speeds ranging from 450 MHz to 1.4 GHz,
making it one of the faster processors of its time.
3. Improved Cache:
o The Pentium III included an integrated L2 cache of up to 512 KB for better
performance.
4. Internet Streaming and Multimedia:
o The Pentium III was optimized for streaming media, making it ideal for
internet applications and rich multimedia content.

6. Pentium 4
The Pentium 4, released in 2000, was designed with higher clock speeds and larger caches,
making it suitable for performance-intensive tasks.

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Key Features of Pentium 4:
1. NetBurst Microarchitecture:
o The Pentium 4 was based on the NetBurst microarchitecture, which was
designed to achieve high clock speeds (up to 3.8 GHz and beyond) for better
performance.
2. Hyper-Threading Technology:
o Introduced Hyper-Threading (HT), which allowed each core to execute two
threads simultaneously, improving the processor's efficiency in multitasking
environments.
3. L2 Cache:
o The Pentium 4 featured 256 KB to 1 MB of L2 cache for faster access to
frequently used data.
4. Enhanced Multimedia Performance:
o The Pentium 4 also included SSE2 instructions for better performance in
multimedia, floating-point operations, and 3D rendering.

7. Pentium D
The Pentium D series, launched in 2005, marked the introduction of dual-core processors to
the Pentium line, providing substantial improvements in multitasking and parallel
processing.
Key Features of Pentium D:
1. Dual-Core Architecture:
o The Pentium D featured two cores on a single chip, each capable of executing
instructions independently, significantly improving multitasking performance.
2. Enhanced Performance:
o The dual-core architecture, along with Hyper-Threading, allowed for better
performance in parallel processing tasks and multitasking.
3. L2 Cache:
o The Pentium D processors included up to 2 MB L2 cache per core for faster
data access.

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