DIGITAL FAQ

1) What are different ways to synchronize between two clock domains?

The following section explains clock domain interfacing
One of the biggest challenges of system-on-chip (SOC) designs is that different blocks
operate on independent clocks. Integrating these blocks via the processor bus, memory
ports, peripheral busses, and other interfaces can be troublesome because unpredictable
behavior can result when the asynchronous interfaces are not properly synchronized.
A very common and robust method for synchronizing multiple data signals is a
handshake technique as shown in diagram below This is popular because the handshake
technique can easily manage changes in clock frequencies, while minimizing latency at
the crossing. However, handshake logic is significantly more complex than standard
synchronization structures.

FSM1(Transmitter) asserts the req (request) signal, asking the receiver to accept the data
on the data bus. FSM2(Receiver) generally a slow module asserts the ack (acknowledge)
signal, signifying that it has accepted the data.
it has loop holes: when system Receiver samples the systems Transmitter req line and
Transmitter samples system Receiver ack line, they have done it with respect to their
internal clock, so there will be setup and hold time violation. To avoid this we go for
double or triple stage synchronizers, which increase the MTBF and thus are immune to
meta stability to a good extent. The figure below shows how this is done.
2) Blocking vs Non-Blocking. . .

self triggering blocks -

module osc2 (clk);
output clk;
reg clk;
initial #10 clk = 0;
always @(clk) #10 clk <= ~clk;
endmodule
After the first @(clk) trigger, the RHS expression of the nonblocking assignment is
evaluated and the LHS value scheduled into the nonblocking assign updates event
queue.
Before the nonblocking assign updates event queue is "activated," the @(clk) trigger
statement is encountered and the always block again becomes sensitive to changes on
the clk signal. When the nonblocking LHS value is updated later in the same time step,
the @(clk) is again triggered.
module osc1 (clk);
output clk;
reg clk;
initial #10 clk = 0;
always @(clk) #10 clk = ~clk;
endmodule
Blocking assignments evaluate their RHS expression and update their LHS value
without interruption. The blocking assignment must complete before the @(clk) edge-
trigger event can be scheduled. By the time the trigger event has been scheduled, the
blocking clk assignment has completed; therefore, there is no trigger event from within
the always block to trigger the @(clk) trigger.
Bad modeling: - (using blocking for seq. logic)
always @(posedge clk) begin
q1 = d;
q2 = q1;
q3 = q2;
end

Race Condition
always @(posedge clk) q1=d;
always @(posedge clk) q2=q1;
always @(posedge clk) q3=q2;
always @(posedge clk) q2=q1;
always @(posedge clk) q3=q2;
always @(posedge clk) q1=d;
always @(posedge clk) begin
q3 = q2;
q2 = q1;
q1 = d;
end
3)
Bad style but still works

Good modeling: -
always @(posedge clk) begin
q1 <= d;
q2 <= q1;
q3 <= q2;
end
always @(posedge clk) begin
q3 <= q2;
q2 <= q1;
q1 <= d;
end
No matter of sequence for Nonblocking
always @(posedge clk) q1<=d;
always @(posedge clk) q2<=q1;
always @(posedge clk) q3<=q2;
always @(posedge clk) q2<=q1;
always @(posedge clk) q3<=q2;
always @(posedge clk) q1<=d;
Good Combinational logic :- (Blocking)
always @(a or b or c or d) begin
tmp1 = a & b;
tmp2 = c & d;
y = tmp1 | tmp2;
end
Bad Combinational logic :- (Nonblocking)
always @(a or b or c or d) begin will simulate incorrectly…
tmp1 <= a & b; need tmp1, tmp2 insensitivity
tmp2 <= c & d;
y <= tmp1 | tmp2;
end
Mixed design: -
Use Nonblocking [Link] case on multiple non-blocking assignments last one
will win.
4) Verilog FSM

5) Explain about setup time and hold time, what will happen if there is setup time and
hold tine violation, how to overcome this?
Set up time is the amount of time before the clock edge that the input signal needs to be
stable to guarantee it is accepted properly on the clock edge.
Hold time is the amount of time after the clock edge that same input signal has to be
held before changing it to make sure it is sensed properly at the clock edge.
Whenever there are setup and hold time violations in any flip-flop, it enters a state where
its output is unpredictable: this state is known as metastable state (quasi stable state); at
the end of metastable state, the flip-flop settles down to either '1' or '0'. This whole
process is known as metastability
6) What is skew, what are problems associated with it and how to minimize it?
In circuit design, clock skew is a phenomenon in synchronous circuits in which the
clock signal (sent from the clock circuit) arrives at different components at different
times.
This is typically due to two causes. The first is a material flaw, which causes a signal
to travel faster or slower than expected. The second is distance: if the signal has to
travel the entire length of a circuit, it will likely (depending on the circuit's size) arrive
 at different parts of the circuit at different times. Clock skew can cause harm in two
ways. Suppose that a logic path travels through combinational logic from a source flip-
flop to a destination flip-flop. If the destination flip-flop receives the clock tick later
than the source flip-flop, and if the logic path delay is short enough, then the data
signal might arrive at the destination flip-flop before the clock tick, destroying there
the previous data that should have been clocked through. This is called a hold violation
because the previous data is not held long enough at the destination flip-flop to be
properly clocked through. If the destination flip-flop receives the clock tick earlier
than the source flip-flop, then the data signal has that much less time to reach the
destination flip-flop before the next clock tick. If it fails to do so, a setup violation
occurs, so-called because the new data was not set up and stable before the next clock
tick arrived. A hold violation is more serious than a setup violation because it cannot
be fixed by increasing the clock period.
Clock skew, if done right, can also benefit a circuit. It can be intentionally introduced
to decrease the clock period at which the circuit will operate correctly, and/or to
increase the setup or hold safety margins. The optimal set of clock delays is
determined by a linear program, in which a setup and a hold constraint appears for
each logic path. In this linear program, zero clock skew is merely a feasible point.
Clock skew can be minimized by proper routing of clock signal (clock distribution
tree) or putting variable delay buffer so that all clock inputs arrive at the same time
7) What is slack?

'Slack' is the amount of time you have that is measured from when an event 'actually
happens' and when it 'must happen’.. The term 'actually happens' can also be taken as
being a predicted time for when the event will 'actually happen'.
When something 'must happen' can also be called a 'deadline' so another definition of
slack would be the time from when something 'actually happens' (call this Tact) until
the deadline (call this Tdead).
Slack = Tdead - Tact.
Negative slack implies that the 'actually happen' time is later than the 'deadline'
time...in other words it's too late and a timing violation....you have a timing problem
that needs some attention.
8) Given only two xor gates one must function as buffer and another as inverter?

Tie one of xor gates input to 1 it will act as inverter.

Tie one of xor gates input to 0 it will act as buffer.

6) What is difference between latch and flipflop?

The main difference between latch and FF is that latches are level sensitive while FF
are edge sensitive. They both require the use of clock signal and are used in sequential
logic. For a latch, the output tracks the input when the clock signal is high, so as long
as the clock is logic 1, the output can change if the input also changes. FF on the other
hand, will store the input only when there is a rising/falling edge of the clock.
 9) What is glitch? What causes it (explain with waveform)? How to overcome it?
The following figure shows a synchronous alternative to the gated clock using a data
path. The flip-flop is clocked at every clock cycle and the data path is controlled by an
enable. When the enable is Low, the multiplexer feeds the output of the register back
on itself. When the enable is High, new data is fed to the flip-flop and the register
changes its state

7) Build a 4:1 mux using only 2:1 MUX?

Difference between heap and stack?

The Stack is more or less responsible for keeping track of what's executing in our code (or
what's been "called"). The Heap is more or less responsible for keeping track of our objects
(our data, well... most of it - we'll get to that later.).
Think of the Stack as a series of boxes stacked one on top of the next. We keep track of
what's going on in our application by stacking another box on top every time we call a
method (called a Frame). We can only use what's in the top box on the stack. When we're
done with the top box (the method is done executing) we throw it away and proceed to use
the stuff in the previous box on the top of the stack. The Heap is similar except that its
purpose is to hold information (not keep track of execution most of the time) so anything in
our Heap can be accessed at any time. With the Heap, there are no constraints as to what can
be accessed like in the stack. The Heap is like the heap of clean laundry on our bed that we
have not taken the time to put away yet - we can grab what we need quickly. The Stack is
like the stack of shoe boxes in the closet where we have to take off the top one to get to the
one underneath it.

9) Difference between mealy and moore state machine?

A) Mealy and Moore models are the basic models of state machines. A state machine which
uses only Entry Actions, so that its output depends on the state, is called a Moore model. A
state machine which uses only Input Actions, so that the output depends on the state and also
on inputs, is called a Mealy model. The models selected will influence a design but there are
no general indications as to which model is better. Choice of a model depends on the
application, execution means (for instance, hardware systems are usually best realized as
Moore models) and personal preferences of a designer or programmer

B) Mealy machine has outputs that depend on the state and input (thus, the FSM has the
output written on edges)
Moore machine has outputs that depend on state only (thus, the FSM has the output written
in the state itself.

Adv and Disadv

In Mealy as the output variable is a function both input and state, changes of state of the state
variables will be delayed with respect to changes of signal level in the input variables, there
are possibilities of glitches appearing in the output variables. Moore overcomes glitches as
output dependent on only states and not the input signal level.
All of the concepts can be applied to Moore-model state machines because any Moore state
machine can be implemented as a Mealy state machine, although the converse is not true.
Moore machine: the outputs are properties of states themselves... which means that you get
the output after the machine reaches a particular state, or to get some output your machine
has to be taken to a state which provides you the [Link] outputs are held until you go to
some other state Mealy machine:
Mealy machines give you outputs instantly, that is immediately upon receiving input, but the
output is not held after that clock cycle.
10) Difference between onehot and binary encoding?

Common classifications used to describe the state encoding of an FSM are Binary (or highly
encoded) and One hot.
A binary-encoded FSM design only requires as many flip-flops as are needed to uniquely
encode the number of states in the state machine. The actual number of flip-flops required is
equal to the ceiling of the log-base-2 of the number of states in the FSM.
A onehot FSM design requires a flip-flop for each state in the design and only one flip-flop
(the flip-flop representing the current or "hot" state) is set at a time in a one hot FSM design.
For a state machine with 9- 16 states, a binary FSM only requires 4 flip-flops while a onehot
FSM requires a flip-flop for each state in the design
FPGA vendors frequently recommend using a onehot state encoding style because flip-flops
are plentiful in an FPGA and the combinational logic required to implement a onehot FSM
design is typically smaller than most binary encoding styles. Since FPGA performance is
typically related to the combinational logic size of the FPGA design, onehot FSMs typically
run faster than a binary encoded FSM with larger combinational logic blocks

12) How to calculate maximum operating frequency?

13) How to find out longest path?

You can find answer to this in [Link] of presentations section on this site

15) How to achieve 180 degree exact phase shift?

Never tell using inverter

a) dcm’s an inbuilt resource in most of fpga can be configured to get 180 degree phase shift.
b) Bufgds that is differential signaling buffers which are also inbuilt resource of most of
FPGA can be used.
17) Tell some of applications of buffer?

a)They are used to introduce small delays

b)They are used to eliminate cross talk caused due to inter electrode capacitance due to close
routing.
c)They are used to support high fanout,eg:bufg

14) Draw the state diagram to output a "1" for one cycle if the sequence "0110" shows
up (the leading 0s cannot be used in more than one sequence)?
16) What is significance of ras and cas in SDRAM?

SDRAM receives its address command in two address words.

It uses a multiplex scheme to save input pins. The first address word is latched into the
DRAM chip with the row address strobe (RAS).
Following the RAS command is the column address strobe (CAS) for latching the second
address word.
Shortly after the RAS and CAS strobes, the stored data is valid for reading.

18) Implement an AND gate using mux?

This is the basic question that many interviewers ask. for and gate, give one input as select
line,incase if u r giving b as select line, connect one input to logic '0' and other input to a.

19) What will happen if contents of register are shifter left, right?

It is well known that in left shift all bits will be shifted left and LSB will be appended with 0
and in right shift all bits will be shifted right and MSB will be appended with 0 this is a
straightforward answer

What is expected is in a left shift value gets Multiplied by 2 eg:consider 0000_1110=14 a left
shift will make it 0001_110=28, it the same fashion right shift will Divide the value by 2.
20)Given the following FIFO and rules, how deep does the FIFO need to be to prevent
underflow or overflow?

RULES:
1) frequency(clk_A) = frequency(clk_B) / 4
2) period(en_B) = period(clk_A) * 100
3) duty_cycle(en_B) = 25%

Assume clk_B = 100MHz (10ns)

From (1), clk_A = 25MHz (40ns)
From (2), period(en_B) = 40ns * 400 = 4000ns, but we only output for
1000ns,due to (3), so 3000ns of the enable we are doing no output work. Therefore, FIFO
size = 3000ns/40ns = 75 entries.

21) Design a four-input NAND gate using only two-input NAND gates ?

A:Basically, you can tie the inputs of a NAND gate together to get an inverter, so...

22)Difference between Synchronous and Asynchronous reset.?

Synchronous reset logic will synthesize to smaller flip-flops, particularly if the reset is gated
with the logic generating the d-input. But in such a case, the combinational logic gate count
grows, so the overall gate count savings may not be that significant.
The clock works as a filter for small reset glitches; however, if these glitches occur near the
active clock edge, the Flip-flop could go metastable. In some designs, the reset must be
generated by a set of internal conditions. A synchronous reset is recommended for these
types of designs because it will filter the logic equation glitches between clock.

Disadvantages of synchronous reset:

Problem with synchronous resets is that the synthesis tool cannot easily distinguish the reset
signal from any other data signal.
Synchronous resets may need a pulse stretcher to guarantee a reset pulse width wide enough
to ensure reset is present during an active edge of the clock[ if you have a gated clock to save
power, the clock may be disabled coincident with the assertion of reset. Only an
asynchronous reset will work in this situation, as the reset might be removed prior to the
resumption of the clock.
Designs that are pushing the limit for data path timing, can not afford to have added gates
and additional net delays in the data path due to logic inserted to handle synchronous resets.
Asynchronous reset :
The biggest problem with asynchronous resets is the reset release, also called reset removal.
Using an asynchronous reset, the designer is guaranteed not to have the reset added to the
data path. Another advantage favoring asynchronous resets is that the circuit can be reset
with or without a clock present.
Disadvantages of asynchronous reset: ensure that the release of the reset can occur within
one clock period. if the release of the reset occurred on or near a clock edge such that the
flip-flops went metastable.

23) Why are most interrupts active low?

This answers why most signals are active low

If you consider the transistor level of a module, active low means the capacitor in the output
terminal gets charged or discharged based on low to high and high to low transition
respectively. when it goes from high to low it depends on the pull down resistor that pulls it
down and it is relatively easy for the output capacitance to discharge rather than charging.
hence people prefer using active low signals.

24)Give two ways of converting a two input NAND gate to an inverter?

(a) short the 2 inputs of the nand gate and apply the single input to it.
(b) Connect the output to one of the input and the other to the input signal.

25) What are set up time & hold time constraints? What do they signify? Which one is
critical for estimating maximum clock frequency of a circuit?

set up time: - the amount of time the data should be stable before the application of the clock
signal, where as the hold time is the amount of time the data should be stable after the
application of the clock. Setup time signifies maximum delay constraints; hold time is for
minimum delay constraints. Setup time is critical for establishing the maximum clock
frequency.

26) Differences between D-Latch and D flip-flop?

D-latch is level sensitive where as flip-flop is edge sensitive. Flip-flops are made up of
latches.

27) What is a multiplexer?

Is a combinational circuit that selects binary information from one of many input lines and
directs it to a single output line. (2n =>n).
28)How can you convert an SR Flip-flop to a JK Flip-flop?
By giving the feed back we can convert, i.e !Q=>S and Q=>[Link] the S and R inputs will
act as J and K respectively.
29)How can you convert the JK Flip-flop to a D Flip-flop?

By connecting the J input to the K through the inverter.

30)What is Race-around problem?How can you rectify it?

The clock pulse that remains in the 1 state while both J and K are equal to 1 will cause the
output to complement again and repeat complementing until the pulse goes back to 0, this is
called the race around [Link] avoid this undesirable operation, the clock pulse must
have a time duration that is shorter than the propagation delay time of the F-F, this is
restrictive so the alternative is master-slave or edge-triggered construction.

31)How do you detect if two 8-bit signals are same?

XOR each bits of A with B (for e.g. A[0] xor B[0] ) and so [Link] o/p of 8 xor gates are then
given as i/p to an 8-i/p nor gate. if o/p is 1 then A=B.

32)7 bit ring counter's initial state is 0100010. After how many clock cycles will it
return to the initial state?

6 cycles

33) Convert D-FF into divide by 2. (not latch) What is the max clock frequency the
circuit can handle, given the following information?

T_setup= 6nS T_hold = 2nS T_propagation = 10nS

Circuit: Connect Qbar to D and apply the clk at clk of DFF and take the O/P at Q. It gives
freq/2. Max. Freq of operation: 1/ (propagation delay+setup time) = 1/16ns = 62.5 MHz

34)Guys this is the basic question asked most frequently. Design all the basic
gates(NOT,AND,OR,NAND,NOR,XOR,XNOR) using 2:1 Multiplexer?

Using 2:1 Mux, (2 inputs, 1 output and a select line)

(a) NOT
Give the input at the select line and connect I0 to 1 & I1 to 0. So if A is 1, we will get I1 that
is 0 at the O/P.
(b) AND
Give input A at the select line and 0 to I0 and B to I1. O/p is A & B
(c) OR
Give input A at the select line and 1 to I1 and B to I0. O/p will be A | B
(d) NAND
AND + NOT implementations together
(e) NOR
OR + NOT implementations together
(f) XOR
A at the select line B at I0 and ~B at I1. ~B can be obtained from (a) (g) XNOR
A at the select line B at I1 and ~B at I0

35)N number of XNOR gates are connected in series such that the N inputs
(A0,A1,A2......) are given in the following way: A0 & A1 to first XNOR gate and A2 &
O/P of First XNOR to second XNOR gate and so on..... Nth XNOR gates output is final
output. How does this circuit work? Explain in detail?

If N=Odd, the circuit acts as even parity detector, ie the output will 1 if there are even
number of 1's in the N input...This could also be called as odd parity generator since with this
additional 1 as output the total number of 1's will be ODD.
If N=Even, just the opposite, it will be Odd parity detector or Even Parity Generator.

36)An assembly line has 3 fail safe sensors and one emergency shutdown [Link]
line should keep moving unless any of the following conditions arise:
(i) If the emergency switch is pressed
(ii) If the senor1 and sensor2 are activated at the same time.
(iii) If sensor 2 and sensor3 are activated at the same time.
(iv) If all the sensors are activated at the same time
Suppose a combinational circuit for above case is to be implemented only with NAND
Gates. How many minimum number of 2 input NAND gates are required?

No of 2-input NAND Gates required = 6 You can try the whole implementation.

37)Design a circuit that calculates the square of a number? It should not use any
multiplier circuits. It should use Multiplexers and other logic?

This is interesting....
1^2=0+1=1
2^2=1+3=4
3^2=4+5=9
4^2=9+7=16
5^2=16+9=25
and so on
See a pattern yet?To get the next square, all you have to do is add the next odd number to the
previous square that you [Link] how 1,3,5,7 and finally 9 are [Link]'t this be a
possible solution to your question since it only will use a counter,multiplexer and a couple of
adders?It seems it would take n clock cycles to calculate square of n.

38) How will you implement a Full subtractor from a Full adder?
all the bits of subtrahend should be connected to the xor gate. Other input to the xor being
[Link] input carry bit to the full adder should be made 1. Then the full adder works like a
full subtractor
39)A very good interview question... What is difference between setup and hold time.
The interviewer was looking for one specific reason , and its really a good answer
too..The hint is hold time doesn't depend on clock, why is it so...?

Setup violations are related to two edges of clock, i mean you can vary the clock frequency
to correct setup violation. But for hold time, you are only concerned with one edge and does
not basically depend on clock frequency.

40)In a 3-bit Johnson's counter what are the unused states?

2(power n)-2n is the one used to find the unused states in johnson counter.
So for a 3-bit counter it is 8-6=[Link] states=2. the two unused states are 010 and 101.

48) Draw timing diagrams for following circuit.?

51)Design a FSM (Finite State Machine) to detect a sequence 10110?

41)The question is to design minimal hardware system, which encrypts 8-bit parallel
data. A synchronized clock is provided to this system as well. The output encrypted
data should be at the same rate as the input data but no necessarily with the same
phase?

The encryption system is centered around a memory device that perform a LUT (Look-Up
Table) conversion. This memory functionality can be achieved by using a PROM, EPROM,
FLASH and etc. The device contains an encryption code, which may be burned into the
device with an external programmer. In encryption operation, the data_in is an address
pointer into a memory cell and the combinatorial logic generates the control signals. This
creates a read access from the memory. Then the memory device goes to the appropriate
address and outputs the associate data. This data represent the data_in after encryption.

41) What is an LFSR .List a few of its industry applications.?

LFSR is a linear feedback shift register where the input bit is driven by a linear function of
the overall shift register value. coming to industrial applications, as far as I know, it is used
for encryption and decryption and in BIST(built-in-self-test) based applications..

42)what is false path?how it determine in ckt? what the effect of false path in ckt?

By timing all the paths in the circuit the timing analyzer can determine all the critical paths in
the circuit. However, the circuit may have false paths, which are the paths in the circuit
which are never exercised during normal circuit operation for any set of inputs.
An example of a false path is shown in figure below. The path going from the input A of the
first MUX through the combinational logic out through the B input of the second MUS is a
false path. This path can never be activated since if the A input of the first MUX is activated,
then Sel line will also select the A input of the second MUX.
STA (Static Timing Analysis) tools are able to identify simple false paths; however they are
not able to identify all the false paths and sometimes report false paths as critical paths.
Removal of false paths makes circuit testable and its timing performance predictable
(sometimes faster)

43)Consider two similar processors, one with a clock skew of 100ps and other with a
clock skew of 50ps. Which one is likely to have more power? Why?

Clock skew of 50ps is more likely to have clock power. This is because it is likely that low-
skew processor has better designed clock tree with more powerful and number of buffers and
overheads to make skew better.

44)What are multi-cycle paths?

Multi-cycle paths are paths between registers that take more than one clock cycle to become
stable.
For ex. Analyzing the design shown in fig below shows that the output SIN/COS requires 4
clock-cycles after the input ANGLE is latched in. This means that the combinatorial block
(the Unrolled Cordic) can take up to 4 clock periods (25MHz) to propagate its result. Place
and Route tools are capable of fixing multi-cycle paths problem.
45)You have two counters counting upto 16, built from negedge DFF , First circuit is
synchronous and second is "ripple" (cascading), Which circuit has a less propagation
delay? Why?

The synchronous counter will have lesser delay as the input to each flop is readily available
before the clock edge. Whereas the cascade counter will take long time as the output of one
flop is used as clock to the other. So the delay will be propagating. For Eg: 16 state counter =
4 bit counter = 4 Flip flops Let 10ns be the delay of each flop The worst case delay of ripple
counter = 10 * 4 = 40ns The delay of synchronous counter = 10ns only.(Delay of 1 flop)

46) what is difference between RAM and FIFO?

FIFO does not have address lines

Ram is used for storage purpose where as fifo is used for synchronization purpose i.e. when
two peripherals are working in different clock domains then we will go for fifo.

47)The circle can rotate clockwise and back. Use minimum hardware to build a circuit
to indicate the direction of rotating.?

2 sensors are required to find out the direction of rotating. They are placed like at the
drawing. One of them is connected to the data input of D flip-flop,and a second one - to the
clock input. If the circle rotates the way clock sensor sees the light first while D input
(second sensor) is zero - the output of the flip-flop equals zero, and if D input sensor "fires"
first - the output of the flip-flop becomes high.

49)Implement the following circuits:

(a) 3 input NAND gate using min no of 2 input NAND Gates
(b) 3 input NOR gate using min no of 2 inpur NOR Gates
(c) 3 input XNOR gate using min no of 2 inpur XNOR Gates
Assuming 3 inputs A,B,C?
3 input NAND:
Connect :
a) A and B to the first NAND gate
b) Output of first Nand gate is given to the two inputs of the second NAND gate (this
basically realizes the inverter functionality)
c) Output of second NAND gate is given to the input of the third NAND gate, whose other
input is C
((A NAND B) NAND (A NAND B)) NAND C Thus, can be implemented using '3' 2-input
NAND gates. I guess this is the minimum number of gates that need to be used.
3 input NOR:
Same as above just interchange NAND with NOR ((A NOR B) NOR (A NOR B)) NOR C
3 input XNOR:
Same as above except the inputs for the second XNOR gate, Output of the first XNOR gate
is one of the inputs and connect the second input to ground or logical '0'
((A XNOR B) XNOR 0)) XNOR C

50) Is it possible to reduce clock skew to zero? Explain your answer ?

Even though there are clock layout strategies (H-tree) that can in theory reduce clock skew to
zero by having the same path length from each flip-flop from the pll, process variations in R
and C across the chip will cause clock skew as well as a pure H-Tree scheme is not practical
(consumes too much area).

52)Convert D-FF into divide by 2. (not latch)? What is the max clock frequency of the
circuit , given the following information?
T_setup= 6nS
T_hold = 2nS
T_propagation = 10nS

Circuit:
Connect Qbar to D and apply the clk at clk of DFF and take the O/P at Q. It gives freq/2.
Max. Freq of operation:
1/ (propagation delay+setup time) = 1/16ns = 62.5 MHz

54) For the Circuit Shown below, What is the Maximum Frequency of Operation?Are
there any hold time violations for FF2? If yes, how do you modify the circuit to avoid them?
The minumum time period = 3+2+(1+1+1) = 8ns Maximum Frequency = 1/8n= 125MHz.
And there is a hold time violation in the circuit,because of feedback, if you observe,
tcq2+AND gate delay is less than thold2,To avoid this we need to use even number of
inverters(buffers). Here we need to use 2 inverters each with a delay of 1ns. then the hold
time value exactly meets.

55)Design a D-latch using (a) using 2:1 Mux (b) from S-R Latch ?

56)How to implement a Master Slave flip flop using a 2 to 1 mux?

57)how many 2 input xor's are needed to inplement 16 input parity generator ?

It is always n-1 Where n is number of [Link] 16 input parity generator will require 15 two
input xor's .

58)Design a circuit for finding the 9's compliment of a BCD number using 4-bit binary
adder and some external logic gates?

9's compliment is nothing but subracting the given no from [Link] using a 4 bit binary adder
we can just subract the given binary no from 1001(i.e. 9).Here we can use the 2's compliment
method addition.
59) what is Difference between writeback and write through cache?

A caching method in which modifications to data in the cache aren't copied to the cache
source until absolutely necessary. Write-back caching is available on many microprocessors ,
including all Intel processors since the 80486. With these microprocessors, data
modifications to data stored in the L1 cache aren't copied to main memory until absolutely
necessary. In contrast, a write-through cache performs all write operations in parallel -- data
is written to main memory and the L1 cache simultaneously. Write-back caching yields
somewhat better performance than write-through caching because it reduces the number of
write operations to main memory. With this performance improvement comes a slight risk
that data may be lost if the system crashes.
A write-back cache is also called a copy-back cache.

60)Difference between Synchronous,Asynchronous & Isynchronous communication?

Sending data encoded into your signal requires that the sender and receiver are both using the
same enconding/decoding method, and know where to look in the signal to find data.
Asynchronous systems do not send separate information to indicate the encoding or clocking
information. The receiver must decide the clocking of the signal on it's own. This means that
the receiver must decide where to look in the signal stream to find ones and zeroes, and
decide for itself where each individual bit stops and starts. This information is not in the data
in the signal sent from transmitting unit.

Synchronous systems negotiate the connection at the data-link level before communication
begins. Basic synchronous systems will synchronize two clocks before transmission, and
reset their numeric counters for errors etc. More advanced systems may negotiate things like
error correction and compression.

Time-dependent. it refers to processes where data must be delivered within certain time
constraints. For example, Multimedia stream require an isochronous transport mechanism to
ensure that data is delivered as fast as it is displayed and to ensure that the audio is
synchronized with the video.

61) What are different ways Multiply & Divide?

Binary Division by Repeated Subtraction

Set quotient to zero
 Repeat while dividend is greater than or equal to divisor

 Subtract divisor from dividend

 Add 1 to quotient
End of repeat block
quotient is correct, dividend is remainder
STOP

Binary Division by Shift and Subtract

Basically the reverse of the mutliply by shift and add.
Set quotient to 0
Align leftmost digits in dividend and
divisor
Repeat

 If that portion of the dividend above the

divisor is greater than or equal to the
divisor
o Then subtract divisor from that
portion of the dividend and
o Concatentate 1 to the right hand
end of the quotient
o Else concatentate 0 to the right
hand end of the quotient
 Shift the divisor one place right
Until dividend is less than the divisor
quotient is correct, dividend is remainder
STOP

Binary Multiply - Repeated Shift and Add

Repeated shift and add - starting with a result
of 0, shift the second multiplicand to
correspond with each 1 in the first
multiplicand and add to the result. Shifting
each position left is equivalent to multiplying
by 2, just as in decimal representation a shift
left is equivalent to multiplying by 10.
Set result to 0
Repeat
  Shift 2nd multiplicand left until
rightmost digit is lined up with leftmost
1 in first multiplicand
 Add 2nd multiplicand in that position
to result
 Remove that 1 from 1st multiplicand
Until 1st multiplicand is zero
Result is correct
STOP

62)What is a SoC (System On Chip), ASIC, “full custom chip”, and an FPGA?
There are no precise definitions. Here is my sense of it all. First, 15 years ago, people were
unclear on exactly what VLSI meant. Was it 50000 gates? 100000 gates? was is just anything
bigger than LSI? My professor simply told me that; VLSI is a level of complexity and
integration in a chip that demands Electronic Design Automation tools in order to succeed. In
other words, big enough that manually drawing lots of little blue, red and green lines is too
much for a human to reasonably do. I think that, likewise, SoC is that level of integration
onto a chip that demands more expertise beyond traditional skills of electronics. In other
words, pulling off a SoC demands Hardware, Software, and Systems Engineering talent. So,
trivially, SoCs aggressively combine HW/SW on a single chip. Maybe more pragmatically,
SoC just means that ASIC and Software folks are learning a little bit more about each other’s
techniques and tools than they did before. Two other interpretations of SoC are 1) a chip that
integrates various IP (Intellectual Property) blocks on it and is thus highly centered with
issues like Reuse, and 2) a chip integrating multiple classes of electronic circuitry such as
Digital CMOS, mixed-signal digital and analog (e.g. sensors, modulators, A/Ds), DRAM
memory, high voltage power, etc.

ASIC stands for “Application Specific Integrated Circuit”. A chip designed for a specific
application. Usually, I think people associate ASICs with the Standard Cell design
methodology. Standard Cell design and the typical “ASIC flow” usually means that
designers are using Hardware Description Languages, Synthesis and a library of primitive
cells (e.g. libraries containing AND, NAND, OR, NOR, NOT, FLIP-FLOP, LATCH,
ADDER, BUFFER, PAD cells that are wired together (real libraries are not this simple, but
you get the idea..). Design usually is NOT done at a transistor level. There is a high reliance
on automated tools because the assumption is that the chip is being made for a SPECIFIC
APPLICATION where time is of the essence. But, the chip is manufactured from scratch in
that no pre-made circuitry is being programmed or reused. ASIC designer may, or may not,
even be aware of the locations of various pieces of circuitry on the chip since the tools do
much of the construction, placement and wiring of all the little pieces.

Full Custom, in contrast to ASIC (or Standard Cell), means that every geometric feature
going onto the chip being designed (think of those pretty chip pictures we have all seen) is
controlled, more or less, by the human design. Automated tools are certainly used to wire up
different parts of the circuit and maybe even manipulate (repeat, rotate, etc.) sections of the
chip. But, the human designer is actively engaged with the physical features of the circuitry.
Higher human crafting and less reliance on standard cells takes more time and implies higher
NRE costs, but lowers RE costs for standard parts like memories, processors, uarts, etc.

FPGAs, or Field Programmable Gate Arrays are completely designed chips that designers
load a programming pattern into to achieve a specific digital function. A bit pattern (almost
like a software program) is loaded into the already manufactured device which essentially
interconnects lots of available gates to meet the designers purposes. FPGAs are sometimes
thought of as a “Sea of Gates” where the designer specifies how they are connected. FPGA
designers often use many of the same tools that ASIC designers use, even though the FPGA
is inherently more flexible. All these things can be intermixed in hybrid sorts of ways. For
example, FPGAs are now available that have microprocessor embedded within them which
were designed in a full custom manner, all of which now demands “SoC” types of HW/SW
integration skills from the designer.

63)What is "Scan" ?
Scan Insertion and ATPG helps test ASICs (e.g. chips) during manufacture. If you know
what JTAG boundary scan is, then Scan is the same idea except that it is done inside the chip
instead of on the entire board. Scan tests for defects in the chip's circuitry after it is
manufactured (e.g. Scan does not help you test whether your Design functions as intended).
ASIC designers usually implement the scan themselves and occurs just after synthesis.
ATPG (Automated Test Pattern Generation) refers to the creation of "Test Vectors" that the
Scan circuitry enables to be introduced into the chip. Here's a brief summary:

· Scan Insertion is done by a tool and results in all (or most) of your design's
flip-flops to be replaced by special "Scan Flip-flops". Scan flops have additional
inputs/outputs that allow them to be configured into a "chain" (e.g. a big shift
register) when the chip is put into a test mode.

· The Scan flip-flops are connected up into a chain (perhaps multiple chains)

· The ATPG tool, which knows about the scan chain you've created, generates
a series of test vectors.

· The ATPG test vectors include both "Stimulus" and "Expected" bit patterns.
These bit vectors are shifted into the chip on the scan chains, and the chips
reaction to the stimulus is shifted back out again.

· The ATE (Automated Test Equipment) at the chip factory can put the chip
into the scan test mode, and apply the test vectors. If any vectors do not match,
then the chip is defective and it is thrown away.

· Scan/ATPG tools will strive to maximize the "coverage" of the ATPG

vectors. In other words, given some measure of the total number of nodes in the
chip that could be faulty (shorted, grounded, "stuck at 1", "stuck at 0"), what
percentage of them can be detected with the ATPG vectors? Scan is a good
technology and can achive high coverage in the 90% range.
 · Scan testing does not solve all test problems. Scan testing typically does not
test memories (no flip-flops!), needs a gate-level netlist to work with, and can
take a long time to run on the ATE.

· FPGA designers may be unfamiliar with scan since FPGA testing has
already been done by the FPGA manufacturer. ASIC designers do not have this
luxury and must handle all the manufacturing test details themselves.

· Check out the Synopsys WWW site for more info.

FPGA interview questions & answers.

What is FPGA ?

A field-programmable gate array is a semiconductor device containing programmable logic

components called "logic blocks", and programmable interconnects. Logic blocks can be
programmed to perform the function of basic logic gates such as AND, and XOR, or more
complex combinational functions such as decoders or mathematical functions. In most
FPGAs, the logic blocks also include memory elements, which may be simple flip-flops or
more complete blocks of memory. A hierarchy of programmable interconnects allows logic
blocks to be interconnected as needed by the system designer, somewhat like a one-chip
programmable breadboard. Logic blocks and interconnects can be programmed by the
customer or designer, after the FPGA is manufactured, to implement any logical function—
hence the name "field-programmable". FPGAs are usually slower than their application-
specific integrated circuit (ASIC) counterparts, cannot handle as complex a design, and draw
more power (for any given semiconductor process). But their advantages include a shorter
time to market, ability to re-program in the field to fix bugs, and lower non-recurring
engineering costs. Vendors can sell cheaper, less flexible versions of their FPGAs which
cannot be modified after the design is committed. The designs are developed on regular
FPGAs and then migrated into a fixed version that more resembles an ASIC.

What logic is inferred when there are multiple assign statements targeting the same wire?

It is illegal to specify multiple assign statements to the same wire in a synthesizable code that
will become an output port of the module. The synthesis tools give a syntax error that a net is
being driven by more than one source.
However, it is legal to drive a three-state wire by multiple assign statements.

What do conditional assignments get inferred into?

Conditionals in a continuous assignment are specified through the “?:” operator. Conditionals
get inferred into a multiplexor. For example, the following is the code for a simple
multiplexor
assign wire1 = (sel==1'b1) ? a : b;
What value is inferred when multiple procedural assignments made to the same reg variable
in an always block?

When there are multiple nonblocking assignments made to the same reg variable in a
sequential always block, then the last assignment is picked up for logic synthesis. For
example
always @ (posedge clk) begin
out <= in1^in2;
out <= in1 &in2;
out <= in1|in2;

In the example just shown, it is the OR logic that is the last assignment. Hence, the logic
synthesized was indeed the OR gate. Had the last assignment been the “&” operator, it would
have synthesized an AND gate.
1) What is minimum and maximum frequency of dcm in spartan-3 series fpga?

Spartan series dcm’s have a minimum frequency of 24 MHZ and a maximum of 248

2)Tell me some of constraints you used and their purpose during your design?

There are lot of constraints and will vary for tool to tool ,I am listing some of Xilinx
constraints
a) Translate on and Translate off: the Verilog code between Translate on and Translate off is
ignored for synthesis.
b) CLOCK_SIGNAL: is a synthesis constraint. In the case where a clock signal goes through
combinatorial logic before being connected to the clock input of a flip-flop, XST cannot
identify what input pin or internal net is the real clock signal. This constraint allows you to
define the clock net.
c) XOR_COLLAPSE: is synthesis constraint. It controls whether cascaded XORs should be
collapsed into a single XOR.
For more constraints detailed description refer to constraint guide.
3) Suppose for a piece of code equivalent gate count is 600 and for another code
equivalent gate count is 50,000 will the size of bitmap change?in other words will size of
bitmap change it gate count change?

The size of bitmap is irrespective of resource utilization, it is always the same,for Spartan
xc3s5000 it is 1.56MB and will never change.

4) What are different types of FPGA programming modes?what are you currently
using ?how to change from one to another?

Before powering on the FPGA, configuration data is stored externally in a PROM or some
other nonvolatile medium either on or off the board. After applying power, the configuration
data is written to the FPGA using any of five different modes: Master Parallel, Slave Parallel,
Master Serial, Slave Serial, and Boundary Scan (JTAG). The Master and Slave Parallel
modes
Mode selecting pins can be set to select the mode, refer data sheet for further details.

5) Tell me some of features of FPGA you are currently using?

I am taking example of xc3s5000 to answering the question .

Very low cost, high-performance logic solution for
high-volume, consumer-oriented applications
- Densities as high as 74,880 logic cells
- Up to 784 I/O pins
- 622 Mb/s data transfer rate per I/O
- 18 single-ended signal standards
- 6 differential I/O standards including LVDS, RSDS
- Termination by Digitally Controlled Impedance
- Signal swing ranging from 1.14V to 3.45V
- Double Data Rate (DDR) support
• Logic resources
- Abundant logic cells with shift register capability
- Wide multiplexers
- Fast look-ahead carry logic
- Dedicated 18 x 18 multipliers
- Up to 1,872 Kbits of total block RAM
- Up to 520 Kbits of total distributed RAM
• Digital Clock Manager (up to four DCMs)
- Clock skew elimination
• Eight global clock lines and abundant routing
6) What is gate count of your project?

Well mine was 3.2 million, I don’t know yours.!

7) Can you list out some of synthesizable and non synthesizable constructs?
not synthesizable->>>>
initial
ignored for synthesis.
delays
ignored for synthesis.
events
not supported.
real
Real data type not supported.
time
Time data type not supported.
force and release
Force and release of data types not supported.
fork join
Use nonblocking assignments to get same effect.
user defined primitives
Only gate level primitives are supported.

synthesizable constructs->>
assign,for loop,Gate Level Primitives,repeat with constant value...

8)Can you explain what struck at zero means?

These stuck-at problems will appear in ASIC. Some times, the nodes will permanently tie to
1 or 0 because of some fault. To avoid that, we need to provide testability in RTL. If it is
permanently 1 it is called stuck-at-1 If it is permanently 0 it is called stuck-at-0.

9) Can you draw general structure of fpga?

10) Difference between FPGA and CPLD?

FPGA:
a)SRAM based technology.
b)Segmented connection between elements.
c)Usually used for complex logic circuits.
d)Must be reprogrammed once the power is off.
e)Costly
CPLD:
a)Flash or EPROM based technology.
b)Continuous connection between elements.
c)Usually used for simpler or moderately complex logic circuits.
d)Need not be reprogrammed once the power is off.
e)Cheaper

11) What are dcm's?why they are used?

Digital clock manager (DCM) is a fully digital control system that

uses feedback to maintain clock signal characteristics with a
high degree of precision despite normal variations in operating
temperature and voltage.
That is clock output of DCM is stable over wide range of temperature and voltage , and also
skew associated with DCM is minimal and all phases of input clock can be obtained . The
output of DCM coming form global buffer can handle more load.

12) FPGA design flow?

Also,Please refer to presentation section synthesis ppt on this site.

13)what is slice,clb,lut?

I am taking example of xc3s500 to answer this question

The Configurable Logic Blocks (CLBs) constitute the main logic resource for implementing
synchronous as well as combinatorial circuits.
CLB are configurable logic blocks and can be configured to combo,ram or rom depending on
coding style
CLB consist of 4 slices and each slice consist of two 4-input LUT (look up table) F-LUT and
G-LUT.
14) Can a clb configured as ram?
YES.
The memory assignment is a clocked behavioral assignment, Reads from the memory are
asynchronous, And all the address lines are shared by the read and write statements.

15)What is purpose of a constraint file what is its extension?

The UCF file is an ASCII file specifying constraints on the logical design. You create this
file and enter your constraints in the file with a text editor. You can also use the Xilinx
Constraints Editor to create constraints within a UCF(extention) file. These constraints affect
how the logical design is implemented in the target device. You can use the file to override
constraints specified during design entry.

16) What is FPGA you are currently using and some of main reasons for choosing it?
18) How many global buffers are there in your current fpga,what is their significance?
There are 8 of them in xc3s5000
An external clock source enters the FPGA using a Global Clock Input Buffer (IBUFG),
which directly accesses the global clock network or an Input Buffer (IBUF). Clock signals
within the FPGA drive a global clock net using a Global Clock Multiplexer Buffer
(BUFGMUX). The global clock net connects directly to the CLKIN input.

19) What is frequency of operation and equivalent gate count of u r project?

20)Tell me some of timing constraints you have used?

21)Why is map-timing option used?

Timing-driven packing and placement is recommended to improve design performance,

timing, and packing for highly utilized designs.
17) Draw a rough diagram of how clock is routed through out FPGA?
22)What are different types of timing verifications?

Dynamic timing:
a. The design is simulated in full timing mode.
b. Not all possibilities tested as it is dependent on the input test vectors.
c. Simulations in full timing mode are slow and require a lot of memory.
d. Best method to check asynchronous interfaces or interfaces between different timing
domains.
Static timing:
a. The delays over all paths are added up.
b. All possibilities, including false paths, verified without the need for test vectors.
c. Much faster than simulations, hours as opposed to days.
d. Not good with asynchronous interfaces or interfaces between different timing domains.

23) Compare PLL & DLL ?

PLL:
PLLs have disadvantages that make their use in high-speed designs problematic, particularly
when both high performance and high reliability are required.
The PLL voltage-controlled oscillator (VCO) is the greatest source of problems. Variations
in temperature, supply voltage, and manufacturing process affect the stability and operating
performance of PLLs.

DLLs, however, are immune to these problems. A DLL in its simplest form inserts a variable
delay line between the external clock and the internal clock. The clock tree distributes the
clock to all registers and then back to the feedback pin of the DLL.
The control circuit of the DLL adjusts the delays so that the rising edges of the feedback
clock align with the input clock. Once the edges of the clocks are aligned, the DLL is locked,
and both the input buffer delay and the clock skew are reduced to zero.
Advantages:
· precision
· stability
· power management
· noise sensitivity
· jitter performance.

24) Given two ASICs. one has setup violation and the other has hold violation. how can
they be made to work together without modifying the design?

Slow the clock down on the one with setup violations..

And add redundant logic in the path where you have hold violations.

25)Suggest some ways to increase clock frequency?

· Check critical path and optimize it.

· Add more timing constraints (over constrain).
· pipeline the architecture to the max possible extent keeping in mind latency req's.
26)What is the purpose of DRC?

DRC is used to check whether the particular schematic and corresponding layout(especially
the mask sets involved) cater to a pre-defined rule set depending on the technology used to
design. They are parameters set aside by the concerned semiconductor manufacturer with
respect to how the masks should be placed , connected , routed keeping in mind that
variations in the fab process does not effect normal functionality. It usually denotes the
minimum allowable configuration.

27)What is LVs and why do we do that. What is the difference between LVS and DRC?

The layout must be drawn according to certain strict design rules. DRC helps in layout of the
designs by checking if the layout is abide by those rules.
After the layout is complete we extract the netlist. LVS compares the netlist extracted from
the layout with the schematic to ensure that the layout is an identical match to the cell
schematic.

28)What is DFT ?

DFT means design for testability. 'Design for Test or Testability' - a methodology that
ensures a design works properly after manufacturing, which later facilitates the failure
analysis and false product/piece detection
Other than the functional logic,you need to add some DFT logic in your [Link] will help
you in testing the chip for manufacturing defects after it come from fab.
Scan,MBIST,LBIST,IDDQ testing etc are all part of this. (this is a hot field and with lots of
opportunities)

29) There are two major FPGA companies: Xilinx and Altera. Xilinx tends to promote
its hard processor cores and Altera tends to promote its soft processor cores. What is
the difference between a hard processor core and a soft processor core?

A hard processor core is a pre-designed block that is embedded onto the device. In the Xilinx
Virtex II-Pro, some of the logic blocks have been removed, and the space that was used for
these logic blocks is used to implement a processor. The Altera Nios, on the other hand, is a
design that can be compiled to the normal FPGA logic.
30)What is the significance of contamination delay in sequential circuit timing?
Look at the figure below. tcd is the contamination delay.
Contamination delay tells you if you meet the hold time of a flip flop. To understand this
better please look at the sequential circuit below.

The contamination delay of the data path in a sequential circuit is critical for the hold time at
the flip flop where it is exiting, in this case R2.
mathematically, th(R2) <= tcd(R1) + tcd(CL2)
Contamination delay is also called tmin and Propagation delay is also called tmax in many
data sheets.

31)When are DFT and Formal verification used?

DFT:
· manufacturing defects like stuck at "0" or "1".
· test for set of rules followed during the initial design stage.

Formal verification:
· Verification of the operation of the design, i.e, to see if the design follows spec.
· gate netlist == RTL ?
· using mathematics and statistical analysis to check for equivalence.

32)What is Synthesis?

Synthesis is the stage in the design flow which is concerned with translating your Verilog
code into gates - and that's putting it very simply! First of all, the Verilog must be written in a
particular way for the synthesis tool that you are using. Of course, a synthesis tool doesn't
actually produce gates - it will output a netlist of the design that you have synthesised that
represents the chip which can be fabricated through an ASIC or FPGA vendor.

33)We need to sample an input or output something at different rates, but I need to
vary the rate? What's a clean way to do this?

Many, many problems have this sort of variable rate requirement, yet we are usually
constrained with a constant clock frequency. One trick is to implement a digital NCO
(Numerically Controlled Oscillator). An NCO is actually very simple and, while it is most
naturally understood as hardware, it also can be constructed in software. The NCO, quite
simply, is an accumulator where you keep adding a fixed value on every clock (e.g. at a
constant clock frequency). When the NCO "wraps", you sample your input or do your action.
By adjusting the value added to the accumulator each clock, you finely tune the AVERAGE
frequency of that wrap event. Now - you may have realized that the wrapping event may
have lots of jitter on it. True, but you may use the wrap to increment yet another counter
where each additional Divide-by-2 bit reduces this jitter. The DDS is a related technique. I
have two examples showing both an NCOs and a DDS in my File Archive. This is tricky to
grasp at first, but tremendously powerful once you have it in your bag of tricks. NCOs also
relate to digital PLLs, Timing Recovery, TDMA and other "variable rate" phenomena

VERILOG FAQ

1) Write a verilog code to swap contents of two registers with and without a temporary
register?
With temp reg ;
always @ (posedge clock)
begin
temp=b;
b=a;
a=temp;
end
Without temp reg;
always @ (posedge clock)
begin
a <= b;
b <= a;
end
2) Difference between blocking and non-blocking?(Verilog interview questions that is
most commonly asked)
The Verilog language has two forms of the procedural assignment statement: blocking and
non-blocking. The two are distinguished by the = and <= assignment operators. The blocking
assignment statement (= operator) acts much like in traditional programming languages. The
whole statement is done before control passes on to the next statement. The non-blocking
(<= operator) evaluates all the right-hand sides for the current time unit and assigns the left-
hand sides at the end of the time unit. For example, the following Verilog program
// testing blocking and non-blocking assignment
module blocking;
reg [0:7] A, B;
initial begin: init1
A = 3;
#1 A = A + 1; // blocking procedural assignment
B = A + 1;
$display("Blocking: A= %b B= %b", A, B ); A = 3;
#1 A <= A + 1; // non-blocking procedural assignment
B <= A + 1;
#1 $display("Non-blocking: A= %b B= %b", A, B );
end
endmodule
produces the following output:
Blocking: A= 00000100 B= 00000101
Non-blocking: A= 00000100 B= 00000100
The effect is for all the non-blocking assignments to use the old values of the variables at the
beginning of the current time unit and to assign the registers new values at the end of the
current time unit. This reflects how register transfers occur in some hardware systems.
blocking procedural assignment is used for combinational logic and non-blocking procedural
assignment for sequential

Tell me about verilog file I/O?

OPEN A FILE
integer file;
file = $fopenr("filename");
file = $fopenw("filename");
file = $fopena("filename");
The function $fopenr opens an existing file for reading. $fopenw opens a new file for
writing, and $fopena opens a new file for writing where any data will be appended to the end
of the file. The file name can be either a quoted string or a reg holding the file name. If the
file was successfully opened, it returns an integer containing the file number
(1..MAX_FILES) or NULL (0) if there was an error. Note that these functions are not the
same as the built-in system function $fopen which opens a file for writing by $fdisplay. The
files are opened in C with 'rb', 'wb', and 'ab' which allows reading and writing binary data on
the PC. The 'b' is ignored on Unix.

CLOSE A FILE
integer file, r;
r = $fcloser(file);
r = $fclosew(file);

The function $fcloser closes a file for input. $fclosew closes a file for output. It returns EOF
if there was an error, otherwise 0. Note that these are not the same as $fclose which closes
files for writing.

3) Difference between task and function?

Function:
A function is unable to enable a task however functions can enable other functions.
A function will carry out its required duty in zero simulation time. ( The program time will
not be incremented during the function routine)
Within a function, no event, delay or timing control statements are permitted
In the invocation of a function their must be at least one argument to be passed.
Functions will only return a single value and can not use either output or inout statements.
Tasks:
Tasks are capable of enabling a function as well as enabling other versions of a Task
Tasks also run with a zero simulation however they can if required be executed in a non zero
simulation time.
Tasks are allowed to contain any of these statements.
A task is allowed to use zero or more arguments which are of type output, input or inout.
A Task is unable to return a value but has the facility to pass multiple values via the output
and inout statements .
4) Difference between inter statement and intra statement delay?

//define register variables

reg a, b, c;
//intra assignment delays
initial
begin
a = 0; c = 0;
b = #5 a + c; //Take value of a and c at the time=0, evaluate
//a + c and then wait 5 time units to assign value
//to b.
end
//Equivalent method with temporary variables and regular delay control
initial
begin
a = 0; c = 0;
temp_ac = a + c;
#5 b = temp_ac; //Take value of a + c at the current time and
//store it in a temporary variable. Even though a and c
//might change between 0 and 5,
//the value assigned to b at time 5 is unaffected.
end

5) What is delta simulation time?

6) Difference between $monitor,$display & $strobe?
These commands have the same syntax, and display text on the screen during simulation.
They are much less convenient than waveform display tools like cwaves?. $display and
$strobe display once every time they are executed, whereas $monitor displays every time one
of its parameters changes.
The difference between $display and $strobe is that $strobe displays the parameters at the
very end of the current simulation time unit rather than exactly where it is executed. The
format string is like that in C/C++, and may contain format characters. Format characters
include %d (decimal), %h (hexadecimal), %b (binary), %c (character), %s (string) and %t
(time), %m (hierarchy level). %5d, %5b etc. would give exactly 5 spaces for the number
instead of the space needed. Append b, h, o to the task name to change default format to
binary, octal or hexadecimal.
Syntax:
$display (“format_string”, par_1, par_2, ... );
$strobe (“format_string”, par_1, par_2, ... );
$monitor (“format_string”, par_1, par_2, ... );

7) What is difference between Verilog full case and parallel case?

A "full" case statement is a case statement in which all possible case-expression binary
patterns can be matched to a case item or to a case default. If a case statement does not
include a case default and if it is possible to find a binary case expression that does not match
any of the defined case items, the case statement is not "full."
A "parallel" case statement is a case statement in which it is only possible to match a case
expression to one and only one case item. If it is possible to find a case expression that would
match more than one case item, the matching case items are called "overlapping" case items
and the case statement is not "parallel."

8) What is meant by inferring latches,how to avoid it?

Consider the following :

always @(s1 or s0 or i0 or i1 or i2 or i3)
case ({s1, s0})
2'd0 : out = i0;
2'd1 : out = i1;
2'd2 : out = i2;
endcase
in a case statement if all the possible combinations are not compared and default is also not
specified like in example above a latch will be inferred ,a latch is inferred because to
reproduce the previous value when unknown branch is specified.
For example in above case if {s1,s0}=3 , the previous stored value is reproduced for this
storing a latch is inferred.
The same may be observed in IF statement in case an ELSE IF is not specified.
To avoid inferring latches make sure that all the cases are mentioned if not default condition
is provided.
9) Tell me how blocking and non blocking statements get executed?
Execution of blocking assignments can be viewed as a one-step process:
1. Evaluate the RHS (right-hand side equation) and update the LHS (left-hand side
expression) of the blocking assignment without interruption from any other Verilog
statement. A blocking assignment "blocks" trailing assignments in the same always block
from occurring until after the current assignment has been completed
Execution of nonblocking assignments can be viewed as a two-step process:
1. Evaluate the RHS of nonblocking statements at the beginning of the time step. 2. Update
the LHS of nonblocking statements at the end of the time step.
10) Variable and signal which will be Updated first?
Signals
11) What is sensitivity list?
The sensitivity list indicates that when a change occurs to any one of elements in the list
change, begin…end statement inside that always block will get executed.
12) In a pure combinational circuit is it necessary to mention all the inputs in sensitivity
disk? if yes, why?
Yes in a pure combinational circuit is it necessary to mention all the inputs in sensitivity disk
other wise it will result in pre and post synthesis mismatch.
13) Tell me structure of Verilog code you follow?
A good template for your Verilog file is shown below.
// timescale directive tells the simulator the base units and precision of the simulation
`timescale 1 ns / 10 ps
module name (input and outputs);
// parameter declarations
parameter parameter_name = parameter value;
// Input output declarations
input in1;
input in2; // single bit inputs
output [msb:lsb] out; // a bus output
// internal signal register type declaration - register types (only assigned within always
statements). reg register variable 1;
reg [msb:lsb] register variable 2;
// internal signal. net type declaration - (only assigned outside always statements) wire net
variable 1;
// hierarchy - instantiating another module
reference name instance name (
.pin1 (net1),
.pin2 (net2),
.
.pinn (netn)
);
// synchronous procedures
always @ (posedge clock)
begin
.
end
// combinatinal procedures
always @ (signal1 or signal2 or signal3)
begin
.
end
assign net variable = combinational logic;
endmodule

14) Difference between Verilog and vhdl?

Compilation
VHDL. Multiple design-units (entity/architecture pairs), that reside in the same system file,
may be separately compiled if so desired. However, it is good design practice to keep each
design unit in it's own system file in which case separate compilation should not be an issue.

Verilog. The Verilog language is still rooted in it's native interpretative mode. Compilation is
a means of speeding up simulation, but has not changed the original nature of the language.
As a result care must be taken with both the compilation order of code written in a single file
and the compilation order of multiple files. Simulation results can change by simply
changing the order of compilation.

Data types
VHDL. A multitude of language or user defined data types can be used. This may mean
dedicated conversion functions are needed to convert objects from one type to another. The
choice of which data types to use should be considered wisely, especially enumerated
(abstract) data types. This will make models easier to write, clearer to read and avoid
unnecessary conversion functions that can clutter the code. VHDL may be preferred because
it allows a multitude of language or user defined data types to be used.
Verilog. Compared to VHDL, Verilog data types a re very simple, easy to use and very much
geared towards modeling hardware structure as opposed to abstract hardware modeling.
Unlike VHDL, all data types used in a Verilog model are defined by the Verilog language
and not by the user. There are net data types, for example wire, and a register data type called
reg. A model with a signal whose type is one of the net data types has a corresponding
electrical wire in the implied modeled circuit. Objects, that is signals, of type reg hold their
value over simulation delta cycles and should not be confused with the modeling of a
hardware register. Verilog may be preferred because of it's simplicity.

Design reusability
VHDL. Procedures and functions may be placed in a package so that they are avail able to
any design-unit that wishes to use them.

Verilog. There is no concept of packages in Verilog. Functions and procedures used within a
model must be defined in the module. To make functions and procedures generally
accessible from different module statements the functions and procedures must be placed in a
separate system file and included using the `include compiler directive.

15) What are different styles of Verilog coding I mean gate-level,continuous level and
others explain in detail?

16) Can you tell me some of system tasks and their purpose?

$display, $displayb, $displayh, $displayo, $write, $writeb, $writeh, $writeo.

The most useful of these is $[Link] can be used for displaying strings, expression or
values of variables.
Here are some examples of usage.
$display("Hello oni");
--- output: Hello oni
$display($time) // current simulation time.
--- output: 460
counter = 4'b10;
$display(" The count is %b", counter);
--- output: The count is 0010
$reset resets the simulation back to time 0; $stop halts the simulator and puts it in interactive
mode where the
user can enter commands; $finish exits the simulator back to the operating system

17) Can you list out some of enhancements in Verilog 2001?

In earlier version of Verilog ,we use 'or' to specify more than one element in sensitivity list .
In Verilog 2001, we can use comma as shown in the example below.
// Verilog 2k example for usage of comma
always @ (i1,i2,i3,i4)

Verilog 2001 allows us to use star in sensitive list instead of listing all the variables in RHS
of combo logics . This removes typo mistakes and thus avoids simulation and synthesis
mismatches,
Verilog 2001 allows port direction and data type in the port list of modules as shown in the
example below
module memory (
input r,
input wr,
input [7:0] data_in,
input [3:0] addr,
output [7:0] data_out
);
18)Write a Verilog code for synchronous and asynchronous reset?

Synchronous reset, synchronous means clock dependent so reset must not be present in
sensitivity disk eg:
always @ (posedge clk )

begin if (reset)
. . . end
Asynchronous means clock independent so reset must be present in sensitivity list.
Eg
Always @(posedge clock or posedge reset)
begin
if (reset)
. . . end
19) What is pli?why is it used?
Programming Language Interface (PLI) of Verilog HDL is a mechanism to interface Verilog
programs with programs written in C language. It also provides mechanism to access internal
databases of the simulator from the C program.
PLI is used for implementing system calls which would have been hard to do otherwise (or
impossible) using Verilog syntax. Or, in other words, you can take advantage of both the
paradigms - parallel and hardware related features of Verilog and sequential flow of C -
using PLI.
20) There is a triangle and on it there are 3 ants one on each corner and are free to
move along sides of triangle what is probability that they will collide?

Ants can move only along edges of triangle in either of direction, let’s say one is represented
by 1 and another by 0, since there are 3 sides eight combinations are possible, when all ants
are going in same direction they won’t collide that is 111 or 000 so probability of not
collision is 2/8=1/4 or collision probability is 6/8=3/4

What are the differences between blocking and nonblocking assignments?

While both blocking and nonblocking assignments are procedural assignments, they differ in
behaviour with respect to simulation and logic
synthesis as follows:
How can I model a bi-directional net with assignments influencing both source and
destination?

The assign statement constitutes a continuous assignment. The changes on the RHS of the
statement immediately reflect on the LHS net. However, any changes on the LHS don't get
reflected on the RHS. For example, in the following statement, changes to the rhs net will
update the lhs net, but not vice versa.
System Verilog has introduced a keyword alias, which can be used only on nets to have a
two-way assignment. For example, in the following code, any changes to the rhs is reflected
to the lh s , and vice versa.
wire rhs , lhs
assign lhs=rhs;
System Verilog has introduced a keyword alias, which can be used only on nets to have a
two-way assignment. For example, in the following code, any changes to the rhs is reflected
to the lh s , and vice versa.
module test ();
wire rhs,lhs;
alias lhs=rhs;
In the above example, any change to either side of the net gets reflected on the other side.
Are tasks and functions re-entrant, and how are they different from static task and function
calls?

In Verilog-95, tasks and functions were not re-entrant. From Verilog version 2001 onwards,
the tasks and functions are reentrant. The reentrant tasks have a keyword automatic between
the keyword task and the name of the task. The presence of the keyword automatic replicates
and allocates the variables within a task dynamically for each task entry during concurrent
task calls, i.e., the values don’t get overwritten for each task call. Without the keyword, the
variables are allocated statically, which means these variables are shared across different task
calls, and can hence get overwritten by each task call.

How can I override variables in an automatic task?

By default, all variables in a module are static, i.e., these variables will be replicated for all
instances of a module. However, in the case of task and function, either the task/function
itself or the variables within them can be defined as static or automatic. The following
explains the inferences through different combinations of the task/function and/or its
variables, declared either as static or automatic:

No automatic definition of task/function or its variables This is the Verilog-1995 format,

wherein the task/function and its variables were implicitly static. The variables are allocated
only once. Without the mention of the automatic keyword, multiple calls to task/function will
override their variables.

static task/function definition

System Verilog introduced the keyword static. When a task/function is explicitly defined as
static, then its variables are allocated only once, and can be overridden. This scenario is
exactly the same scenario as before.

automatic task/function definition

From Verilog-2001 onwards, and included within SystemVerilog, when the task/function is
declared as automatic, its variables are also implicitly automatic. Hence, during multiple calls
of the task/function, the variables are allocated each time and replicated without any
overwrites.

static task/function and automatic variables

SystemVerilog also allows the use of automatic variables in a static task/function. Those
without any changes to automatic variables will remain implicitly static. This will be useful
in scenarios wherein the implicit static variables need to be initialised before the task call,
and the automatic variables can be allocated each time.

automatic task/function and static variables

SystemVerilog also allows the use of static variables in an automatic task/function. Those
without any changes to static variables will remain implicitly automatic. This will be useful
in scenarios wherein the static variables need to be updated for each call, whereas the rest can
be allocated each time.
What are the rules governing usage of a Verilog function?

The following rules govern the usage of a Verilog function construct:

A function cannot advance simulation-time, using constructs like #, @. etc.
A function shall not have nonblocking assignments.
A function without a range defaults to a one bit reg for the return value.
It is illegal to declare another object with the same name as the function in the scope where
the function is declared.
How do I prevent selected parameters of a module from being overridden during
instantiation?

If a particular parameter within a module should be prevented from being overridden, then it
should be declared using the localparam construct, rather than the parameter construct. The
localparam construct has been introduced from Verilog-2001. Note that a localparam
variable is fully identical to being defined as a parameter, too. In the following example, the
localparam construct is used to specify num_bits, and hence trying to override it directly
gives an error message.

Note, however, that, since the width and depth are specified using the parameter construct,
they can be overridden during instantiation or using defparam, and hence will indirectly
override the num_bits values. In general, localparam constructs are useful in defining new
and localized identifiers whose values are derived from regular parameters.
What are the pros and cons of specifying the parameters using the defparam construct vs.
specifying during instantiation?

The advantages of specifying parameters during instantiation method are:

All the values to all the parameters don’t need to be specified. Only those parameters that are
assigned the new values need to be specified. The unspecified parameters will retain their
default values specified within its module definition.
The order of specifying the parameter is not relevant anymore, since the parameters are
directly specified and linked by their name.

The disadvantage of specifying parameter during instantiation are:

This has a lower precedence when compared to assigning using defparam.

The advantages of specifying parameter assignments using defparam are:

This method always has precedence over specifying parameters during instantiation.

All the parameter value override assignments can be grouped inside one module and together
in one place, typically in the top-level testbench itself.

When multiple defparams for a single parameter are specified, the parameter takes the value
of the last defparam statement encountered in the source if, and only if, the multiple
defparam’s are in the same file. If there are defparam’s in different files that override the
same parameter, the final value of the parameter is indeterminate.

The disadvantages of specifying parameter assignments using defparam are:

The parameter is typically specified by the scope of the hierarchies underneath which it
exists. If a particular module gets ungrouped in its hierarchy, [sometimes necessary during
synthesis], then the scope to specify the parameter is lost, and is unspecified. B

For example, if a module is instantiated in a simulation testbench, and its internal parameters
are then overridden using hierarchical defparam constructs (For example, defparam
U1.U_fifo.width = 32;). Later, when this module is synthesized, the internal hierarchy within
U1 may no longer exist in the gate-level netlist, depending upon the synthesis strategy
chosen. Therefore post-synthesis simulation will fail on the hierarchical defparam override.

Can there be full or partial no-connects to a multi-bit port of a module during its
instantiation?

No. There cannot be full or partial no-connects to a multi-bit port of a module during
instantiation
What happens to the logic after synthesis, that is driving an unconnected output port that is
left open (, that is, noconnect) during its module instantiation?

An unconnected output port in simulation will drive a value, but this value does not
propagate to any other logic. In synthesis, the cone of any combinatorial logic that drives the
unconnected output will get optimized away during boundary optimisation, that is,
optimization by synthesis tools across hierarchical boundaries.

How is the connectivity established in Verilog when connecting wires of different widths?

When connecting wires or ports of different widths, the connections are right-justified, that
is, the rightmost bit on the RHS gets connected to the rightmost bit of the LHS and so on,
until the MSB of either of the net is reached.
Can I use a Verilog function to define the width of a multi-bit port, wire, or reg type?

The width elements of ports, wire or reg declarations require a constant in both MSB and
LSB. Before Verilog 2001, it is a syntax error to specify a function call to evaluate the value
of these widths. For example, the following code is erroneous before Verilog 2001 version.

reg [ port1(val1:vla2) : port2 (val3:val4)] reg1;

In the above example, get_high and get_low are both function calls of evaluating a constant
result for MSB and LSB respectively. However, Verilog-2001 allows the use of a function
call to evaluate the MSB or LSB of a width declaration
What is the implication of a combinatorial feedback loops in design testability?

The presence of feedback loops should be avoided at any stage of the design, by periodically
checking for it, using the lint or synthesis tools. The presence of the feedback loop causes
races and hazards in the design, and 104 RTL Design
leads to unpredictable logic behavior. Since the loops are delay-dependent, they cannot be
tested with any ATPG algorithm. Hence, combinatorial loops should be avoided in the logic.
What are the various methods to contain power during RTL coding?

Any switching activity in a CMOS circuit creates a momentary current flow from VDD to
GND during logic transition, when both N and P type transistors are ON, and, hence,
increases power consumption.
The most common storage element in the designs being the synchronous FF, its output can
change whenever its data input toggles, and the clock triggers. Hence, if these two elements
can be asserted in a controlled fashion, so that the data is presented to the D input of the FF
only when required, and the clock is also triggered only when required, then it will reduce
the switching activity, and, automatically the power.

The following bullets summarize a few mechanisms to reduce the power consumption:
Reduce switching of the data input to the Flip-Flops.
Reduce the clock switching of the Flip-Flops.
Have area reduction techniques within the chip, since the number of gates/Flip-Flops that
toggle can be reduced.

How do I model Analog and Mixed-Signal blocks in Verilog?

First, this is a big [Link] and Mixed-Signal designers use tools like Spice to fully
characterize and model their [Link] only involvement with Mixed-Signal blocks has
been to utilize behavioral models of things like PLLs, A/Ds, D/As within a larger [Link]
are some specific Verilog tricks to this which is what this FAQ is about (I do not wish to
trivialize true Mixed-Signal methodology, but us chip-level folks need to know this trick).

A mixed-signal behavioral model might model the digital and analog input/output behavior
of, for example, a D/A (Digital to Analog Converter).So, digital input in and analog voltage
[Link] to model might be the timing (say, the D/A utilizes an internal Success
Approximation algorithm), output range based on power supply voltages, voltage biases,
etc.A behavioral model may not have any knowledge of the physical layout and therefore
may not offer any fidelity whatsoever in terms of noise, interface, cross-talk, etc.A
model might be parameterized given a specific characterization for a [Link] very careful
about the assumptions and limitations of the model!

Issue #1; how do we model analog voltages in [Link]: use the Verilog real data
type, declare “analog wires” as wire[63:0] in order to use a 64-bit floating-type
represenation, and use the built-in PLI functions:

$rtoi converts reals to integers w/truncation e.g. 123.45 -> 123

$itor converts integers to reals e.g. 123 -> 123.0

$realtobits converts reals to 64-bit vector

$bitstoreal converts bit pattern to real

That was a [Link] is a trick to be used in vanilla [Link] 64-bit wire is simply a ways to
actually interface to the ports of the mixed-signal [Link] other words, our example D/A
module may have an output called AOUT which is a [Link] does not allow us to
declare an output port of type [Link], instead declare AOUT like this:

module dtoa (clk, reset..... aout.....);

wire [63:0]aout;// Analog output

We use 64 bits because we can use floating-point numbers to represent out voltage output
(e.g. 1.22x10-3 for 1.22 millivolts).The floating-point value is relevant only to Verilog and
your workstation and processor, and the IEEE floating-point format has NOTHING to do
with the D/A [Link] the disconnect in terms of the netlist [Link] physical
“netlist” that you might see in GDS may have a single metal interconnect that is AOUT, and
obviously NOT 64 metal [Link], this is a [Link] 64-bit bus is only for [Link]
may have to do some quick netlist substitutions when you hand off a netlist.

In Verilog, the real data type is basically a floating-point number (e.g. like double in C).If
you want to model an analog value either within the mixed-signal behavorial model, or
externally in the system testbench (e.g. the sensor or actuator), use the real data [Link] can
convert back and forth between real and your wire [63:0] using the PLI functions listed
above.A trivial D/A model could simply take the digital input value, convert it to real, scale
it according to some #defines, and output the value on AOUT as the 64-bit “psuedo-analog”
[Link] testbench can then do the reverse and print out the value, or [Link]
sophisticated models can model the Successive Approximation algorithm, employ look-ups,
equations, etc. etc.

That’s [Link] you are getting a mixed-signal block from a vendor, then you may also receive (or
you should ask for) the behavioral Verilog models for the IP.
How do I synthesize Verilog into gates with Synopsys?

The answer can, of course, occupy several lifetimes to completely answer.. BUT.. a straight-
forward Verilog module can be very easily synthesized using Design Compiler (e.g.
dc_shell). Most ASIC projects will create very elaborate synthesis scripts, CSH scripts,
Makefiles, etc. This is all important in order automate the process and generalize the
synthesis methodology for an ASIC project or an organization. BUT don't let this stop you
from creating your own simple dc_shell experiments!

Let's say you create a Verilog module named foo.v that has a single clock input named 'clk'.
You want to synthesize it so that you know it is synthesizable, know how big it is, how fast it
is, etc. etc. Try this:

target_library = { [Link] } <--- This part you need to get from your
vendor...

read -format verilog foo.v

create_clock -name clk -period 37.0

 set_clock_skew -uncertainty 0.4 clk

set_input_delay 1.0 -clock clk all_inputs() - clk - reset

set_output_delay 1.0 -clock clk all_outputs()

compile

report_area

report_timing

write -format db -hierarchy -output [Link]

write -format verilog -hierarchy -output [Link]

quit

You can enter all this in interactively, or put it into a file called 'synth_foo.scr' and then enter:

dc_shell -f synth_foo.scr

You can spend your life learning more and more Synopsys and synthesis-related commands
and techniques, but don't be afraid to begin using these simple commands.

How can I pass parameters to my simulation?

A testbench and simulation will likely need many different parameters and settings for
different sorts of tests and conditions. It is definitely a good idea to concentrate on a single
testbench file that is parameterized, rather than create a dozen seperate, yet nearly identical,
testbenches. Here are 3 common techniques:

Use a define. This is almost exactly the same approach as the #define and -D
compiler arg that C programs use. In your Verilog code, use a `define to define the
variable condition and then use the Verilog preprocessor directives like `ifdef. Use the
'+define+' Verilog command line option. For example:

... to run the simulation

verilog testbench.v cpu.v +define+USEWCSDF

... in your code ...

`ifdef USEWCSDF

initial $sdf_annotate ([Link], "[Link]");

`endif
The +define+ can also be filled in from your Makefile invocation, which in turn, can be
finally

filled in the your UNIX promp command line.

Defines are a blunt weapon because they are very global and you can only do so much with

them since they are a pre-processor trick. Consider the next approach before resorting to

defines.

Use parameters and parameter definition modules. Parameters are not

preprocessor definitions and they have scope (e.g. parameters are associated with
specific modules). Parameters are therefore more clean, and if you are in the habit of
using a lot of defines; consider switching to parameters. As an example, lets say we
have a test (e.g. test12) which needs many parameters to have particular settings. In
your code, you might have this sort of stuff:

module testbench_uart1 (....)

parameter BAUDRATE = 9600;

if (BAUDRATE > 9600) begin

... E.g. use the parameter in your code like you might any general variable

... BAUDRATE is completely local to this module and this instance. You might

... have the same parameters in 3 other UART instances and they'd all be different

... values...

Now, your test12 has all kinds of settings required for it. Let's define a special module

called testparams which specifies all these settings. It will itself be a module
instantiated

under the testbench:

module testparams;

defparam [Link] = 19200;

defparam [Link] = 9600;

defparam [Link] = 9600;

defparam [Link] CLOCKRATE = 200; // Period in ns.

... etc ...

 endmodule

The above module always has the same module name, but you would have many different

filenames; one for each test. So, the above would be kept in test12_params.v. Your

Makefile includes the appropriate params file given the desired make target. (BTW: You

may run across this sort of technique by ASIC vendors who might have a module containing

parameters for a memory model, or you might see this used to collect together a large

number of system calls that turn off timing or warnings on particular troublesome nets, etc.

etc.)

Use memory blocks. Not as common a technique, but something to consider.

Since Verilog has a very convenient syntax for declaring and loading memories, you
can store your input data in a hex file and use $readmemh to read all the data in at
once.

In your testbench:

module testbench;

reg [31:0] control[0:1023];

initial $readmemh ("[Link]", control);

endmodule

You could vary the filename using the previous techniques. The [Link] file is just a file

of hex values for the parameters. Luckily, $readmemh allows embedded comments, so you

can keep the file very readable:

A000 // Starting address to put boot code in

10 // Activate all ten input pulse sources

... etc...
Obviously, you are limitied to actual hex values with this approach. Note, of course, that

you are free to mix and match all of these techniques!

1) Tell something about why we do gate level simulations?

a. Since scan and other test structures are added during and after synthesis, they are not
checked by the rtl simulations and therefore need to be verified by gate level simulation.
b. Static timing analysis tools do not check asynchronous interfaces, so gate level simulation
is required to look at the timing of these interfaces.
c. Careless wildcards in the static timing constraints set false path or mutlicycle path
constraints where they don't belong.
d. Design changes, typos, or misunderstanding of the design can lead to incorrect false paths
or multicycle paths in the static timing constraints.
e. Using create_clock instead of create_generated_clock leads to incorrect static
timing between clock domains.
f. Gate level simulation can be used to collect switching factor data for power estimation.
g. X's in RTL simulation can be optimistic or pessimistic. The best way to verify that the
design does not have any unintended dependence on initial conditions is to run gate level
simulation.
f. It's a nice "warm fuzzy" that the design has been implemented correctly.

2) Say if I perform Formal Verification say Logical Equivalence across Gatelevel

netlists(Synthesis and post routed netlist). Do you still see a reason behind GLS.?

If we have verified the Synthesized netlist functionality is correct when compared to RTL
and when we compare the Synthesized netlist versus Post route netlist logical Equivalence
then I think we may not require GLS after P & R. But how do we ensure on Timing . To my
knowledge Formal Verification Logical Equivalence Check does not perform Timing checks
and dont ensure that the design will work on the operating frequency , so still I would go for
GLS after post route database.

3)An AND gate and OR gate are given inputs X & 1 , what is expected output?

AND Gate output will be X

OR Gate output will be 1.

4) What is difference between NMOS & RNMOS?

RNMOS is resistive nmos that is in simulation strength will decrease by one unit , please
refer to below Diagram.
4) Tell something about modeling delays in verilog?

Verilog can model delay types within its specification for gates and buffers. Parameters that
can be modelled are T_rise, T_fall and T_turnoff. To add further detail, each of the three
values can have minimum, typical and maximum values

T_rise, t_fall and t_off

Delay modelling syntax follows a specific discipline;
gate_type #(t_rise, t_fall, t_off) gate_name (paramters);
When specifiying the delays it is not necessary to have all of the delay values specified.
However, certain rules are followed.

and #(3) gate1 (out1, in1, in2);

When only 1 delay is specified, the value is used to represent all of the delay types, i.e. in
this example, t_rise = t_fall = t_off = 3.

or #(2,3) gate2 (out2, in3, in4);

When two delays are specified, the first value represents the rise time, the second value
represents the fall time. Turn off time is presumed to be 0.
buf #(1,2,3) gate3 (out3, enable, in5);
When three delays are specified, the first value represents t_rise, the second value represents
t_fall and the last value the turn off time.

Min, typ and max values

The general syntax for min, typ and max delay modelling is;
gate_type #(t_rise_min:t_ris_typ:t_rise_max, t_fall_min:t_fall_typ:t_fall_max,
t_off_min:t_off_typ:t_off_max) gate_name (paramteters);

Similar rules apply for th especifying order as above. If only one t_rise value is specified
then this value is applied to min, typ and max. If specifying more than one number, then all 3
MUST be scpecified. It is incorrect to specify two values as the compiler does not know
which of the parameters the value represents.

An example of specifying two delays;

and #(1:2:3, 4:5:6) gate1 (out1, in1, in2);
This shows all values necessary for rise and fall times and gives values for min, typ and max
for both delay types.

Another acceptable alternative would be;

or #(6:3:9, 5) gate2 (out2, in3, in4);
Here, 5 represents min, typ and max for the fall time.

N.B. T_off is only applicable to tri-state logic devices, it does not apply to primitive logic
gates because they cannot be turned off.

5) With a specify block how to defining pin-to-pin delays for the module ?

module A( q, a, b, c, d )

input a, b, c, d;

output q;

wire e, f;

// specify block containing delay statements

specify

( a => q ) = 6; // delay from a to q

( b => q ) = 7; // delay from b to q

( c => q ) = 7; // delay form c to q

( d => q ) = 6; // delay from d to q

 endspecify

// module definition

or o1( e, a, b );

or o2( f, c, d );

exor ex1( q, e, f );

endmodule

module A( q, a, b, c, d )
input a, b, c, d;
output q;
wire e, f;
// specify block containing full connection statements
specify
( a, d *> q ) = 6; // delay from a and d to q
( b, c *> q ) = 7; // delay from b and c to q
endspecify
// module definition
or o1( e, a, b );
or o2( f, c, d );
exor ex1( q, e, f );
endmodule

6) What are conditional path delays?

Conditional path delays, sometimes called state dependent path delays, are used to model
delays which are dependent on the values of the signals in the circuit. This type of delay is
expressed with an if conditional statement. The operands can be scalar or vector module
input or inout ports, locally defined registers or nets, compile time constants (constant
numbers or specify block parameters), or any bit-select or part-select of these. The
conditional statement can contain any bitwise, logical, concatenation, conditional, or
reduction operator. The else construct cannot be used.

//Conditional path delays

Module A( q, a, b, c, d );
output q;
input a, b, c, d;
wire e, f;
// specify block with conditional timing statements
specify
// different timing set by level of input a
if (a) ( a => q ) = 12;
if ~(a) ( a => q ) = 14;
// delay conditional on b and c
// if b & c is true then delay is 7 else delay is 9
 if ( b & c ) ( b => q ) = 7;
if ( ~( b & c )) ( b => q ) = 9;
// using the concatenation operator and full connections
if ( {c, d} = 2'b10 ) ( c, d *> q ) = 15;
if ( {c, d} != 2'b10 ) ( c, d *> q ) = 12;
endspecify
or o1( e, a, b );
or o2( f, c, d );
exor ex1( q, e, f );
endmodule

6) Tell something about Rise, fall, and turn-off delays?

Timing delays between pins can be expressed in greater detail by specifying rise, fall, and
turn-off delay values. One, two, three, six, or twelve delay values can be specified for any
path. The order in which the delay values are specified must be strictly followed.

// One delay used for all transitions

specparam delay = 15;
( a => q ) = delay;
// Two delays gives rise and fall times
specparam rise = 10, fall = 11;
( a => q ) = ( rise, fall );
// Three delays gives rise, fall and turn-off
// rise is used for 0-1, and z-1, fall for 1-0, and z-0, and turn-off for 0-z, and 1-z.
specparam rise = 10, fall = 11, toff = 8;
( a => q ) = ( rise, fall, toff );
// Six delays specifies transitions 0-1, 1-0, 0-z, z-1, 1-z, z-0
// strictly in that order
specparam t01 = 8, t10 = 9, t0z = 10, tz1 = 11, t1z = 12, tz0 = 13;
( a => q ) = ( t01, t10, t0z, tz1, t1z, tz0 );
// Twelve delays specifies transitions:
// 0-1, 1-0, 0-z, z-1, 1-z, z-0, 0-x, x-1, 1-x, x-0, x-z, z-x
// again strictly in that order
specparam t01 = 8, t10 = 9, t0z = 10, tz1 = 11, t1z = 12, tz0 = 13;
specparam t0x = 11, tx1 = 14, t1x = 12, tx0 = 10, txz = 8, tzx = 9;
( a => q ) = ( t01, t10, t0z, tz1, t1z, tz0, t0x, tx1, t1x, tx0, txz, tzx );

7)Tell me about In verilog delay modeling?

Distributed Delay

Distributed delay is delay assigned to each gate in a module. An example circuit is shown
below.
 Figure 1: Distributed delay

As can be seen from Figure 1, each of the or-gates in the circuit above has a delay assigned
to it:

 gate 1 has a delay of 4

 gate 2 has a delay of 6

 gate 3 has a delay of 3

When the input of any gate change, the output of the gate changes after the delay value
specified.

The gate function and delay, for example for gate 1, can be described in the following
manner:

or #4 a1 (e, a, b);

A delay of 4 is assigned to the or-gate. This means that the output of the gate, e, is delayed
by 4 from the inputs a and b.

The module explaining Figure 1 can be of two forms:

1)
Module or_circ (out, a, b, c, d);
output out;
input a, b, c, d;
wire e, f;
//Delay distributed to each gate
or #4 a1 (e, a, b);
or #6 a2 (f, c, d);
or #3 a3 (out, e, f);
 endmodule
2)
Module or_circ (out, a, b, c, d);
output out;
input a, b, c, d;
wire e, f;
//Delay distributed to each expression
assign #4 e = a & b;
assign #6 e = c & d;
assign #3 e = e & f;
endmodule

Version 1 models the circuit by assigning delay values to individual gates, while version 2
use delay values in individual assign statements. (An assign statement allows us to describe a
combinational logic function without regard to its actual structural implementation. This
means that the assign statement does not contain any modules with port connections.)

The above or_circ modules results in delays of (4+3) = 7 and (6+3) = 9 for the 4 connections
part from the input to the output of the circuit.

Lumped Delay

Lumped delay is delay assigned as a single delay in each module, mostly to the output gate
of the module. The cumulative delay of all paths is lumped at one location. The figure below
is an example of lumped delay. This figure is similar as the figure of the distributed delay,
but with the sum delay of the longest path assigned to the output gate: (delay of gate 2 +
delay of gate 3) = 9.

Figure 2: Lumped delay

As can be seen from Figure 2, gate 3 has got a delay of 9. When the input of this gate
changes, the output of the gate changes after the delay value specified.
The program corresponding to Figure 2, is very similar to the one for distributed delay. The
difference is that only or - gate 3 has got a delay assigned to it:

1)
Module or_circ (out, a, b, c, d);
output out;
input a, b, c, d;
wire e, f;
or a1 (e, a, b);
or a2 (f, c, d);
or #9 a3 (out, e, f); //delay only on the output gate
endmodule

This model can be used if delay between different inputs is not required.

Pin - to Pin Delay

Pin - to - Pin delay, also called path delay, is delay assigned to paths from each input to each
output. An example circuit is shown below.

path a - e - out, delay = 7

path b - e - out, delay = 7
path c - f - out, delay = 9
path d - f - out, delay = 9
Figure 3: Pin - to Pin delay

The total delay from each input to each output is given. The same example circuit as for the
distributed and lumped delay model is used. This means that the sum delay from each input
to each output is the same.

The module for the above circuit is shown beneath:

Module or_circ (out, a, b, c, d);

output out;
 input a, b, c, d;
wire e, f;
//Blocks specified with path delay
specify
(a => out) = 7;
(b => out) = 7;
(c => out) = 9;
(d => out) = 9;
endspecify
//gate calculations
or a1(e, a, b);
or a2(f, c, d);
or a3(out, e, f);
endmodule

Path delays of a module are specified incide a specify block, as seen from the example
above. An example of delay from the input, a, to the output, out, is written as (a => out) =
delay, where delay sets the delay between the two ports. The gate calculations are done after
the path delays are defined.

For larger circuits, the pin - to - pin delay can be easier to model than distributed delay. This
is because the designer writing delay models, needs to know only the input / output pins of
the module, rather than the internals of the module. The path delays for digital circuits can be
found through different simulation programs, for instance SPICE. Pin - to - Pin delays for
standard parts can be found from data books. By using the path delay model, the program
speed will increase.

8) Tell something about delay modeling timing checks?

Delay Modeling: Timing Checks.

Keywords: $setup, $hold, $width

This section, the final part of the delay modeling chapter, discusses some of the various
system tasks that exist for the purposes of timing checks. Verilog contains many timing-
check system tasks, but only the three most common tasks are discussed
here: $setup, $hold and $width. Timing checks are used to verify that timing constraints are
upheld, and are especially important in the simulation of high-speed sequential circuits such
as microprocessors. All timing checks must be contained within specify blocks as shown in
the example below.

The $setup and $hold tasks are used to monitor the setup and hold constraints during the
simulation of a sequential circuit element. In the example, the setup time is the minimum
allowed time between a change in the input d and a positive clock edge. Similarly, the hold
time is the minimum allowed time between a positive clock edge and a change in the input d.

The $width task is used to check the minimum width of a positive or negative-going pulse.
In the example, this is the time between a negative transition and the transition back to 1.
Syntax:

NB: data_change, reference and reference1 must be declared wires.

$setup(data_change, reference, time_limit);

data_change: signal that is checked against the reference

reference: signal used as reference

time_limit: minimum time required between the two events.

Violation if: Treference - Tdata_change < time_limit.

$hold(reference, data_change, time_limit);

reference: signal used as reference

data_change: signal that is checked against the reference

time_limit: minimum time required between the two events.

Violation if: Tdata_change - Treference < time_limit

$width(reference1, time_limit);

reference1: first transition of signal

time_limit: minimum time required between transition1 and transition2.

Violation if: Treference2 - Treference1 < time_limit

Example:
module d_type(q, clk, d);
output q;
input clk, d;

reg q;

always @(posedge clk)

q = d;

endmodule // d_type

module stimulus;

reg clk, d;
wire q, clk2, d2;

d_type dt_test(q, clk, d);

assign d2=d;
assign clk2=clk;

initial
begin
$display ("\t\t clock d q");
$display ($time," %b %b %b", clk, d, q);
clk=0;
d=1;
#7 d=0;
#7 d=1; // causes setup violation
#3 d=0;
#5 d=1; // causes hold violation
#2 d=0;
#1 d=1; // causes width violation
end // initial begin

initial
#26 $finish;

always
#3 clk = ~clk;

always
#1 $display ($time," %b %b %b", clk, d, q);

specify
$setup(d2, posedge clk2, 2);
$hold(posedge clk2, d2, 2);
 $width(negedge d2, 2);
endspecify
endmodule // stimulus

Output:

clock d q
0 x xx
1 0 1x
2 0 1x
3 1 1x
4 1 11
5 1 11
6 0 11
7 0 01
8 0 01
9 1 01
10 1 0 0
11 1 0 0
12 0 0 0
13 0 0 0
14 0 1 0
15 1 1 0

"timechecks.v", 46: Timing violation in stimulus

$setup( d2:14, posedge clk2:15, 2 );

16 1 11
17 1 01
18 0 01
19 0 01
20 0 01
21 1 01
22 1 10

"timechecks.v", 47: Timing violation in stimulus

$hold( posedge clk2:21, d2:22, 2 );

23 1 1 0
24 0 0 0
25 0 1 0

"timechecks.v", 48: Timing violation in stimulus

$width( negedge d2:24, : 25, 2 );
9) Draw a 2:1 mux using switches and verilog code for it?

1-bit 2-1 Multiplexer

This circuit assigns the output out to either inputs in1 or in2 depending on the low or high
values of ctrl respectively.

// Switch-level description of a 1-bit 2-1 multiplexer

// ctrl=0, out=in1; ctrl=1, out=in2

module mux21_sw (out, ctrl, in1, in2);

output out; // mux output

input ctrl, in1, in2; // mux inputs
wire w; // internal wire

inv_sw I1 (w, ctrl); // instantiate inverter module

cmos C1 (out, in1, w, ctrl); // instantiate cmos switches

cmos C2 (out, in2, ctrl, w);

endmodule

An inverter is required in the multiplexer circuit, which is instantiated from the previously
defined module.

Two transmission gates, of instance names C1 and C2, are implemented with
the cmos statement, in the format cmos
[instancename]([output],[input],[nmosgate],[pmosgate]). Again, the instance name is
optional.
10)What are the synthesizable gate level constructs?

The above table gives all the gate level constructs of only the constructs in first two columns
are synthesizable.

CMOS INTERVIEW QUESTIONS.

1) What is latch up?

Latch-up pertains to a failure mechanism wherein a parasitic thyristor (such as a parasitic
silicon controlled rectifier, or SCR) is inadvertently created within a circuit, causing a high
amount of current to continuously flow through it once it is accidentally triggered or turned
on. Depending on the circuits involved, the amount of current flow produced by this
mechanism can be large enough to result in permanent destruction of the device due to
electrical overstress (EOS) .

2)Why is NAND gate preferred over NOR gate for fabrication?

NAND is a better gate for design than NOR because at the transistor level the mobility of
electrons is normally three times that of holes compared to NOR and thus the NAND is a
faster gate.
Additionally, the gate-leakage in NAND structures is much lower. If you consider t_phl and
t_plh delays you will find that it is more symmetric in case of NAND ( the delay profile), but
for NOR, one delay is much higher than the other(obviously t_plh is higher since the higher
resistance p mos's are in series connection which again increases the resistance).

3)What is Noise Margin? Explain the procedure to determine Noise Margin

The minimum amount of noise that can be allowed on the input stage for which the output
will not be effected.

4)Explain sizing of the inverter?

In order to drive the desired load capacitance we have to increase the size (width) of the
inverters to get an optimized performance.
5) How do you size NMOS and PMOS transistors to increase the threshold voltage?

6) What is Noise Margin? Explain the procedure to determine Noise Margin?

The minimum amount of noise that can be allowed on the input stage for which the output
will not be effected.

7) What happens to delay if you increase load capacitance?

delay increases.

8)What happens to delay if we include a resistance at the output of a CMOS circuit?

Increases. (RC delay)

9)What are the limitations in increasing the power supply to reduce delay?

The delay can be reduced by increasing the power supply but if we do so the heating effect
comes because of excessive power, to compensate this we have to increase the die size which
is not practical.

10)How does Resistance of the metal lines vary with increasing thickness and increasing
length?

R = ( *l) / A.

11)For CMOS logic, give the various techniques you know to minimize power
consumption?

Power dissipation=CV2f ,from this minimize the load capacitance, dc voltage and the
operating frequency.

12) What is Charge Sharing? Explain the Charge Sharing problem while sampling data
from a Bus?

In the serially connected NMOS logic the input capacitance of each gate shares the charge
with the load capacitance by which the logical levels drastically mismatched than that of the
desired once. To eliminate this load capacitance must be very high compared to the input
capacitance of the gates (approximately 10 times).

13)Why do we gradually increase the size of inverters in buffer design? Why not give
the output of a circuit to one large inverter?

Because it can not drive the output load straight away, so we gradually increase the size to
get an optimized performance.
14)What is Latch Up? Explain Latch Up with cross section of a CMOS Inverter. How
do you avoid Latch Up?

Latch-up is a condition in which the parasitic components give rise to the Establishment of
low resistance conducting path between VDD and VSS with Disastrous results.

15) Give the expression for CMOS switching power dissipation?

CV2

16) What is Body Effect?

In general multiple MOS devices are made on a common substrate. As a result, the substrate
voltage of all devices is normally equal. However while connecting the devices serially this
may result in an increase in source-to-substrate voltage as we proceed vertically along the
series chain (Vsb1=0, Vsb2 0).Which results Vth2>Vth1.

17) Why is the substrate in NMOS connected to Ground and in PMOS to VDD?

we try to reverse bias not the channel and the substrate but we try to maintain the
drain,source junctions reverse biased with respect to the substrate so that we dont loose our
current into the substrate.

18) What is the fundamental difference between a MOSFET and BJT ?

In MOSFET, current flow is either due to electrons(n-channel MOS) or due to holes(p-

channel MOS) - In BJT, we see current due to both the carriers.. electrons and holes. BJT is a
current controlled device and MOSFET is a voltage controlled device.

19)Which transistor has higher gain. BJT or MOS and why?

BJT has higher gain because it has higher [Link] is because the current in
BJT is exponentially dependent on input where as in MOSFET it is square law.

20)Why do we gradually increase the size of inverters in buffer design when trying to
drive a high capacitive load? Why not give the output of a circuit to one large inverter?

We cannot use a big inverter to drive a large output capacitance because, who will drive the
big inverter? The signal that has to drive the output cap will now see a larger gate
capacitance of the BIG [Link] this results in slow raise or fall times .A unit inverter can
drive approximately an inverter thats 4 times bigger in size. So say we need to drive a cap of
64 unit inverter then we try to keep the sizing like say 1,4,16,64 so that each inverter sees a
same ratio of output to input cap. This is the prime reason behind going for progressive
sizing.

21)In CMOS technology, in digital design, why do we design the size of pmos to be
higher than the [Link] determines the size of pmos wrt nmos. Though this is a
simple question try to list all the reasons possible?

In PMOS the carriers are holes whose mobility is less[ aprrox half ] than the electrons, the
carriers in NMOS. That means PMOS is slower than an NMOS. In CMOS technology, nmos
helps in pulling down the output to ground ann PMOS helps in pulling up the output to Vdd.
If the sizes of PMOS and NMOS are the same, then PMOS takes long time to charge up the
output node. If we have a larger PMOS than there will be more carriers to charge the node
quickly and overcome the slow nature of PMOS . Basically we do all this to get equal rise
and fall times for the output node.

22)Why PMOS and NMOS are sized equally in a Transmission Gates?

In Transmission Gate, PMOS and NMOS aid each other rather competing with each other.
That's the reason why we need not size them like in CMOS. In CMOS design we have
NMOS and PMOS competing which is the reason we try to size them proportional to their
mobility.

23)All of us know how an inverter works. What happens when the PMOS and NMOS
are interchanged with one another in an inverter?

I have seen similar Qs in some of the discussions. If the source & drain also connected
properly...it acts as a buffer. But suppose input is logic 1 O/P will be degraded 1 Similarly
degraded 0;

24)A good question on Layouts. Give 5 important Design techniques you would follow
when doing a Layout for Digital Circuits?

a)In digital design, decide the height of standard cells you want to [Link] depends upon
how big your transistors will [Link] reasonable width for VDD and GND metal
[Link] uniform Height for all the cell is very important since this will help you
use place route tool easily and also incase you want to do manual connection of all the blocks
it saves on lot of area.
b)Use one metal in one direction only, This does not apply for metal 1. Say you are using
metal 2 to do horizontal connections, then use metal 3 for vertical connections, metal4 for
horizontal, metal 5 vertical etc...
c)Place as many substrate contact as possible in the empty spaces of the layout.
d)Do not use poly over long distances as it has huge resistances unless you have no other
choice.
e)Use fingered transistors as and when you feel necessary.
f)Try maintaining symmetry in your design. Try to get the design in BIT Sliced manner.

25)What is metastability? When/why it will occur?Different ways to avoid this?

Metastable state: A un-known state in between the two logical known [Link] will happen
if the O/P cap is not allowed to charge/discharge fully to the required logical levels.
One of the cases is: If there is a setup time violation, metastability will occur,To avoid this, a
series of FFs is used (normally 2 or 3) which will remove the intermediate states.
26)Let A and B be two inputs of the NAND gate. Say signal A arrives at the NAND gate
later than signal B. To optimize delay of the two series NMOS inputs A and B which
one would you place near to the output?

The late coming signals are to be placed closer to the output node ie A should go to the nmos
that is closer to the output.

VLSI & ASIC MISCELLANEOUS INTERVIEW QUESTIONS

1)Explain zener breakdown and avalanche breakdown?

A thermally generated carrier (part of reverse saturation current) falls down the junction
barrier and acquires energy from the applied potential. This carriers collides with a crystal
ion and imparts sufficient energy to disrupt a covalent [Link] addition to the original carrier,
a new electron-hole pair has been generated. These carriers may also pick up sufficient
energy and creates still another electron-hole pair. This cumulative process is called the
Avalanche breakdown.
A reverse electric field at the junction causes a strong force to be applied on a bounded
electron by the field to tear it out of its covalent bond. The new hole-electron pair which is
created increases the reverse current, called zener breakdown.

2)What is Instrumentation Amplifier(IA) and what are all the advantages?

An instrumentation amplifier is a differential op-amp circuit providing high input

impedances with ease of gain adjustment by varying a single resistor

3) What is the fundamental difference between a MOSFET and BJT ?

In MOSFET,current flow is either due to electrons(n-channel MOS) or due to holes(p-

channel MOS)
- In BJT, we see current due to both the carriers.. electrons and holes. BJT is a current
controlled device and MOSFET is a voltage controlled device.

4) What is the basic difference between Analog and Digital Design?

Digital design is distinct from analog design. In analog circuits we deal with physical signals
which are continuous in amplitude and time. Ex: biological data, sesimic signals, sensor
output, audio, video etc.

Analog design is quite challenging than digital design as analog circuits are sensitive to
noise, operating voltages, loading conditions and other conditions which has severe effects
on performance. Even process technology poses certain topological limitations on the circuit.
Analog designer has to deal with real time continuous signals and even manipulate them
effectively even in harsh environment and in brutal operating conditions.
Digital design on the other hand is easier to process and has great immunity to noise. No
room for automation in analog design as every application requires a different design. Where
as digital design can be automated. Analog circuits generally deal with instantaneous value
of voltage and current(real time). Can take any value within the domain of specifications for
the [Link] of passive elements which contribute to the noise( thermal) of the circuit .
They are usually more sensitive to external noise more so because for a particular function a
analog design
uses lot less transistors providing design challenges over process corners and temperature
ranges. deals with a lot of device level physics and the state of the transistor plays a very
important role Digital Circuits on the other hand deal with only two logic levels 0 and 1(Is it
true that according to quantum mechanics there is a third logic level?) deal with lot more
transistors for a particular logic, easier to design complex designs, flexible logic synthesis
and greater speed although at the cost of greater power. Less sensitive to noise. design and
analysis of such circuits is dependant on the clock. challenge lies in negating the timing and
load delays and ensuring there is no set up or hold violation.

5)What is ring oscillator? And derive the freq of operation?

Ring oscillator circuit is a coupled inverter chain with the output being connected to the input
as feedback. The number of stages(inverters) is always odd to ensure that there is no single
stable state(output value). sometimes one of the stages consists of a logic gate which is used
to initialise and control the circuit. The total time period of operation is the product of
2*number of gates and gate(inverter) delay. And frequency of operation will be inverse of
time period.
Application: used as prototype circuits for modeling and designing new semiconductor
processes due to simplicity in design and ease of use. Also forms a part of clock recovery
circuit.

6)What are RTL, Gate, Metal and FIB fixes? What is a "sewing kits"?

There are several ways to fix an ASIC-based design. >From easiest to most extreme:

RTL Fix -> Gate Fix -> Metal Fix -> FIB Fix

First, let's review fundementals. A standard-cell ASIC consists of at least 2 dozen

manufactured layers/masks. Lower layers conists of materialsmaking up the actual CMOS
transistors and gates of the design. The upper 3-6 layers are metal layers used ti connect
everything together. ASICs, of course, are not intended to be flexible like an FPGA,
however, important "fixes" can be made during the manufacturing process. The progression
of possible fixes in the manufacturing life cycle is as listed above.

An RTL fix means you change the Verilog/VHDL code and you resynthesize. This usually
implies a new Plance&Route. RTL fixes would also imply new masks, etc. etc. In other
words - start from scratch.

A Gate Fix means that a select number of gates and their interconections may be added or
subtracted from the design (e.g. the netlist). This avoids resynthesis. Gate fixes preserve the
previous synthesis effort and involve manually editing a gate-level netlist - adding gates,
removing gates, etc. Gate level fixes affect ALL layers of the chip and all masks.

A Metal Fix means that only the upper metal interconnect layers are affected. Connections
may be broken or made, but new cells may not be added. A Sewing Kit is a means of adding
a new gate into the design while only affecting the metal layers. Sewing Kits are typically
added into the initial design either at the RTL level or during synthesis by the customer and
are part of the netlist. A Metal Fix affects only the top layers of the wafers and does not
affect the "base" layers.

Sewing Kits are modules that contain an unused mix of gates, flip-flops or any other cells
considered potentially useful for an unforseen metal fix. A Sewing Kit may be specified in
RTL by instantiating the literal cells from the vendor library. The cells in the kit are usually
connected such that each cell's output is unconnected and the inputs are tied to ground.
Clocks and resets may be wired into the larger design's signals, or not.

A FIB Fix (Focussed Ion Beam) Fix is only performed on a completed chip. FIB is a
somewhat exotic technology where a particle beam is able to make and break connections on
a completed die. FIB fixes are done on individual chips and would only be done as a last
resort to repair an otherwise defective prototype chip. Masks are not affected since it is the
final chip that is intrusively repaired.

Clearly, these sorts of fixes are tricky and risky. They are available to the ASIC developer,
but must be negotiated and coordinated with the foundry. ASIC designers who have been
through enough of these fixes appreciate the value of adding test and fault-tolerant design
features into the RTL code so that Software Fixes can correct mior silicon problems!