Assignment
1. a) A logic circuit has four inputs A, B, C and D. The output F is high when the majority of inputs are
logic 0. Minimize the function and also implement the circuit.
b) A logic circuit has four inputs A, B, C and D. The output F is high when the majority of inputs are
logic 1. Minimize the function and also implement the circuit.
c) Construct a boolean function of four variables A, B, C, and D that has an output 1 when at least three
of A, B, C, and D are having values 0, and output 0 in all other cases. Minimize the function and also
implement the circuit.
d) Construct a boolean function of four variables A, B, C, and D that has an output 1 when at least three
of A, B, C, and D are having values 1, and output 0 in all other cases. Minimize the function and also
implement the circuit.
e) A logic circuit has three inputs, A, B, and C. It generates an output of 1 only when A=0, B=1, C=0, or
when A=1, B=1, C=0. Design a combinational circuit for this system.
2. a) Convert the following:
(i) (135A.9F)16 = (?)2 (ii) (565)5=(?)4 (iii) (6473)8=(?)6
b) Convert the following numbers
i. A8516 to decimal
ii. 14278 to decimal
iii. 1011000110012 to octal
iv. (7092)10 =(?)BCD
v. (5704)10 =(?)XS-3
vi. (3AF)16=(?)10
c) Evaluate the following:
(i) 100001÷110 (ii) 101110×1011 (iii) 11111111-1111
d) What is code? Prove that the code 2-4-2-1 is a self reflecting code.
e) Prove that the code 5-2-1-1 is a self reflecting code.
3. a) What is the purpose of parity bit? Write limitations of parity method with example.
b) If the 7-bit hamming code word received by a receiver is 1011011. Assuming the odd/even parity
state. Whether the received code word is correct or wrong. If wrong locate the bit having error.
c) Convert the logic expression A+ B C +AB D +ABCD to standard SOP form.
d) Given the logic expression A+ B C +AB D +ABCD
i. Express in standard SOP
ii. Draw K-map for the equation
iii. Minimize and realize using NAND gates only
f) Simplify the following Boolean expressions using Boolean technique:
i. AB+ AC +A B C( AB+C)
ii. A′B′C + (A + B + C′)′ + A′B′C′D′
iii. A B+ ABC + A (B+ A B)
iv. BD + B (D + E) + D′ (D + F)
v. (A + C)(A + D)(B + C)(B + D)
vi. (A′ + B′ + D′) (A′ + B + D′) (B + C + D) (A + C′) (A + C′ + D)
4. a) Implement a full adder using NAND/NOR gates only.
b) Implement a full subtractor using NAND/NOR gates only.
c) Implement a half adder using NAND/NOR gates only.
d) Implement a half subtractor using NAND/NOR gates only.