Power Reduction

Techniques in the SoC

Clock Network

Low Power Design for SoCs ASIC Tutorial SoC Clock.1

Clock.1 ©M.J. Irwin, PSU, 1999

Clock Power
l Why clock power is important/large
» Generally the signal with the highest frequency
» Typically drives a large load
– all sequential logic elements
– all precharged/dynamic logic
– distributed throughout chip, so lots of wiring
» DEC 21164’s clock accounts for 40% of total
chip power
– 3.75nF total clock load
– 20W (out of 50W) in clock distribution network
Low Power Design for SoCs ASIC Tutorial SoC Clock.2
Clock.2 ©M.J. Irwin, PSU, 1999

1
 Processor Power Budgets

Clock
Datapath
Memory
I/O (pads)

Inner circle: low end embedded microprocessor

Next circle: high end CPU with on-chip cache
Next circle: MPEG2 decoder ASIC
Outer circle: ATM switch ASIC
Low Power Design for SoCs ASIC Tutorial SoC Clock.3
Clock.3 ©M.J. Irwin, PSU, 1999

Clock Power Reduction

Pclock = CVdd2f
l Minimize voltage (V) using half swing clocks
l Minimize clock load (C)
» clock gating
» careful routing, distributed drivers
l Minimize clock frequency (f)
» DET flipflops
» localized PLL to multiply frequency of clock
l GALS design approach
Low Power Design for SoCs ASIC Tutorial SoC Clock.4
Clock.4 ©M.J. Irwin, PSU, 1999

2
 Reduced Swing Clock
Vdd N-device clock

Gnd P-device clock

Regular Clock

Vdd
P-device clock
Vtp
Vtn N-device clock
Gnd
Half Swing Clock

Low Power Design for SoCs ASIC Tutorial SoC Clock.5

Clock.5 ©M.J. Irwin, PSU, 1999

Half Swing Clocks

l Advantages
» as long as Vtn (Vtp) less (greater) than 1/2Vdd
on-off characteristics of nfet (pfet) unchanged
l Disadvantages
» sequential element delay approx. doubled
(propagation delay and setup/hold time) due to
increased on-resistance
» half-swing clock generator done via charge
sharing, so sleep modes problematic
» not appropriate for very low voltage systems

Low Power Design for SoCs ASIC Tutorial SoC Clock.6

Clock.6 ©M.J. Irwin, PSU, 1999

3
 Clock Gating
l Most popular method for power reduction
of clock signals and fu’s
» often idle functional units Functional
– e.g., floating point units clock unit

» need circuit to generate

enable signal enable
– increases complexity of control logic
– timing critical to avoid clock glitches at AND gate
output
» additional gate delay on clock signal
– masking AND gate can replace a buffer in the
clock distribution tree
Low Power Design for SoCs ASIC Tutorial SoC Clock.7
Clock.7 ©M.J. Irwin, PSU, 1999

Glitch Free Clock Gating

< From <

B
< Gated
A Clock Clock
Clock
0 1 (1)

Gated Clock (1)

REG <
Clock
Gated
Gated Clock (2)
Clock Clock

(2)

Low Power Design for SoCs ASIC Tutorial SoC Clock.8

Clock.8 ©M.J. Irwin, PSU, 1999

4
 Gated Clock FSM Architecture

Comb
Reg Logic

AF - Activation Function,
AF
Latch

Which evaluates to logic 1

when clock needs to be stopped.

Gated Clock
Clock

Low Power Design for SoCs ASIC Tutorial SoC Clock.9

Clock.9 ©M.J. Irwin, PSU, 1999

Clock Tree Construction to

Facilitate Gating
Can insert clock gating at
multiple levels in clock tree
Can shut off entire subtree
if all gating conditions are
satisfied

Clock

Idle
condition
Gated
Clock clock

H-Tree Clock Network

Low Power Design for SoCs ASIC Tutorial SoC Clock.10
Clock.10 ©M.J. Irwin, PSU, 1999

5
 Clock Driver Distribution
Comparison
Dimension (cm) SD (W) DD (W)
0.25 0.052 0.051
0.5 0.206 0.101
0.75 0.464 0.152
1.0 0.825 0.202
1.25 1.29 0.253
1.5 1.85 0.303
1.75 2.53 0.354

SD = single driver, DD = distributed driver (H-tree)

3.3V supply, 100MHz frequency, 1 micron feature size

Low Power Design for SoCs ASIC Tutorial SoC Clock.11

Clock.11 ©M.J. Irwin, PSU, 1999

Clock Tree Structure Affects

Gating
x1
R1
x1 R1

x2 R2
Clock A Clock A
R3
x3
x1+x3
B B
R3 R2

R4 x2
R4
x2+x4 x4
(a) (b)

Assuming x1, x2, x3, x4 are mutually exclusive

Low Power Design for SoCs ASIC Tutorial SoC Clock.12
Clock.12 ©M.J. Irwin, PSU, 1999

6
 Multiple Frequency Clocks
f1
Bus Interface Parallel
f < f1 < f2 < f3
serial
I/O interface
PLL controller

System PLL
f f3
clock

Key is in the design

PLL
of the local circuits RISC Core
used to generate f2
the clock signal in
each module

Low Power Design for SoCs ASIC Tutorial SoC Clock.13

Clock.13 ©M.J. Irwin, PSU, 1999

Clock Frequency Multipliers

Circuit Tech Input Vdd Power Area

Freq Diss
PLL1 0.8µ 50MHz 5V 16mW 0.31mm2
PLL2 0.5µ 50MHz 3.3V 10mW 0.52mm2
DDL3 33MHz 3.8V 49.4mW

1 Young, 1992
2 Alvarez, 1995
3 Gupta

Low Power Design for SoCs ASIC Tutorial SoC Clock.14

Clock.14 ©M.J. Irwin, PSU, 1999

7
 GALS Design Style
l Reduce clock power consumption by using
a Globally Asynchronous, Locally
Synchronous (GALS) design style
l Overheads for
» local clock generation
– independent clock generators
– low power global clock reference signal with local
clock frequency multipliers
» global asynchronous communication
l Skew tolerant
Low Power Design for SoCs ASIC Tutorial SoC Clock.15
Clock.15 ©M.J. Irwin, PSU, 1999

GALS Architecture

f1
Bus Interface Parallel
serial
I/O interface
PLL controller
PLL
f3

data
PLL
RISC Core
f2
handshake
protocol

Low Power Design for SoCs ASIC Tutorial SoC Clock.16

Clock.16 ©M.J. Irwin, PSU, 1999

8
 Key References
Alvarez, A wide bandwidth low voltage PLL for PowerPC microprocessors, IEEE
Journal of SSC, 30:383-391, April 1995.
Chen, A simple technique for global clock power reduction, PSU Internal Report,
1998.
Chen, Clock power issues in system-on-a-chip designs, Proc. of Workshop on
VLSI, pp. 48-53, March 1999.
Friedman, Clock distribution design in VLSI circuits: An Overview, Proc. of
ISCAS, pp. 1475-1478, May 1994.
Gupta, Features of differential delay line used on the embedded ultra low power
Intel486® in [Link]/design/intarch/papers/[Link]
Hemani, Lowering power consumption in clock by using GALS design style, Proc.
of DAC, pp. 873-878, 1999.
Kojima, Half-swing clocking scheme for 75% power saving, IEEE Journal of SSC,
30(4):432-435, April 1994.
Tellez, Activity driven clock design for low power circuits, Proc. of ICCAD, pp. 62-
65, Nov. 1995.
Young, A PLL clock generator with 5 to 110MHz of lock range for
microprocessors, IEEE Journal of SSC, pp. 1599-1607, Nov. 1992
Low Power Design for SoCs ASIC Tutorial SoC Clock.17
Clock.17 ©M.J. Irwin, PSU, 1999