MODULE 2

DEVICES AND COMMUNICATION BUSES FOR DEVICES

NETWORK

IO TYPES AND EXAMPLES

There are two types of IO ports:
1. Serial Port
2. Parallel Port
Serial Port:
➢ A serial port is used for serial communication. A serial port communication is over
short or long distances.
➢ In Serial communication, over a given line or channel one bit can communicate and
the bits transmit at periodic intervals generated by a clock.
Parallel Port:
➢ A parallel port is used for parallel communication. Parallel communication means that
multiple bits can communicate over a set of parallel lines at any given instance.
➢ A parallel port communicates within the same board, between ICs or wires over very
short distances of at most less than a meter.

• A serial or parallel port can provide certain special features and sophistication by
using a processing element.
• Ports can interconnect by wireless.
• Wireless or mobile communication is serial communication but without wires, can be
over a short-range personal area network as well as long-range wireless network, and
transmission takes place by using carrier frequencies.
• The carrier modulates the serial bits before transmission in air. A receiver
demodulates and retrieves the serial bits back.

Serial and parallel ports of IO devices can be classified into following IO types:
i. Synchronous serial input
ii. Synchronous serial output
iii. Asynchronous serial UART input
iv. Asynchronous serial UART output
v. Parallel port one bit input
vi. Parallel port one bit output
vii. Parallel port input
viii. Parallel port output.
Some devices function both as input and as output: for example, a modem.

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Synchronous Serial Input:

• The part 1 in Figure 1(a) shows a synchronous input serial port in which each bit in each
byte and each received byte is in synchronization, i.e. separated by a constant interval or
phase difference shown in part 2 in Figure 1(a).
• If clock period equals T, then each byte at the port is received at input in period 8T. The
bytes are received at constant rates. Each byte at the input port separates by 8T and data
transfer rate for the serial line bits is 1/T bit per second.
• The sender, along with the serial bits, also sends the clock pulses SCLK (serial clock) to
the receiver port pin, which synchronizes the serial data-input bits with clock bits.
• The serial data input and clock pulse-input are on same input line when the clock pulses
either encode or modulate serial data input bits suitably.
• The receiver detects clock pulses and receives data bits after decoding or demodulating.
• When a separate SCLK input is sent, the receiver detects at the middle, positive or
negative edge of the clock pulses that indicate whether data-input is 1 or 0 and saves the
bits in 8-bit shift register.
• The processing element at the port (peripheral) saves the byte at a port register from
where the microprocessor reads the byte.
• Synchronous serial input is also called master output slave input (MOSI) when the
SCLK is sent from the sender to the receiver and slave is forced to synchronize sent
inputs from the master as per the master clock inputs.
• Synchronous serial input is also called master input slave output (MISO) when the
SCLK is sent to the sender (slave) from the receiver (master) and the slave is forced to
synchronize sending the inputs to master as per the master clock's outputs.
• Synchronous serial input is used for inter-processor transfers, audio inputs and streaming
data inputs.

Figure 1 (a): Synchronous Serial Input Port

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Synchronous Serial Output:

Figure 1 (a): Synchronous Serial Input Port

• The part 3 in figure 1(a) shows a synchronous output serial port.
• Each bit in each byte is in synchronization with a clock.
• The bytes are sent at constant rates [part 4 in Figure 1(a)]. If the clock period equals
T, then the data transfer rate is 1/T bps. The sender sends either the clock pulses at
SCLK pin or the serial data output and clock pulse-input through same output line
when the clock pulses either suitably modulate or encode the serial output bits.
• The processing element at the port (peripheral) sends the byte through a shift register
at the port to which the microprocessor writes the byte.
• Synchronous serial output is used for inter-processor transfers, audio outputs and
streaming data outputs.

Synchronous Serial Input-Output:

Figure 1 (a): Synchronous Serial Input Output Port
• The part 5 in Figure 1(a) shows a synchronous serial input-output port. Each bit in
each byte synchronizes with the clock input and output.
• The bytes are sent or received at constant rates as shown in parts (2) and (4) in Figure
1(a).
• The IOs are on same IO line when the clock pulses suitably modulate or encode the
serial input and output, respectively. If the clock period equals T, then the data
transfer rate is 1/ T bps.
• The processing element at the port (peripheral) sends and receives the byte at a port
register to or from which the microprocessor writes or reads the byte.
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• Synchronous serial input/outputs are also called master input slave output (MISO) and
master output slave input (MOSI), respectively.
• They are used for inter-processor transfers and streaming data. The bits are read from
or written on magnetic media such as a hard disk or on optical media such as a CD by
using devices with serial synchronous IO ports.
• The part 6 in Figure 1(a) shows the IO synchronous port when input and output lines
are separate.

Asynchronous Serial input:

Figure 1(b) and (c): Asynchronous Serial Input and Output

• Figure 1 (b) shows the asynchronous input serial port link, denoted by RxD (receive
data). Each RxD bit is received in each byte at fixed intervals but each received byte
is not in synchronization.
• The bytes can separate by variable intervals or phase differences. Figure 1(c). On the
right side, shows the starting point of receiving the bits for each byte, indicated by a
line transition from 1 to 0 for a period T.
• When a sender shifts after every clock period T, then a byte at the port is received at
input in period 10T or 11T. The time of 2T is due to use of additional bits at the start
and end of each byte. An addition time of 1T is taken when a P-bit is sent before the
stop hit.
• The bit transfer rate (for the serial line bits) is (1/ T) baud per second but different
bytes may be received at varying intervals.
• The receiver detects bits at the intervals of T from the middle of the first indicating bit
n = 0. 1. 10 or 11, finds out whether the data-input is 1 or 0 and saves the bits in an
8-bit shift register. The processing element at the port (peripheral) saves the byte at a
port register, from where the microprocessor reads the byte.
• Asynchronous serial input is also called UART input if the serial input is according to
the UART protocol. Asynchronous serial input is used for keypad and modem inputs.

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Asynchronous Serial Output:

Figure 1(b): Asynchronous Serial Input and Output

• Figure 1(b) shows the asynchronous output serial port line. Denoted by TxD (transmit
data).
• Each bit in each byte is sent at fixed intervals but each output byte is not in
synchronization (it is separated by a variable interval or phase difference).
• The Figure 1(c) shows the starting point of sending the bits for each byte, which is
indicated by a line transition from 1 to 0 for a period T. The sender port of TxD does
not send clock pulses along with the bits.
• The sender transmits bytes at the minimum intervals of n T. Bits start from the middle
of the start indicating bit, where n= 0, 1, ..., 10 or 11 and sends the bits through a 10-
or 11-bit shift register [Figure 1(c)]. The processing element at the port (peripheral)
sends the byte at a port register to where the microprocessor writes the byte.
• Asynchronous serial output is also called UART output if the serial output is
according to a UART protocol.
• Asynchronous serial output is used for modem and printer inputs.

Parallel Port:
A parallel port can have one or multibit input or output and can be bi-directional IO.
i) One bit input, output and IO
ii) Eight or more bit input, output and IO.

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Half Duplex and Full Duplex:

• The part 5 in above figure on the left side shows the IO serial port (bi-directional half-
duplex serial port).
• The part 6 in the above figure shows the separate input and output serial port lines.
• There are two types of communication ports for IO’s: serial and parallel.
• Serial line port communication is synchronous when a clock of the master device
controls the synchronization of the bits on the line.
• Serial line port communication is asynchronous when clocks of the sender and
receiver are independent and bytes are received, not necessarily at constant phase
differences.
• Serial communication can be full duplex, which means simultaneously
communication both ways, or half duplex, which means one way communication.

Examples of Serial and Parallel Port IOs

Table 1 gives a classification of IO devices into various types. It also gives examples of cache
type.
Table 1 Examples of various types of IO devices
IO Device Type Examples
Inter-processor data transfer, reading from CD or hard disk,
audio input. video input, dial tone, network input, transceiver
Serial synchronous input input, scanner input, remote controller input, serial IO bus
input, reading from flash memory using SDIO (Secure Data
Association IO) card
Inter-processor data transfer. multiprocessor communication,
writing to CD or hard disk, audio output, video output, dialer
Serial synchronous output output. network device output, remote TV Control, transceiver
output, and serial IO bus output, writing to flash memory using
SDIO card

Keypad controller serial data-in, mice, keyboard controller data

in, modem input, character inputs on serial line [also called
Serial asynchronous input UART (universal receiver and transmitter) input when
according to UART mode]
Output from modem, output for printer, the output on a serial
Serial asynchronous output line [also called UART output when according to UART model

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(i) Completion of a revolution of a wheel.

(ii) Achieving preset pressure in a boiler.
(iii) Exceeding the upper limit of the permitted weight over
Parallel port single bit input thepan of an electronic balance.
(iv) Presence of a magnetic piece in the vicinity of or
withinreach of a robot arm to its end point and
(v) Filling a liquid up to a fixed level

(i) PWM output for a DAC, which controls liquid level,

temperature, pressure, speed or angular position of a
Parallel port single bit output rotating shaft or a linear displacement of an object or a
DC motor control
(ii) Pulses to an external circuit
(i) ADC input from liquid level measuring sensor or
temperature sensor or pressure sensor or speed sensor or
Parallel port input DC motor rpm sensor
(ii) Encoder inputs for bits for angular position of a rotating
shaft or a linear displacement of an object
(i) LCD controller for multiline LCD display matrix unit in
a cellular phone to display on screen the phone number,
time, messages, character outputs or pictogram bit-
Parallel port output images or e-mail or web page
(ii) Print controller
(iii) Stepper motor coil driving output bits

SERIAL COMMUNICATION DEVICES:

Synchronous, Iso-synchronous and Asynchronous Communications from
Serial Devices
• Synchronous Communication: When a byte (character) or frame (a collection of
bytes) of data is received or transmitted at constant time intervals with uniform phase
differences, the communication is called synchronous. Bits of a data frame are sent in
a fixed maximum time interval.
• Iso-synchronous is a special case when the maximum time interval can be varied.
• An example of synchronous serial communication is frames sent over a LAN. Frames
of data communicate, with the time interval between each frame remaining constant.

Table 2 gives a synchronous device port bits.

Sl. Bits at Ports Compulsory Explanation

No. or Optional
1 Sync code bits or Optional A few bits (each separated by interval ΔT)
bi-sync code bits or as sync code for frame synchronization or
frame start and signature precedes the data bits. There may
end signalling bits be inversion of code bits after each frame.
Flag bits at start and end are also used in
certain protocols.

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2 Data Bits Compulsory M frame bits or 8 bits transmit such that

each bit is at the line for time ΔT or each
frame is at the line for the time m.ΔT2.
3 Clock Bits Most not Either on a separate clock line or on a single
Optional line such that the clock information is also
embedded with the data bits by an
appropriate encoding or modulation.

Figure 1 (a): Synchronous Serial Input Port

Figure 1(a) part 2 showed the serial IO bit format and serial line states as a function of time.
Two characteristics of synchronous communication are as follows:
1. Bytes (or frames) maintain a constant phase difference. It means they are
synchronous, that is, in synchronization. There is no permission for sending either the
bytes or the frames at random time intervals; this mode therefore does not provide for
handshaking during the communication interval. [Handshaking means that the source
and destination first exchange the signals between them before they communicate the
data bits.] The master is the one whose clock pulses guide the transmission and slave
is the one which synchronizes the bits as per the master clock.
2. A clock ticking at a certain rate must always be there to serially transmit the bytes (or
frames). The clock is not always implicit to the synchronous data receiver. The
transmitter generally transmits the clock rate information in the synchronous
communication of the data.

Figure 2: Ten ways by which the synchronous signals with the clocking information from
a master device to slave device

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• Figure 2 gives ten methods by which synchronous signals, with the clocking
information, are sent. (i) There are two separate lines for the data bits and clock. The
parallel-in serial-out (PISO) and serial-in parallel-out (SIPO) are used for transmitting
and receiving the signals for data, respectively. (ii) There is a common line and the
clock information is encoded by modulating the clock with the stream of bits. (iii)
There are preceding and succeeding additional synchronizing and signalling bits.
• There are five common methods of encoding the clock information into a serial
stream of the bits: (a) Frequency Modulation (FM) (b) Mid Frequency Modulation
(MFM) (c) Manchester coding (d) Quadrature amplitude modulation (QAM) (e) Bi-
phase coding. The synchronous receiver separates serial bits of the message as well as
synchronizing clock.

Asynchronous Communication:

• When a byte (characters) or frame (a collection of bytes) of data received or

transmitted at variable time intervals, communication is called asynchronous.
• Voice data on the line is sent in asynchronous mode.

• Two characteristics of asynchronous communication are as follows:

1. Bytes (or frames) need not maintain a constant phase difference and are
asynchronous, that is, not in synchronization. Bytes or frames can be sent at
variable time intervals. This mode therefore facilitates in between handshaking
between the serial transmitter port and serial receiver port.
2. Though the clock must tick at a certain rate to transmit bits of a single byte (or
frame) serially, it always implicit to the asynchronous data receiver. The
transmitter does not transmit (neither separately nor by encoding using
modulation) along with serial stream of bits any clock rate information in
asynchronous communication. The receiver clock is thus not able to maintain
identical frequency and constant phase difference with the transmitter clock.
• When a device sends data using a serial communication frame, it may not be as
simple. It can be complex and has to be as per the protocol, which is followed by
transmitting and receiving devices during communication between them.
• A communication system may use the following protocols for synchronous or
asynchronous transmission from a device port: RS232C, UART, HDLC, X.25, Frame
Relay, ATM, DSL and ADSL.
• The protocols in embedded network devices such as bridges, routers, embedded
Internet appliances use bridging, routing, application and web protocols.
• Internet enabled embedded systems use application protocols - HTTP (hypertext
transfer protocol), HTTPS (hypertext transfer protocol Secure Socket Layer), SMTP
(Simple Mail Transfer Protocol). POP3 (Post office Protocol version 3), ESMTP
(Extended SMTP), TELNET (Tele network), FTP (file transfer protocol), DNS
(domain network server), IMAP 4 (Internet Message Exchange Application Protocol)
and Bootp (Bootstrap protocol) and others.
• Embedded wireless appliances use wireless protocols-IrDA, Bluetooth, 802.11 and
others.

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RS232C/RS485 Communication:
1 RS232C:
a. RS232C communication between DTE (computer) COM (communication) port and
DCE (modem) port. DTE stands for 'Data Terminal Equipment” DCE stands for
"Data Communication Equipment” RS232C is an interfacing signal standard
between DCE and DTE

• Above figure showed the interfacing (handshaking) signals on a RS232C port.

• The receive data and transmit data signals from RS232C port are RxD and TxD,
respectively which is an asynchronous type and follow UART protocol.
• Receiver end voltage level from -3 to -25 V denotes logic 1 and voltage level
from +3 to +25 V denotes logic 0. Transmitter end voltage level from -5 to -15
V denotes logic 1 and voltage level from + 5 to + 15 V denote logic 0.
• RS232C port in a computer is used up to 9600 baud/s asynchronous serial
transmission rate with UART mode communication.
• Generally, baud rates are set at 300, 600, 1200, 4800 and 9600.
• RS232C port is used for keyboard serial communication at 1200 baud/s
asynchronous serial transmission rate with UART mode communication at IBM
PC COM port.
• The signals used are RTS, CTS, TxD and RxD for keypad communication.

2 RS485:
a. RS485, now called EIA-485 is a protocol for physical layer in case of two wires full
or half duplex serial connection between multiple points.
b. Transmission is at 35 Mbps upto 10 meter and 100 Kbps up 1.2 km.
c. Electrical signals are between +12 V and -7 V Logic 1 is +ve and 0 is reverse
polarity.
d. Difference in potential defines logic 1 and 0.
e. A converter is used to convert RS232C bits to RS485 and another for vice versa.

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UART

• Figure above shows the handshaking signals of RS232C port and UART serial bits in
the output to a serial line device.
• The UART mode is as follows:
1. A line is in non-return to zero (NRZ) state. It means that in the idle state the
logic state is 1 at serial line.
2. The start of serial bits is signalled by 1→0 transition (negative edge) on the
line for a period equal in reciprocal of baud rate. The baud rate is preset at
both receiver and transmitter. The receiver detects the start bit at middle of the
interval, logic 0 state of the transmitter start bit.
3. UART bits, when sending a byte, consist of start bit. 8 data bits (for example,
for an ASCII character or for a command word), option programmable bit (P-
bit) and stop bit, each during the interval δT, when sending or receiving a byte,
the logic states during interval 10 δT or 11 δT are as shown in Figure 1(c) as a
function of time t. A bit period, δT is equal to the reciprocal of baud rate, the
rate at which the bits from UART transmitter are sent. One extra bit before the
stop bit is programmable bit P and is called TB8 at the transmitter and RB8 at
the receiver.
4. The data bits in certain specific cases can be 5 or 6 or 7 instead of 8.
5. The stop bit can be for a minimum interval of 1.5 δT or 2 δT instead of δT in
certain specific cases.
6. Optional programmable bit (P-bit) can be used for parity detection or can be
used to specify the purpose of the serial data bits that are before the P-bit. For
example, P can specify bits as the bits of a control or command word when P
= 1 and data bits when P=0. Bit P can specify the address of receiver when P=
1 and data bits when P=0 so that only the addressed receiver wakes up and
receives the data in the subsequent data transfers. When P is used as
address/data specification, it provides a means to interface a number of UART
devices through a common set of TxD and RxD lines and form a UART bus.
• UART 16550 includes a 16-byte FIFO buffer and is nowadays used more commonly
as compared original IBM PC COM port, which had an 8-bit register at UART port
and was based on 8250 and did not include the FIFO buffer.

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HDLC Protocol:
• When data are communicated using the physical devices on a network, synchronous
serial communication may be used. HDLC (High Level Data Link Control) is an
International Standard protocol for a data link network. It is used for linking data from
point to point and between multiple points. It is used in telecommunication and
computer networks. It is a bit-oriented protocol. The total number of bits is not
necessarily an integer multiple of a byte or a 32-bit integer. Communication is full
duplex.
• Table 3 gives the synchronous network device port bits in an HDLC protocol. The
reader may refer to standard textbook, for example, "Data Communications,
Computer Networks and Open Systems" by Fred Halsall from Pearson Education
(1996) for details of HDLC and its field bits.

Serial Data Communication using the SPI, SCI and SI Ports:

• Microcontrollers have internal devices for SPI or SCI or SI.

• Each device has separate registers for control, status, serially received data bits and
transmitting serial bits. Each device is programmable as described below. The device
can be used in programmed IO modes or in interrupt driven reception and
transmission.

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Figure 3 (a) SPI Port Signal, (b) SPI port programmable features and DDR at port D in
68HC11/12 (c) SCI port in 68HC11/12 (d) SI port in 8051 (e) SDIO communication feature
(f) SDIO card structure

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Synchronous Peripheral Interface (SPI) Port:

• Figure (b) shows SPI port in 68HC11 and 68HC12 microcontroller. It has full-
duplex feature for synchronous communication.
• There are signals SCLK for serial clock, MOSI and MISO output from and input to
master.
• Figure (b) show programmable features and DDK feature of Port D. An SPM feature
is programmable rates for clock bits, and therefore for the serial out of the data bits
down so the interval of 0.5 µs for an 8 MHz crystal at 65HC11.
• SPI is also programmable for defining the occurrence of negative and positive edges
within bits at serial data out or in .It is also programmable in the open-drain or totem
pole output from a master to a slave and for device selection as master or slave.
• This can be done by a signal to hardware input SS (slave select when D) pin. In the
hardware the slave select pin connects to ‘1’ at the user SI device and to '0' at the
slave. Defining SPI at slave or master can also be done by software. Programming
bit at the device control register does this.
• 68HC12 provides SPI communication device operations at 4 Mbps SPI device
operates up to 2 Mbps in 68HC11.

Serial Connect Interface (SCI) Port:

• Figure (c) shows an SCI port programmable features and DDR port bits in
68HC11/12 SCI is a UART asynchronous mode port. Communication is in full-

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duplex mode for the SCI transmission and receiver SCI baud rates are fixed as
prescaling bits.
• Rate not programmable separately for individual serial in and out lines. A baud rate
can be selected among 32 possible ones by the three-rate bits and two prescaling bits.
The SCI receiver has a wake-up feature and is programmable by RWU (Receiver
wakeup Unavailable) bit It is enabled if RWU (1st bit of SCC2, Serial Communication
Control Register 2) is set, and is disabled if RWU is reset.
• If RWU if set, then the receiver of a slave is not interrupted by the succeeding bytes.
SC has two control register bits, TB8 and RB8. RWU feature helps in inter processor
communication, and SCI is defined for transmission and for reception using the SCC2
bits.
• UART communication, when programmed by control bits, is in 11-bit format. A
number of processors can communicate on the bus in UART mode RWU when RB8
and TB8 bits are set.
• There are separate hardware devices at 68HC11 for synchronous and asynchronous
communications. These are SPI and SCI, respectively 68HC12 provides two SCI
communication devices that can operate at two different clock rates Standard band
rates can be set up to 38.4 kbps.
• There is only one SCI and standard baud rates in 68HC11 can be set up to 9.6 kbps
only.

Serial Interface (SI) Port:

• Figure (d) shows an SI port. SI is a UART mode asynchronous port interface. It also
functions as USRT (universal synchronous receiver and transmitter), SI is therefore a
synchronous asynchronous serial communication port called USART (universal
synchronous-asynchronous receiver and transmitter) port. It is an internal serial IO
device in 8051.
• There is an on-chip common hardware device called Sl in Intel 80196. Its features are
as follows: programmable rates register after loading the 14 bits at BAUD_RATE
register twice.
• SI operates in one of the following ways:
1. Half-duplex synchronous mode of operation, called mode 0 When a 12 MHz
crystal is at 8051 and is attached to the processor, the clock bits are at the
intervals of 1 µs.
2. Full-duplex asynchronous serial communication, called mode 1 or 2 or 3.
Using a timer, the baud rate varies according to the programmed timer bits in
modes 1 and 3. Using SMOD bit at SFR called PCON, when mode 2 is used,

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the band rate is programmable at two rates only. It is 1/64 or 1/32 of oscillator
frequency at 8051 TB8 and RB8, when using 11-bit format, provide the 10th
bit for error detection or for indicating whether the sent data byte is a
command or data for the receiving SI device.
• Most microcontrollers have internal serial communication SPI and SCI or SI-like
devices for serial communication.

Secure Digital Input Output (SDIO):

• Secure Digital (SD) Association created a new flash memory card format, called SD
format.
• This SDIO card for SD format IOs [Figure (e)] has become a popular feature in
handheld mobile devices, PDAs, digital cameras and handheld embedded systems.
• SD card size is just 0.14 x 2.4x3.2 cm. SD card [figure (f)] is also allowed to stick out
of the handheld device open slot, which can be at the top in order to facilitate
insertion of the SD card.

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• SDIO is an SD card with programmable IO functionalities such that it (a) can be used
upto eight logical functions, (b) can provide additional memory storage in SD format,
and (c) can provide IOs using protocols in systems such as IrDA adapter. UART
16550, Ethernet adapter, GPS, WiFi, Bluetooth, WLAN, digital camera, barcode or
RFID code reader.
• Figure (e)shows an SDIO communication device port features. It supports SPI, 4-bit
and 1-bit SD formats.
• Both SPI and SD formats specify that there should be interrupt handling of the IOs
and also the CRC checks on transferred data and specifies capabilities for more tries
on error, SD10 card [Figure (f)] has 9 pins are for communication using SPI or SD.
• A processing element function is used as SDIO host controller to process the IOs. The
controller may include SPI controller to support SPT mode for the IO and supports the
needed protocol functionality internally Maximum clock rate supported for SPI is 20
MHz for a maximum of 20 Mbps data transfers.
• There is an optional 4-bit SD mode, which uses 4 data lines. Maximum clock rate
supported is 25 MHz for maximum 100 Mbps SD bit data transfer in 4-bit SD mode
Four serial bits simultaneously transmits at four times clock rate on 4 SD lines in this
mode.
• Four-bit SD mode is compromise between serial and parallel bits communication to
enhance serial transfer rate four times. In 1-bit SD mode, with 25 MHz clock the
maximum data transfer rate is 25 Mbps and one serial bit transmits at 1 line only.
• SDIO card has a control section called function 0. Is necessarily uses function 1 and
optionally uses functions between 2 and 7 (depending on the application in devices
used such as Bluetooth, PHS, GPS or digital camera).
• Each function has PCMIA (Personal Computer Manufacturer Interface Adapter)
defined card information structure and registers, for example, ID number, function
enable bit, supported bus width (1 or 4), voltage, power needs, clock rates and
interrupt enable bit. Each function's specifications for the register hits and protocols
have been defined in SD standard. A standard device driver can therefore be written.
A new function can also be defined.
• Data communication is in 48-bit command/request formal for 48-bit control register/
status register bits and supports data transfer of blocks of bytes. For single byte
transactions, SDIO card may also include a UART 16550 mode communication over
the SD bus.

PARALLEL DEVICE PORTS:

• The parallel port of devices transfers number of bits over the wires in parallel. Parallel
wires capacitive effect reduces the length up to which parallel communication can be
done. High capacitance results in delay for the bits at the other end undergoing
transition from 0 to 1 or from 1 to 0.
• High capacitance can also result in noise and cross talk (induced signals) between the
wires. Therefore, parallel port carries the bits up to short distances, generally within a
circuit board or IC.

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Figure 4 (a) Parallel input port, output port and a bi-directional port for connecting the
devices
• Figure 4(a) shows the parallel input, output, and bi-directional device ports. Figure
also shows a device interfacing circuit with the processor and system buses. Parallel
port inputs I0 to I7 may be to a keypad controller. Parallel port outputs O0 to O7 may
be output hits to LCD display output controller. BRi, and BR0 are the input and output
data buffers at bi-directional IO port.
• A device port connects to the address bus signals. Ai and Aj through a port address
decoder 𝐼𝑂𝑅𝐷 and 𝐼𝑂W𝑅 are additional control signals for a port device read and
write, respectively, in case of an 80x86 processor, which has IO mapped IOs. The
memory read and write signals, 𝑅𝐷 and W𝑅 are used in the processor with memory
mapped IOs.

Figure 4(b) shows the handshaking signals.

• An external input device to the device port makes a strobe request, STROBE, after it
is ready to send the byte and the system IO device sends the acknowledgement. PORT
READY when BRi (receiving buffer) is empty.

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• An external output receiving device sends the message ACKNOWLEDGE when the
IO device port ends the BUFFER FULL signal. The processor is sent the
INTERRUPT REQUEST message when BRo transmitting buffer is empty not full
(available for next write) or when the receiving buffer is full (available for next read).
This enables the processor to interrupt and retransmit next byte(s) in next cycle or
receive the byte(s) from input using the appropriate service routines for output or
input from the port, respectively.

• The following characteristics are taken into consideration when interfacing a device
port
1. A device port may have multi-byte data input buffers and data output buffers
Suppose there is an eight-byte buffer. Assuming that a device (as in the 80196
microcontroller) can generate three interrupts. one on receiving a byte, one on
receiving the fourth byte and one when the buffer is full, then the deadline for
servicing these interrupts increases up to eight times compared to the case
when there is a single byte register instead of buffer.
2. A port may have a DDR (Data Direction Register) (as in the 68HC11
microcontroller). This is an advantage since each bit of the port is now
programmable. It can be set as input or output. DDR programs the port bits.
3. Port LSTTL-driving capability and port-loading capability are important
characteristics. A port may be an OD (open drain) port. It has zero driving
capability unless the drain connects the positive supply voltage. If the given
port has OD gates, an appropriate pull-up resistance or transistor is connected
to each port pin to provide the driving capability. The drain or collector
connects to the supply voltage to provide the pull-up.
4. If a given port is quasi bi-directional (as in 80196), then the port pins have
limited driving capability. which suffices for a period of one or a few clock
cycles and drives a LSTTL. gate for that period. When this device port
connects to more than one LSTTL, then an appropriate pull-up circuit will be
required for the port pins.
5. There may be multiple or alternate functionality in the port pins; for example,
80196 input port pins Each pin of P2 has an alternative use as multi-channel
analog input facility for 8 analog inputs. Another example is 8051 two ports
PO and P2. These port bits also have an alternate function in that they bring
out when needed the internal multiplexed buses for the external program and
memories whenever the internal memory is insufficient. Each pin of P3 in
8051 has multiple uses. These a used during serial communication,
timer/counter signals, interrupt-signals, and 𝑅𝐷 and W𝑅 control signals for
external memories, 68HCI ports B and C are of 8 bits each and have
alternative uses for the port pins in it. One of the alternate functions is to bring
out the internal address and data buses, respectively.
6. A port may have provision for multiplexed output to connect to multiple
systems or units.
7. A port may have provision for demultiplexed inputs from multiple systems or
units.

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Parallel Port Interfacing with Switches and Keypad

• A 16 keys keypad has many applications. A mobile smart phone device has 16 keys
and four menu select up, down, left, right keys, Assume that an IO device has two
ports, A and C. The device has a processing element which functions as a keypad-
controlling device (controller).

Figure 5(a) Parallel input port A and a four bit output port C used for interfacing a set of 16
keys in a keypad and four menu select keys.

• Figure 5(a) shows how a set of switches or a keypad of 16 keys and four menu-select
keys can interface to the device. Four bits of an 8-bit input port A (A4 – A7) can be
used for the four menu select keys. Assume that the idle state logic state equals 1. The
16 keys can be considered as arranged in four rows and four columns. The other four
bits of A (A0 – A3) are inputs from sense lines from four rows, assume that the idle
state logic state is equal to 1. The four bits of output port C (C0 – C3) are output to
sense lines in four columns.
• The processing element in device activates for polling the output port C ten times
each second and sends C0 – C3=0000 after a wait it reads D0 – D7, and A4 – A7. The
processing element computes the code of the pressed key and generates a status signal
when a key is found pressed from the bit pattern found at A0-A3, the processing
element computes 7-bit ASCII code of the pressed key at that instance and can output
that code at D0 – D6. It also outputs D7=1 when a specific key is found pressed, else
D7 = 0. The processing element also processes the bounces when a key is pressed.
This takes care of bouncing effects. The processing element is thus functioning as a
keypad controller, as it is keypad specific.

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Parallel Port Interfacing with Encoders:

• Encoder is a device that measures angular or linear position of a rotating or moving
shaft. It has application in robots and industrial plants. A rotatory-angle encoder has
multiple tracks on a rotating disk. Each track has half of the segments transparent and
half opaque. A linear encoder has a multi-slotted plate. A set of n infrared (IR) LED
and phototransistor pairs generate n-bit inputs for a port. The encoder connects to
parallel port, as shown in Figure (b).

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Parallel Port Interfacing with Stepper Motor:

• A stepper-motor rotates by one step angle when its four coils are given currents in a
specific sequence and that sequence is altered. For example, assume that currents at
an instance equal +i, 0, 0, 0 in four coils X, X’, Y, Y’.
• The motor rotates by one step when the currents change to 0, +i, 0, 0. The sequences
at intervals of T are sequences changed as follows: 1000, 0100, 0010, 0001, 1000,
0100. [The bits in the nibble (set of 4 bits) rotate by right shift.] Here 1 corresponds to
+i. The motor thus rotates n step angles in interval of (n.T).
• They are changed to rotate the motor in the opposite direction, as follows: 0001,
00010, 0100, 1000, 0001, 0010, [The bits in the nibble (set of 4 bits) rotate by left
shift] Alternately, the coils are given the currents in the sequence of 1100, 0110, 0011,
1001, 1100, 0110, …., or 0011, 0110, 1100, 1001, 0011, 0110, The motor rotates
(n/2) steps in interval equals to (n.T/2). T is the period of clock pulses that drives the
motor by change - of coil currents to the next sequence.
• The coils connect to parallel port 4 output pins, as shown in Figure (c). Alternatively,
a processing element called stepper-motor deriver can be used.
• The driver is given two outputs from the port: clock pulses and a rotating direction bit
r. For example, if r=1, motor rotates clockwise and if r=0 then motor rotates anti
clockwise. The motor rotates as long as clock pulses are given at the output PC4-PC7.

Parallel Port Interfacing with LCD Controller:

• An LCD controller has a processing element that needs three control signals as inputs
and 8 input/output bits for parallel set of 8 IO bits. Eight-bit parallel output port B
pins PB0 -PB7, connect LCD controller, as shown in Figure 6(a). LCD controller also
connects to one-bit PC0 at an output port for RS (register select) signal.
• When RS is reset as 0, PB0 -PB7 communicates a control word to control register of
the LCD controller. When RS is set as 1. PB0 – PB7 , communicates data to the LCD
controller.
• The LCD controller also connects to a one-bit PC1 at output port for R/W
(read/write). PC1 is set to 1 when status register of LCD controller is read from PB0 -
PB7. PC1 is reset to 0 when writing into LCD controller the PB0 -PB7 bits.

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• The processing element generates all signals required for LCD displays. The LCD
controller is sent control words and data words for initialization and programming
PB0 -PB7 bits, PC0 and PC1 outputs for each word to LCD controller.
• The controller then has to be enabled by sending 1 at E pin. It connects to one bit PC 2
at output port for E (enable). There is an interval in which the controller may be in
disabled state. During this interval, it cannot accept instructions or data through the
output of control word or data port pins.
• For example, a control instruction is to clear display. The internal processing element
has to clear the bytes at all the N addresses in N characters LCD display. Assume that
in a typical LCD, it is 150 μs. When the first I is written at E, then 0 is written and a
150 μs delay program is called in-between; the E output creates a negative going
pulse at LCD controller. It disables sending of any control word or data for a period of
150 μs.
• LCD controller has M displayed character ROM addresses. M=128 for 128 ASCII
codes. For each distinct ASCII character, there is a 64-bit graphic. The LCD
controller has an internal CGRAM (character graphic RAM). For each ASCII
character, 8 bytes are sent from font table ROM to CGRAM address. CGRAM has N
addresses. N=64 when 64 characters are displayed at the LCD. An address changes by
incrementing or decrementing the cursor position to the previous or next address on
screen. By sending appropriate control words followed by data, the LCD controller is
programmed to display up to 64 characters on the screen.

Parallel Port Interfacing with Touchscreen:

• Touchscreen is an input device cum LCD display device. It is also interfaced through
IO port B functioning as data bus far display, control and status words to an LCD
display device controller.
• The interface uses an additional input port A for a byte, which corresponds to the
address of the position touched on the screen. A touchscreen is either resistive or
capacitive.
• On touching at a position on the screen, there is change in resistance or capacitance,
which depends on the touched position. A touch can be finger or stylus.
• The stylus is about one-fifth thinner than a pencil and about half of the length of the
pencil. The resistance or capacitance is a part of a bridge circuit that generates an
analog voltage. An 8-bit ADC is given an input from a bridge circuit and the 8-bit
ADC output connects to 8-bit input port A.

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• Eight-bit parallel IO port B pins PB0-PB7, E, 𝑅𝑆 and R/W and eight-bit parallel input
port A connect to touch screen circuit ports as shown in Figure 6(b). An interrupt
signal INTR is issued whenever the screen is touched.

SOPHISTICATED INTERFACING FEATURES IN DEVICE PORTS

• A device port may not be as simple as the one for a stepper motor port or for a serial
line UART. Nowadays, a complex embedded system has highly sophisticated IO
devices, for example, SDIO card IO devices with fast serialization and de-
serialization of data, fast transceiver, and real time video processing system.
• The following are the few sophisticated interfacing device and port features.
1. Let the operation voltage level expected for logic state 1=5 V (TTL or CMOS)
. The Schmitt trigger circuit has a property that when a transition from 0 to 1
occurs, only if the voltage level exceeds 2/3 of the 5 V level is there a
transition to 1. Similarly, when a transition from 1 to 0 occurs, only if the
voltage level lowers below 1/3 of the 5 V level is there a transition to 0.
Hence, the Schmitt trigger circuit eliminates noise as large as 2/3 of 5 V, or
3.3 V, when it is superimposed at an input line to the device. One great
advantage of the in-built Schmitt trigger circuit at the port is conditioning of
the signal by noise elimination. Otherwise, a device port input will need an
external chip for Schmill trigger-based noise elimination. Such a device is
used in transceivers for repeating systems, which are used in long distance
communication.
2. When a device port is waiting for instructions, power management can be
done at the gates of the device. Lately, a new technology called DataGate
(from Xilinx) has been developed for use at ports. DataGate is a
programmable ON/OFF switch for power management; DataGate makes it
possible to reduce power consumption by reducing unnecessary toggling of
inputs when these are not in use. The great advantage of an inbuilt DataGate-
like circuit at a device port is reduced power dissipation when the device port
is operated at fast speeds. Such a device is extremely useful in systems
connected to a common bus and there is a need to control unnecessary input
toggling. For example, in a bus interface unit, the input signals should activate
only when the input has to be passed to the circuit. As the number of bus
interfaces in the system grows, the demand to prevent needless switching of
input signals increases.
3. Earlier, port interfaces used to be either open drain CMOSS or TTLS or
RS232Cs. (i) Nowadays, a system may be required to operate at a voltage
lower than 5 V. Low Voltage TTL (LVITL) and Low Voltage CMOS
(LVCMOS) gates may be used at the device ports for 1.5 V IO. (ii) Nowadays,
a system may be required to operate using advanced IO standard interfaces.
Examples are High Speed Transreceiver Logic (HSTL) and Stub-series
Terminated Logic (SSTL) standards HSTL is used for high-speed operations;
SSTL is used when the buses are to be isolated from relatively large stubs.
4. A device connects to a system bus and also to IO bus when it is networked
with other devices. Device and bus-impedances during an IO should match.
Else, line reflections occur. Recent developments make it feasible to match
these dynamically. For example, a new technology, called XCITE (Xilinx
RaviKiran.H.N., Asst. Prof., Dept. of ECE,BGSIT 24
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Controlled Impedance Technology) can be used. The great advantage of an

inbuilt device for dynamically matched impedances is that when resistors are
replaced with digitally, dynamically controlled and matched impedances in the
devices, there are no line reflections and therefore no missing bits or bus
faults.
5. An IO device may consist of multiple gigabit (622 Mbps to 3.125 Gbps)
transceivers (MGTs). Special support circuitry is needed for this rate, Rocker
IOTM serial transreceivers are examples of circuits that provide support
circuitry at this rate.
6. A device for an IO may integrate a SerDes (serialization and de-serialization)
subunit. SerDes is a standard subunit in a device where the bytes placed at
transmit holding buffer serialize on transmission. and once the bits are
received these de-serialize and are placed at the receiver buffer. Once the
device SerDes subunit is configured, serialization and de-serialization is done
automatically without the use of the processor instructions. The great
advantage of the SerDes unit is that these operations are fast when compared
to operations without SerDes. A device for IO may integrate a DAA (direct
access arrangement using analog IOs along with one master and seven slave
CODECS) or McBSP (multi-channel buffered serial port with high speed
communication) subunit when serializing.
7. Recently, multiple IO standards have been developed for IO devices. A
support to the multiple IO standards may be needed in certain embedded
systems. A technology, Flexible Select IOTM -Ultra technology, supports over
20 single-ended and differential IO signalling standards. Advantages of
multiple standard device ports are obvious.
8. An IO device may integrate a digital Physical Coding Sublayer (PCS). Analog
audio and video signals can then be pulse code modulated (PCM) at the
sublayer. The PCS sublayer directly provides codes from analog inputs within
the device itself. The codes are then saved in the device data buffers. The
advantage of an inbuilt PCS at device port is that there is then no need of
external PCM coding. Besides, these operations are performed in the
background as well as fast. It improves the system's performance when there
are multimedia inputs at the device.
9. A device for IO may integrate an analog unit Physical Media Attachment
(PMA) for connecting direct inputs and outputs of voice, music, video and
images. The great advantage of inbuilt PMA is that the device directly
connects to physical media. PMA is needed for real-time processing of video
and audio inputs at the device.

WIRELESS DEVICES
• Wireless devices have become very common in recent years for serial transmission of
bits.
• Wireless devices use infrared (IF or radio frequencies after suitable modulation of
data bits. IrDA, Bluetooth, WiFi, 802.11 WLAN and ZigBee have become popular
protocols for wireless communication of data bits from a source to the receiver.
• An IR source communicates over a line of sight and the receiver phototransistor is
used for detecting infrared rays. Example of applications of IR communication
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includes handheld TV remote controllers and robotic systems. IR devices use IrDA
protocol.
• Radio frequencies communicate over short and long distances. The transmitter and
receiver use antenna to transmit and receive signals and modulator and demodulators
to carry the data bits using RP frequency Mobile GSM wireless devices use 890-915
MHz, 1710-1785 MHz, or 1850-1910 MHz bands Mobile CDMA wireless devices
use 2 GHz carrier frequencies. Bluetooth and ZigBee wireless device use 2.4 GHz or
900 MHz frequencies.
• The number of frequency bands is limited, while a large number of devices may need
to communicate. Therefore, time and frequency division multiplexing are used. An
innovative method is radio frequency hopping over a wider spectrum, as in Bluetooth
devices. The transmitted carrier frequencies hop among different channels at a given
hopping rate. The transmitter modulates the data bits as per protocol specifications.
• The receiver tunes to these hopped carrier frequencies at a given hopping rate and in
the same hopping sequence as the ones used by the transmitter. The receiver
demodulates and detects the data bits as per physical layer protocol used for
transmitting.

TIMER AND COUNTING DEVICES:

Most embedded systems need a timing device.

Timing Device
• A timer device is a device that counts the regular interval (δT) clock pulses at its
input. The counts are stored and incremented on cache pulse. It has output bits (in a
count register or at the output pins) for the period of counts.
• The counts multiplied by interval δT gives the time. The (counts-initial counts) x δT
interval gives the time interval between two instances when the present count bits are
read and the initial counts are read. It has an input pin (or a control bit in a control
register) for resetting to make all count bits = 0.
• It has an output pin (or a status bit in status register) for output when all count bits
equal 0 after reaching the maximum value, which also means timeout on the
overflow.

Counting Device
• A counting device is a device that counts the input for events that may occur at
irregular or regular intervals. The counts give the number of input events or pulses
since it was last read.
Blind Counting Synchronization
• A counting device may be a free running (blind counting) device with a prescalar for
the clock input pulses and for comparing the counts with the ones preloaded in a
compare register.
• The prescalar can be programmed as p=1,2,4,8,16, 32..., by programming a prescalar
register. It divides the input pulses as per the programmed value of p. It has an output
pin (or a status bit in the status register) for output when all count bits equal 0 after
reaching the maximum value, which also means after timeout or on overflow.

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• The counter overflows after px 2n x δT interval. It can have an input pin (or a control
bit in control register) for enabling an output when all count bits equal count
preloaded in the compare register. At that instance, a status bit or output pin also sets
in and an interrupt can occur for event of comparison equality. This device is useful
for the alarm or processor interrupts at preset instances or after preset intervals with
respect to another event from another source.
• The counting device may be the free running (blind counting) device with a prescalar
for the clock input pulses, for comparing the counts with the ones preloaded in a
compare register as well as for capturing counts on an input event. This device
functions are similar to the above, but there is an addition input pin for sensing an
event and for saving the counts at the instance of that event. At this instance, a status
bit can also set in and a processor interrupt can occur for the capture event.
• The above device is useful for alarm generation and processor interrupts at the preset
times as well as for noting the instances of occurrences of the events and processor
interrupts for requesting the processor to use the captured counts on the events. Alarm
generation can be synchronized with the input capture events. Writing counts into the
compare register does this. Counts in the register are set equal to capture register
counts plus additional counts, which define the interval after which an alarm is to be
generated.

Timer cum Counting Device:

• A timer cum counting device is a counting device that has two functions. (1) It counts
the input due to the events at irregular instances and (2) It counts the clock input
pulses at regular intervals. An input or a status bit in the timing device register
controls the mode as timer or counter. The counts give the number of input events or
pulses since it was last read. It has an output pin (or a status bit in status register) for
output when all count bits equal 0 after reaching the maximum value, which also
means timeout or overflow, interrupts to the processor.
• Table 5 lists twelve uses of a timer device. It also explains the meaning of each use.

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• At least one hardware timer device is a must in a system. It is used as a system clock.
Let number of system clock ticks needed before a system interrupt occurs equals
numTicks.
• The hardware timer gets the input from a clock-out signal from the processor and
activates the system clock tick as per the numTicks preset at the hardware timer on
each system clock tick, the user-mode task interrupts and the system take control.
• The system enables the privileged mode actions and the CPU context switches as per
the preset state of the system. The system control actions are performed by operating
system (software).
• Figure 7 shows hardware timer control bits (and signals) and status flags. Control bits
are as per the hardware signals and corresponding bits at control register. Control bits
(or signals) can be of nine types.
• These are: (i) Timer enable (to activate a timer). (ii) Timer start (to start counting at
each clock input). (iii) Timer stop (to stop counting) from the next clock input. (iv)
Presealing bits (to divide the clock-out frequency signal from the processor). (v) Up
count Enable (to enable counting up by incrementing the count value on cache clock
input) (vi) Down count Enable (to decrement on a clock input). (vii) Load enable (to
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enable loading of a value at a register into the timer). (viii) Timer-interrupt enable (to
enable interrupt servicing when the timer outs (overflows) and reaches count value
equals 0) (ix) Time out enable [to enable a signal when the timer overflows (reaches
count equals 0)] to another device.

Figure 7: Signals, Clock-inputs, Control bits and Status flags at registers or memory in a
hardware timer device.

• Status flag is as per the corresponding hardware signal time-out from the hardware
timer. This flag and signal set when the timer all bits (count value) reach to 0.
• Table 7 lists ten forms of the timers for the uses listed in Table 5. Software timer
(SWT) is an innovative concept.

TABLE 7: Ten forms of a TIMER

Sl.
Types
No.
1 Hardware internal timer.
2 Software timer (SWT).
3 User Software-controlled hardware timer.
4 RTOS controlled hardware timer. An RTOS can define the clock ticks per second of
a hardware timer at a system.
5 Timer with periodic time-out events. A timer may be programmable for auto-reload
after each time-out.
6 One shot timer. It triggers on even-input for activating it to running state from its idle
state. It is also used for enforcing time delays between two states or events.
7 Up count action Timer. It is a timer that increments on each count-input.
8 Down count action Timer. It is a timer that decrements on each count-input.
9 Timer with its over-flow status bit (flag), which auto-resets as soon as interrupt
service routine starts running.
10 Timer with over-flow flag, which does not auto reset.

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The system clock or any other hardware-timing device ticks and generates one interrupt or a
chain of interrupts at periodic intervals. This interval is as per the count-value set. Now, the
interrupt becomes a clock input to an SWT. This input is common to all the SWTs that are in
the list of activated SWT. Any number of SWTs can be made active put in a list of active
SWTs. Each SWT will set a status flag on its timeout (count-value reaching 0). Figure 7
shows the control bits and status bits in an SWT. SWT control bits are set as per the
application. There is no hardware input or output in an SWT. A flag sets when the SWT
count-value reaches 0 after reading the maximum. Table 8 lists all the variables of SWT. It
includes the control-bits and status flags. SWT thus has similar control variables and flags as
in the hardware timer or counter.
SWT actions are analogous to that of a hardware timer. While there is physical limit (1, 2 or 3
or 4) for the number of hardware timers in a system, SWT can be limited by the number of
interrupt vectors provided by the user. Processors (microcontrollers) also define the interrupt
vector addresses of two or four SWTs.

Figure 8: Control bits, status flags and variables of a software timer

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WATCHDOG TIMER:
• Watchdog timer is a timing device that can be set for a preset time interval, and an
event must occur during that interval else the device will generate the timeout signal.
• For example, we anticipate that a set of tasks must finish within 100ms. The watchdog
timer disables and stops in case the tasks finish within 100ms. The watchdog timer
generates interrupts after 100ms and executes a routine that runs because the tasks
failed to finish in the anticipated interval. A software task can also be programmed as
a watchdog timer. A micro-controller may also provide for the watchdog timer.
• The watchdog timer has a number of applications. One application in a mobile phone
is that the display is turned off in case no GUI interaction takes place within a
specified time. The interval is usually set at 15, 20. 25, or 30s in a mobile phone. This
saves power.
• An application in a temperature controller is that if a controller takes no action to
switch off the current within the preset time, the current is switched off and a warning
signal raised, indicating controller failure. Failure to switch off current may cause a
boiler in which water is heated to burst.
• A watchdog timer has a number of applications and is a timing device such that it is
set for a preset time interval and an event must occur during that interval else the
device will generate a timeout signal and interrupt for the failure to get that event in
the watched time interval.

REAL TIME CLOCK:

• Real time clock (RTC) is a clock that causes occurrences of regular interval interrupts
on its each tick (timeout).
• An interrupt service routine executes on each timeout (overflow) of this clock.
• This timing device once started never resets or is never reloaded with another value.
• Once it is set, it is not modified later.
• The RTC is used in a system to save the current time and date.
• The RTC is also used in a system to initiate return of control to the system (OS) after
the preset system clock periods.
• The interrupts from a real time clock are disabled or enabled by I bit in clock control
(CC) register. The interrupts from real time clocks are also locally masked by the 6th
bit, RTI in timer interrupt mask register2, TMASK2. This bit is set to unmask and
reset to mask the real time clock interrupts.
• If RTI and I bits permit the interrupt request for real time clock timeout then the
micro-controller fetches the lower and higher bytes of the interrupt servicing routine
address from the addresses OxFFF0 for higher byte) and 0xFFF1 (for lower byte).
• This is the vector address for real time clock interrupts in 68HC11. The interrupt
service routine must clear (0) the RTIF, which is interrupt flag for the real time clock
interrupts. The RTIF is a bit in timer interrupt flag register2, TFLG2. The TFLAG2 is
at address 0x0025.
• It is set by each interrupt from the real time clock interrupt and therefore it must be
cleared in order to enable next interrupt before returning from the corresponding
service routine and before the next real-time clock-interrupt occurs.

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• A real time clock (RTC) provides system clock and it has a number of applications. It
is a clock that generates system interrupts at preset intervals. An interrupt service
routine executes on each tick (timeout or overflow) of this clock. This timing device
once started is generally never reset or never reloaded to another value.

NETWORKED EMBEDDED SYSTEM:

• Each specific IO device may be connected to others using specific interfaces; for
example, an IO device connects and is interfaced to an LCD controller, keyboard
controller or print controller using specific interface.
• Bus communication simplifies the number of connections and provides a common
protocol for interconnecting different or same type of IO devices.
• Any device that is compatible with a system's IO bus can be added to the system
(assuming an appropriate device driver program is available), and a device that is
compatible with a particular IO bus can be integrated into any system that uses that
type of bus.
• This makes systems that use IO buses very flexible, as opposed to direct
interconnections between the processor and each IO device, and it allows system
support to many different IO devices (depending on the needs of its users), and it also
allows users to change the IO devices that are attached to system as their needs
change.
• The main disadvantage of an IO bus (and buses in general) is that each bus has a fixed
bandwidth that must be shared by all the devices, which connect to the bus.
• Even worse, electrical constraints (wire length and transmission line effects) cause
buses to have less bandwidth than using the same number of wires to connect just two
devices. Essentially, there is a trade-off between interface simplicity and bandwidth
sharing.
• IO devices communicate with the processor through an IO bus, which is separate from
the memory bus that the processor uses communicate with the memory system.
• Embedded systems connected internally on the same IC or systems at very short, short
and long distances, and can be networked using the followings types of IO buses, each
functioning according to specific protocols.
1. Using a serial IO bus allows a computer or controller or embedded system to
interface network with a wide range of IO devices without having to implement a
specific interface for each IO device. When the IO devices in the distributed
embedded systems are networked at long distances of 25 cm and above, all can
communicate through a common serial bus. A serial bus has very few lines.
2. Using a parallel IO bus allows a computer or controller or embedded system to
interface with a number of internal systems at very short distances without having
to implement a specific interface for each IO device.
3. Using the Internet or intranet, a computer, controller or embedded system's IO
device can interface globally and can network with other systems or computers
and a wide range of devices in the distributed systems.
4. Using a wireless protocol allows a handheld computer, controller or embedded
system IO device to interface and network with a number of handheld system IO
devices at short distances up to 100 m using a wireless personal area network
(WPAN) protocol, without having implement a specific wireless interface for
each IO device.
RaviKiran.H.N., Asst. Prof., Dept. of ECE,BGSIT 32
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SERIAL BUS COMMUNICATION PROTOCOLS:

Figure 9 A processor of embedded system connected to the system memory bus and
networked to other systems through a serial bus.

I2C BUS:

• Assume that there are number of device circuits in a number of processes in a plant.
One IC each for measuring temperatures and pressures. These ICs mutually network
through a common synchronous serial bus. I2C (inter IC connect) bus is popular bus
for these circuits.
• There are three I2C bus standards: Industrial 100 kbps I2C, 100 kbps SM I2C and 400
kbps I2C.
• The I2C bus has two lines that carry its signal--one line is for clock and one line is for
bidirectional data. There is a protocol for I2C bus.

Fig.(a) shows the signals during a transfer of a byte when using I2C bus.

• Each device has an address using which the data transfers take place.
• The master can address 127 other slaves at an instance.

RaviKiran.H.N., Asst. Prof., Dept. of ECE,BGSIT 33

 MODULE 2

• It has processing element functioning as a bus controller or micro-controller with I2C

bus interface circuit.
• Each slave can also optionally have an I2C bus controller and processing element.
• A number of masters can also connect to the bus.
• However, at any instance, there can be only one master, which is one that initiates a
data transfer on SDA (serial data) line and which transmits SCL (serial clock) pulses.
From the mater or slave, a data frame has fields beginning from start bit as per Table
9.
Table 9
Field and its length Explanation

First field of 1-bit It is start bit similar to one in a UART.

Second field of 7-bits It is called the address field. It defines the slave address being sent the
data frame (of many bytes) by the master.
Third field of 1 It defines whether a read or write cycle is in progress.
control bit
Fourth field of 1 Next bit defines whether the present data is an acknowledgment(from
control bit slave).
Fifth field of 8 bits It is used for IC device data bits.

Sixth field of 1-bit It is negative acknowledgment bit (NACK) from the master. If active,
then acknowledgment, after a transfer is needed from the slave, else
acknowledgment is expected from the slave.
Seventh field of 1-bit It is a stop bit like in UART.

Figure (b): Shows the format of the bits at I2C bus.

• The disadvantage this bus is the time taken by algorithm in the master hardware that
analyses the bits through I2C in case the slave hardware does not provide for the
hardware that support it.
• Some ICs support the protocol and same do not. In that case, interface circuit for those
ICs is also required. Also, there are open collector drivers at the master.
RaviKiran.H.N., Asst. Prof., Dept. of ECE,BGSIT 34
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• Therefore, a pull-up resistance of 2.2k or an active circuit for pulls up of line to logic.
I for on each line is essential.
• I2C is a serial bus for interconnecting ICs. It has a start bit and stop bit like in a
UART.
• It has seven fields for the start, 7-bit address, defining a read or write, defining a byte
as an acknowledging byte, data byte, NACK and end.

CAN Bus:

• Number of devices and controller are located and are distributed in a car. An
automobiles uses number of distributed embedded controllers, including those for
brakes, engine, electric power, lamps, inside temperature control, air conditioning,
gate, front dash board display, meter display panel and cruising control.
• Embedded controller must network through a bus. CAN (controller area network) is
standard bus in distributed network. It is mainly used in automotive electronics. It is
also used medical electronics and industrial plant controllers.

Figure 11 (a) Network during a transfer of data when using the CAN bus
(b) Format of the Bits at CAN Bus

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• The CAN bus [figure 11(a)] network has a serial line, which is bi-directional.
• CAN bus has multi master and multicast feature. A CAN device using CAN controller
receives or sends a bit at any instances by operating at the maximum rate of
1Mbps(bit-period = 1μs).
• It employs twisted pair connection of 120 ohm line independence at each controller
node. The pair can run up to a maximum length of 40m.
1. CAN serial line is pulled to logic level 1 by a resistor(active or passive) between
the line and +4.5v to +12.3v. Line is at logic 1 in its idle state, also called
recessive state.
2. Each node has a buffer gate between an input pin and a CAN serial line. A node
gets the input at any instance from the after sensing that instant when the line is
pulled down to 0. The latter is called dominant state.
3. Each node has current driver circuit output between pin and serial line. The node
sends a bit to line by pulling the line 0 by its driver for a bit period. An NPN
transistor is used current-driving transistor, the emitter of which also connects to
the line ground and collector connects to line. Using a driver (consisting of a
buffer inverter gate connected to the base of NPN transistor), the node can pull
the line to 0. Which is otherwise at logic 1 in its idle state. This lets other nodes
sense the input.
4. A node sends the data bits as data frame. Data frames always start with 1 and
always end with seven 0s. Between two data frames, there are minimum three
fields. Table 10 gives the details of each field in a CAN frame. Figure 1.(b) shows
the format of the bits in a CAN frame.
5. The CAN-bus line usually interconnects to a CAN controller between the line and
host node. [A host node is one that has controller for use as bus master.]The line
gives input and gets output and gets output during reception and transmission
using physical and data link layers at host node. The CAN controller has a
BIU(bus interface unit consisting of buffer and driver),protocol controller, status-
cum-control registers, receivers-buffer and message objects. These units connect
the host node through host interface circuit.
6. There is an arbitration method called CSMA/AMP(Carrier Sense Multiple Access
with Arbitration on Message Priority). A node stops transmitting on sensing a
dominant bit, which indicates that another node is transmitting.

Table 10: Each field in a CAN frame

Field and its length Functions

First field of 12bits This is arbitration field, which contains the packets of 11-bit
destination address and RTR bit(Packet means a set of bits sent on
the bus). RTR stands for ‘Remote Transmission Request’.
The addressed device is at destination address specified at 11-bit
subfield and RTR is defined on the basis of whether the data byte
being sent is a data for the device or a request to the device.
11 bit address identifies the devices to which data is being sent or
the request being made. When an RTR bit is at 1, it means this
RaviKiran.H.N., Asst. Prof., Dept. of ECE,BGSIT 36
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packet is for the device at destination address. If this bit is at

0(dominant state) it means this packet is a request for the data
from the device.
Second field of 6 bits It is control field. The first bit is identifier extension. The second
bit is always 1. The last 4 bits are code fro data length.
Third field of 0 to 64 bits Its length depends on the data length code in control field.

Fourth field (third if data It is CRC (Cyclic Redundancy Check) field with 15-bits CRC
plus 1-bit de3limiter bit. The receiver node uses it to detect errors,
field has no bit present) is of
if any, during the transmission.
16 bits

Fifth field of 2 bits First bit ‘ACK slot’. The sender sends it as 1 and the receiver,
which would send back 0 in this slot when it detects error in
reception. The sender, after sensing 0 in ACK slot, re-transmits
the data frame. The second bit is the ‘ACK delimiter’ bit. It
signals end of ACK field. If the transmitting node does not
receive any acknowledgment of data frame within a specified time
slot. It should re-transmit.
Sixth field of 7 bits This is the end-of-the-frame specification and has seven bits

USB Bus:

• Universal Serial Bus (USB) is a bus between host system and number of
interconnected peripheral devices. A maximum 127 devices can connect to a host.
• It provides a fast (up to 12 Mbps) and as well as a low speed (up to 1.5Mbps) serial
transmission and reception between host and serial devices.
• A USB host, which includes controller for function as bus master can connect flash
memory cards, pen-like memory devices, digital camera, printer, mice, PocketPC and
video games.
• There are three standards: USB 2.0 (low speed 1.5 Mbps 3 m channel along with a
high speed 12 Mbps, 25 m channel); USB 2.0(high speed 480 Mbps 25 meter
channel), and wireless USB(high speed 480 Mbps 3 m).
• USB protocol has this feature--- a USB device can be hot plugged (attached),
confused and used, reset, reconfigured and used; it can share bandwidth with other
devices, detached(while others are in operation) and reattached.
• USB host connects to devices or nodes using USB port-driving software and the host
controller connected to a root hub.
• USB bus cable has 4 wires, one for =5v, two for twisted pairs and one for ground.
There are termination impedances at each end that are as per the device speed.
Electromagnetic Interference (EMI)-shielded cable is used for 15Mbps USB devices.
• USB is a polled bus. The host controller circuit regularly polls the presence of a
device as scheduled by the software. Its sends a token packet. The token consists of
fields for type, direction, USB, device address, and device end-point number.

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• The device does the handshaking through a handshake packet, indicating successful or
unsuccessful transmission. A CRC field in a data packet enables transmission error
detection at the receiver.
• USB supports three types of pipes—
1 ‘Stream’ with no USB- defined protocol. It is used when the connection is
already established and the data flow starts.
2 ‘Default control’ for providing access.
3 ‘Message’ for the control functions of the device.
• The host configures each pipes for followings:
a. Data bandwidth to be used
b. Transfer service type and
c. Buffer sizes.
• Wireless USB is wireless extension of USB 2.0 and its operates at UWB (ultra wide
band) 3.1 to 10.6 Ghz frequencies. It is used for short-range personal area network
(high speed 480 Mbps, 3 m or 110 Mbps, 10 m channel).
USB is a serial bus that interconnects a system. It attaches and detaches a device from
the network. Its uses a root hub. Nodes containing the devices can be organized like tree
structure. It is mostly used in networking the IO receives like scanner in a computer
system. Wireless USB is used for remote connections without wires.

Fire Wire - IEEE 1394 Bus Standard:

• Digital video cameras, digital camcorders, digital video disk (DVD), set-top boxes,
and music systems multimedia peripherals, latest disk drives, and printers need a high
speed bus standard interface for communicating directly to a peripheral computer.
Firewire (IEEE 1394b) is a standard for 800 Mbps serial is synchronous data
transfers.
• A FireWire IEEE1394 port can operate at up to 400 Mbps and the latest machines
include FireWire ports that support IEEE 1394b which operate up to 800 Mbps.
• Since FireWire can transfer data at a guaranteed rate, it is also used in real time
devices, such as video device transfers.
• A single 1394 port can interface up to 63 external FireWire devices. It supports both
plug and play and hot plugging.
• It also provides self-powered and bus-powered support on the bus.
• FireWire is a high speed 800Mbps serial bus for interconnecting a system with
multimedia streaming devices and systems.

Advanced Serial High Speed Buses:

• Secure Digital Input Output, which is an advanced high speed serial bus for handheld
devices.
• An embedded system may need to connect multi gigabits per second (Gbps)
transceiver (transmit and receive) serial interfaces.
• Exemplary products are wireless LAN, Gigabit Ethernet, SONET (OC-48, OC-
192,OC_768).

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• The following are examples of the advanced bus protocols

o IEEE 802.3-2000 [1 Gbps bandwidth Gigabit Ethernet
MAC(MediaAccessContorl)] for 125 Mhz performance.
o IEEE P802.3oe draft 4.1[10 Gbps Ethernet MAC] for 156.25 Mhz dual
direction performance
o IEEE P802.3oe draft 4.1[12.5 Gbps EthernetMAC] for four channel 3.125
Gbps per channel transceiver performance]
o XAUI (10 Gigabit Attachment Unit)
o XSBI (10 Gigabit Serial Bus Interchange)
o SONET OC-48
o SONET OC-192
o SONET OC-768
o ATM OC-12/46/192

PARALLEL BUS DEVICE PROTOCOLS-PARALLEL COMMUNICATION

NETWORK USING ISA, PCI, PCI-X AND ADVANCED BUSES

• A computer system connects at high speed to other subsystems having a range of 10

devices at very short distances (<25 cm) using a parallel bus without having to
implement a specific interface for each IO device When the IO devices in the
distributed embedded subsystems are networked, all can communicate through a
common parallel bus. A parallel bus has a large number of lines as per the protocol.
Figures 12(a) and (b) show the processor of an embedded system A connected to
system memory bus and networked to other subsystems through a parallel bus PCI
using PCI bridge and AMBA-APB bridge, respectively.

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 MODULE 2

Fig. 12 (a) and (b) A processor of embedded system connected to system memory bus
and networked to other subsystems through a parallel bus using PCI and AMBA-APB bridges

• We need an interconnection bus within PC or embedded system to a number of PC-

based IO cards, systems and devices. This bus needs to be separated from system-bus
that connects the processor to memories.
• The system bus and interconnection bus operate at different levels of speeds.
Exemplary devices are display monitor, printer, character devices, network subsystems,
video card, modem card, hard disk controller, thin client, digital video capture card,
streaming displays, 10/100 Base T card and card using DEC 21040 PCI Ethernet LAN
controller.
• Each of these devices, which performs a specific function, may contain a processor and
drives by software. Each device has specific memory address-range, specific interrupt-
vectors (pre-assigned or auto configured) and device IO port addresses. A bus of
appropriate specifications and protocol interfaces these to host system or computer.

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 MODULE 2

• A switch, popularly called PCI bus interface, switches a processor communication with
the memory bus to PCI bus. In most systems, the processor has a single data bus that
connects to a switch module such as the PCI bridge found in many PC systems,
although some processors integrate the switch module onto the same integrated circuit
as the processor to reduce the number of chips required to build a system thereby
reducing the system cost.
• The switch communicates with the memory through memory bus and dedicated set of
wires that transfer data between these systems. A separate IO bus connects the switch to
IO devices. Separate memory and IO buses are used because the IO system is generally
designed for maximum flexibility, to allow as many different IO devices as possible to
interface to the computer, while the memory bus is designed to provide the maximum
possible bandwidth between the processor and memory system.
• Two old interconnection buses for communication between the host and a device are
ISA and EISA (Extended ISA). A new interconnection for the bus is either PCI or
PCI/X. [A variant of it is Compact PCI (cPCI).]

ISA Bus:

• ISA bus (used in IBM Standard Architecture) connects only to an embedded device that
has an 8086 or 80186 or 80286 processor, and in which the processor addressing and
IBM PC architecture addressing limitations and interrupt vector address assignments
are taken into account. There is no geographical addressing.
• The limitation for memory access by a system using the ISA bus of the original IBM
PC were as follows: ISA bus memory accesses can be in two ranges, 640 to 1 MB and
15 to 16 MB. The former range also overlaps with the range used by video boards and
BIOS. [Note: Linux OS does not support the second range for accessing directly a
device.]
• The IO port address limitations for devices are as follows: The 8086 to 80286 processor
has IO mapped IOs, not memory mapped IOS. Though the instruction set provides for
IO instructions for 64 kB IO addresses, the IBM PC configuration ignores the address
lines A₁0 to A₁5 and these are not decoded. Therefore, only 1024 IO port addresses are
available. A hexadecimal addressing scheme with three nibble addressing between 000
to 3FF only can be used for a device. The A10 to A15 bits are thus immaterial.
• The following are the addresses allocated in IBM Standard Architecture (ISA).
1. Addresses allocated are 0x000-0x00F for DMA chip 8237. The addresses for
other devices are as follows.

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 MODULE 2

2. 0x020-0x021 addresses allocated are for programmable interrupt controller 8255.

Hex 0x040-0x043 for timer 8253.
3. 0x060-0x063 for parallel port programmable parallel interface.
4. The hexa-decimal addresses 080-083, 0A0-0AF,0C0-0CF, 0E0-0EF allocated are
for components on the motherboard.
5. Reserved addresses from peripherals are hex 220-24F, 278-27F, 2F0-2F7, 3C0-
3CF and 3E0 to 3F0
6. The addresses allocated are hex 2F8-2FF and 3F8-3FF for IBM COM ports.
7. Addresses are hex. 320-32F and 3F0-3F7 for hard disk and floppy diskette,
respectively.
8. Only 32 addresses between 0x300 to 0x31F are available for prototype card; for
example, ADC card.
9. Addresses allocated are between hex 380-389 and 3A0-3A9 for synchronous
communication.
10. Synchronous Data Link Control (SDLC) addresses allocated are between hex.
380-38C.
11. Display monitor ports are within 380-38F (monochrome) and 3D0-3DF for
(colour and graphics). There is a limited availability of interrupt vectors in the
IBM PC 80x86 family. Only 256 vectors are available. Interrupt service functions
are now shared at software level: for example, SWT interrupts. Original ISA
specifications did not allow that.
• EISA bus is a 32-bit data and address-lines version of ISA, and devices (system using
this bus for IOs) are also supported. An EISA device driver first checks the EISA bus
availability on the hosting computer or system. It supports the sharing of interrupt
functions, SCI (Serial Communication Interface) controller and Ethernet devices. Unix
and Linux support the EISA bus-driven cards and devices.

PCI and PCI/X Buses

• Recently, the most used synchronous parallel bus in the computer system for
interfacing PC-based devices is PCI (Peripheral Component Interconnect). PCI
provides a superior throughput than EISA. It is almost platform independent, unlike the
ISA, which depended on the IBM PC platform, interrupt vectors, IO addresses and
memory allocations. Its clock rate is nearest to the submultiple of the system clock. PCI
provides three types of synchronous parallel interfaces. Its versions are 32/33 MHz,
64/66 MHz, PCI-X 64/100 MHz, PCI Super V2.3 264/528 MBps 3.3 V (on a 64-bit
bus), 132/264 (on a 32-bit bus) and PCI-X Super V1.01a for 800 MBps 64-bit bus 3.3
V.
• PCI bus has 32-bit data bus extendible to 64 bits. In addition, it has 32-bit addresses
extendible to 64 bits. Its protocol specifies the interaction between the different
RaviKiran.H.N., Asst. Prof., Dept. of ECE,BGSIT 42
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components of a computer. A pecification is version 2.1. Its synchronous/asynchronous

throughput is up to 132/ 528 MB/s [33 M x 4'66 M x 8 Byte/s]. It operates on 3.3 V
signals. A typical application is an exemplary PCI Card has a 16 MB Flash ROM with a
router gateway for a LAN.
• A PCI driver can access hardware automatically as well as by addresses assigned by the
programmer. The PCI feature of automatically detecting the interfacing systems and
assigning new addresses is important for coding a device driver. The PCI bus therefore
simplifies the addition and deletion (attachment and detachment) of the system
peripherals. A manufacturer registers a global number for PCI device or card, just as,
68HC11 or 80386 are globally registered numbers. A 16-bit register in PCI device
identifies this number to let that device auto-detected. Another 16-bit register is for a
device ID number. These two numbers allow the device to carry out auto-detection by
its host computer. Each device may use FIFO controller with FIFO buffer for maximum
throughput.
• A device or host identifies its address space by three identification numbers (i) IO port,
(ii) memory locations and (iii) configuration registers of total 256 B with a 4-byte
unique ID. Each PCI device has address space allocation of 256 bytes to access it by the
host computer. The unique feature of PCI bus is its configuration address space. A
uniquely assigned interrupt type (a number) handles an interrupt. For example, interrupt
type 3 has the interrupt vector address 0x0000C and four bytes at the address specify
the interrupt service routine address.
• Interrupt type can be between 0x00 and OxFF. A configuration register number 60
stores the one byte for the interrupt type n(pci). The PCI device or host when
interrupted handles the interrupt of type n(pci). Figure 13 shows 64-byte standard
configuration registers in a PCI device. Following are the abbreviations used in the
figure.
• VID: Vendor ID. DID: Device ID. RID: Revision ID. CR: Common Register. CC:
Class Code. SR: Status Register. CL: Cache Line. LT: Latency Timer. BIST: Base
Input Tick. HT: Header Type. BA: Base Address. CBCISB: Card Base CIS Pointer. SS:
Sub System. ExpROM: Expansion ROM. MIN_GNT: Minimum Guaranteed time.
MAX_GNT: Maximum Guaranteed Time.
• VID, DID, RID, CR, SR, and HT are compulsorily configured. The rest are optional.

Fig. 13: 64 bytes at standard device independent configuration registers in a PCI device or
host

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• A PCI controller must access one device at a time. Thus, all the devices within host
computer can share IO port addresses and memory locations but cannot share the
configuration registers. That means that a device cannot modify other configuration
registers but can access other device resources or share the work or assist the other
device. If there are reasons for it doing so, a PCI driver can change the default bootup
assignments on configuration transactions.
• A device can initialize at booting time. This helps in avoiding any address collision. A
PCI device on bootup disables its interrupt. Its address space is inaccessible and only
the configuration registers space remains accessible. PCI BIOS with the device
performs the configuration transactions and then memory and address spaces
automatically map to the address space in host computer.

ARM Bus:

• ARM processor interfaces the memory, external DRAM (dynamic RAM controller and
on-chip IO devices, which connect to 32-bit data and 32-bit address line at high speed
using AMBA (ARM Main Memory Bus Architecture)-AHB (ARM High Performance
Bus).
• Figure 12(b) shows AMBA-AHB and AMBA-APB bridges. The bridges interface the
memory and external-chip IO devices, which operate at low speed using AMBA-APB.
The maximum AHB bps bandwidth is sixteen times the ARM processor clock.
• A switch, popularly called the AMBA-APB bridge, switches ARM CPU
communication with the AMBA bus to APB bus. The ARM processor-based
microcontroller has a single data bus in AMBA-AHB that connects to the bridge, which
integrates the bridge onto the same integrated circuit as the processor to reduce the
number of chips required to build a system.
• This reduces the system cost. The bridge communicates with the memory through an
AMBA-AHB, a dedicated set of wires that transfer data between these two systems. A
separate APB IO bus connects the bridge to the IO devices. Separate AMBA-AHB and
APB IO buses are used because the IO system is generally designed for maximum
flexibility, to allow as many different 10 devices as possible to interface to the
computer, while the memory bus is designed to provide the maximum possible
bandwidth between the processor and the memory system.
• The APB can connect the I-C, touchscreen, SDIO, MMC (multimedia card), USB,
CAN and other required interfaces to an ARM microcontroller.

Advanced Parallel High Speed Buses

(ii) Many telecommunication, computer and embedded processor-based products need

parallel buses for system IOS. Three versions of PCI parallel
synchronous/asynchronous buses provide system-synchronous parallel interfaces.
These three versions may not have sufficiently high speed, ultra high speed and large
bandwidth that are required for system IOs, routers, LANs, switches and gateways,
SANS (Storage Area Networks), WANS (Wide Area Networks) and other products.
These do not meet the source-synchronous parallel interfacing requirements.
Bandwidth needs increase exponentially in the order of audio, graphics, video,
RaviKiran.H.N., Asst. Prof., Dept. of ECE,BGSIT 44
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interactive video and broadband IPv6 Internet. An embedded system may need to
connect IO system using gigabit parallel synchronous interfaces. The following are
advanced bus standard and proprietary protocols developed recently.
1. GMII (Gigabit Ethernet MAC Interchange Interface).
2. XGMI (10 Gigabit Ethernet MAC Interchange Interface)
3. CSIX-1. 6.6 Gbps 32-bit HSTL with 200 MHz performance.
4. RapidIo™M Interconnect Specification v1.1 at 8 Gbps with 500 MBps
performance or 250 MHz dual direction registering performance using 8-bit
LVDS (Low Voltage Data Bus).

INTERNET ENABLED SYSTEMS-NETWORK PROTOCOLS:

Fig:14 An enabled embedded system communication connected on the Internet

(iii) Figure 14 shows an internet-enabled embedded system communicating to other
systems on the internet-enabled embedded systems use html or MIME type files, TCP
or UDP transport layer protocol ,and are addressed by an IP address and use IP
protocol at network layer.
(iv) An IP address is 32 bits (four decimal numbers separated by dots in between) or 48
bits in IPv4 or IPv6 respectively.
(v) A system at one IP address 1 communicates with another system at another IP address
2 or 3 or … using the physical connections on the Internet and the routers.
(vi) Since the Internet is a global network, the system connects to remotely located as well
as short range located system. Network connectivity is through the layers.
(vii) Each layer has a protocol, which specifies the way in which the data or message
from the previous layer transfers to the next layer.
(viii) There are five layers in a TCP/IP network. They are the application, transport,
network, data-link and physical layers. The TCP/IP application layer protocol also
specifies presentation ways. Transport layer protocol specifies session establishment
and termination ways also.
(ix) Embedded system are Internet enabled by using TCP/IP protocols for networking to
Internet and assigning the IP addresses to each system.

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Hyper- Text Transfer Protocol (HTTP):

(x) An application layer protocol is as per the application.
(xi) This layer accepts the data, for example, in HTML or text format and puts the header
words as per the protocol and sends the application layer header plus data to the
transport layer.
(xii) A port number specifies the application in the header. Following are the
important application layer protocols that support TCP/IP networking.
1. NTP (Network Time Protocol) synchronizes system clocks on a network.
2. MIME enables attachment of multiple types of files. The examples are:
a. txt (text file).
b. doc (MSOFFICE Word document file).
c. gif (graphic image format file ),
d. jpg (jpg format image file), and
e. wav voice or music file.
3. HTTP (Port 80) enables Internet connectivity by Hyper-Text Transfer Protocol.
4. FTP (Port 21 for control. 20 for data) enables file transfer connectivity by File
Transfer Protocol.
TFTP (Port 69) for Trivial FTP . NFS (Network File System) is used for sharing
files on a network.
5. TELNET (Port 23) enables remote login to remote terminals by Terminal Access
Protocol.
6. SMTP (Port 25) enables e-mail transfer, store and forward by Simple Mail Transfer
Protocol.
7. PoP3 (Port 110) enables e-mail retrieval.
8. NNTP (Port 119) (Network News Transfer Protocol) is used for news transfer
port.
9. DNS (Port 53) for Domain Name Service.
10. SNMP (Port 53) Simple Network Management Protocol.
11. Boots and Bootpc (Ports 67 and 68)for Bootstrap Protocol (DHCP) Server and
Client, respectively.
12. DHCP (Dynamic Host Configuration Protocol) used for remote booting as well as
for configuring a system.
(xiii) A port-assigned number supports multiple logical connections using a socket.
Each socket has IP address and port number. A registered port number can be
between 0 and 1023. Registrations is done by IANA (Internet Assigned Number
Authority. Port number 0 means host itself. A user unregistered server can have Port
number above 5000.
(xiv) HTTP port 80 is an application layer protocol. The HTTP features are as follows:
1. HTTP is standard protocol for requesting for a URL (universal resource locator)
address, for example, : [Link] An URL defines a web page
resource, and is used for retrieving or sending web page file. The response from
web may be with or without applying a process. An HTTP client request an HTTP
server on the Internet and the server responds by sending a response.
2. HTTP is a stateless protocol. For an HTTP request, the protocol assumes a fresh
request. It means there is no session or sequence number field or no field that is
retained in the next exchange. This makes a current exchange by an HTTP request
independent of the previous exchanges. The later exchanges do not depend on the
current one. An e-commerce-like application needs a state management
mechanism. A Cookie is a text file created during a particular pair of exchanges of

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HTTP request and response. The creation is either at CGI or processing program or
script or at client (Browser). A prior exchange may then depend on this cookie. By
this mechanism, the stateless feature of HTTP is compensated. The cookie provides
a HTTP State management mechanism.
3. HTTP is a file transfer-like protocol for HTML (hyper text markup language) files.
This makes it easy to explore a web site URL. A request (from a client) is sent and
reply (response from a server)is received.
4. The HTTP protocol is very light (a small format) and thus speedy as compared to
other existing protocols. HTTP is able to transfer any type of data to a browser ( a
client) provided it is capable of handling that data.
5. Besides simplicity, another important feature of HTTP is its flexibility. Assume we
are surfing the web and our connection breaks (or user does so): then too we can
start surfing on the Net from just that point again. Being a stateless protocol. HTTP
does not keep track of the state as FTP does. Each time a connection establishes
between the web server and the client (browser), both these interpret this
connection as a new connection . Simplicity is a must because a web page has its
URL resources distributed over a number of servers.
6. HTTP protocol is based on the Object Oriented Programming System (OOPS).
Methods are applied to objects identified by URL. It means that as in the normal
case of Object Oriented Program , the various methods apply on an object.
7. From HTTP 1.0 and 1.1 version onwards, the following features have been
included:
(a) Multimedia file access is feasible due to provision or the MIME (Multipurpose
Internet Mail Extension) type file definition.
(b) From HTTP 1.1 version onwards, there are eight specified methods and
extension methods. An extension method is method added for a specific HTTP.
There can be none or one or several extension methods. The HTTP specific
methods are as follows. [Link] [Link] [Link] [Link] 5. PUT 6.
DELETE [Link] 8. OPTIONS. (Last four from 1.1). In earlier versions, GET
follows a space and then document name .Server returns the documents and
closes the connection. From 1.1, the POST method has permitted form
processing , as using it the client transmits the form data or other information to
the server. From 1.1, the server does not close the connection after response and
thus response can be processed before it is sent.
(c) A Provision of user authentication exists besides the basic authentication
introduced from HTTP 1.1 version onwards , Digest Access Authentication
prevents the transmission of username and password as HTML or text.
(d) A host header field adds to support those ports and virtual hosts that do not
accept or send IP packets. From HTTP 1.1 version onwards , An error report to
client when a HTTP request is without a host header field.
(e) From HTTP 1.1 version onwards , an absolute URL is acceptable to the server.
Earlier only proxy server accepted that.
(f) Status codes in the response.
(g) Caching of a resource is provided at server (and proxy).
(h) Byte range specification helps in large response in parts.
(i) Selection among various characteristics on retrieval by the client is feasible
when a server sends response to client request. For example, two characteristics,
language and encoding can be specified in server environment variables while
the client sends request header for retrieving a resource. The resource then

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retrieves in that language and with that encoding. The contents sent to client do
not change, only the way in which these are presented to the client change.
(j) Length specification helps in presentation in chunks.
8. An HTTP message header during a request from a client or during from server
consists of two parts (a)A start-line, none or several message- headers(fields) and
empty line, and (b) Body of message . HTTP specifies that request message to
consist of request message headers. HTTP also specifies that response message to
consist of response message headers.
9. HTTP provides for entity headers. These contain information about entity body
contained in the message, or in case body is not present then information about the
entity, not its body. For example, information of content length in bytes.
10. HTTP interaction scheme is that a client requests server directly or through proxy
or a gateway. An HTTP message is therefore either request or response. The
format of the messages called RFC 822, specifies ways of sending text messages
on the Internet. The message during request from client or during response from
server consists of two parts. (a) Start-line , none or several message-
headers(fields)plus empty line, and (b) Body of the message. The start line is either
a ‘request-line’ or ‘status-line’ for request-or response-message, respectively.

Transport Control Protocol (TCP):

(xv) TCP (Transport control protocol) is a protocol used in transport layer. This layer
accepts messages from the upper layer on transmission by application or session
layer. This layer also accepts a data system network layer at receiving end.
(xvi) Before communicating a message to the next layer, it the next network layer, it
may add a header. The message may communicate in parts of segments or fragments
the header generally has the additional bits for source and destination addresses also
there are bits in it for the sequence and acknowledge management, flow and error
controls, etc.
(xvii) There are bits for the offset, window, flags, checksum, urgent pointer, option
and for padding also. TCP supports the point to point networking mode.
(xviii) TCP specifies a format of byte streams all the transport layer of the TCP/IP
suite . TCP is used for a full duplex acknowledgment flow.
(xix) Its format has a TCP header of five plus (n–5)words for options and padding
and data of maximum words then 1≥214 -n ,here n>-5. Here n≥5, n equals the number
of words in the header and it’s called data offset, which means the number of words
after whichdata bits start in the stream.
(xx) If n>5, it means there exists words for options and padding refers to bits used
for filling the remaining part of the available field.

User Datagram Protocol (UDP):

• TCP/IP also supports at the transport layer a simpler protocol than TCP.
• When a message is connectionless and stateless, then the transport layer protocol in the
protocol in the TCP/IP suite is User Datagram Protocol (UDP).
• UDP supports the broadcast networking mode.
• An example is application for communicating header before a data stream. The header
specifies the bits for source and destination ports, total length of message including
header and check sum (optional). During reception, this message to upper layer flows

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after deleting the header bits from the received transport layer header. Header bits add
at the transmitting time in the application or session layer bytes.

Internet Protocol (IP):

• All Internet enabled devices communicate using Internet Protocol (IP).
• The transport layer data transmits on the network, divides into the packets at the
network layer. Each packet transmits through a chain of routers on the Internet.
• A packet is minimum unit of data that transmits on the Internet through routers. Several
packets forming a source can reach a destination using different routes and can have
different delays.
• The packet consists of IP header plus data or IP header plus routing protocol along with
the routing messages. The packet has a maximum of 216 bytes (214 words, 1
word=32bits=4bytes).
• Network routing is as per standard IPv4 (version 4) or IPv6(version 6).
• IPv6 is a broadband protocol.
• Table 11 lists in IPv4 protocol header.
Table 11 Various fields at IPv4 header for routing the packets through routers to
Destination node

Field at the IP header Explanation

Version IP version bits are 0100 for IPv4(presently in wide use) and 0100 for IP ng
IP next generation for broad band internet)
Precedence Precedence type is between 8th to 10th bit. Bits 111 specifies highest
precedence, for example , for streaming audio or video 000 specifies
common data.
Service Service type is between 11th to 15th bit.
QoS (quality of service ) Bits are for QoS (quality of service) specification in terms of security , speed,
delays and cost desired or must be achieved.
Fragment ID Each messages may have many pockets fragmented through the routers . each
fragment must thus provide a unique ID for identification for assembly at the
receiver end.
Flags Flags indicate whether present fragment through the routers . each fragment
must thus provide a unique ID for identification for re-assembly at the
receiver end. Flags indicate whether more fragments will follow . Let
q=number of header words (1 Word =32-bit). Flag bit 1 indicates whether
more fragments of the packet will succeed this fragment . flag bit 2 identifies
it as a test fragment or not . flag bit 3 checks whether the fragmentation is
permitted or not.
Checksum Header checksum checks errors in header transmission.
Time -to-live Time to live indicate number of retransmission hops permitted in case of
failed delivery.
Protocol Type Each messages may have many pockets fragmented through the routers . each
fragment must thus provide a unique ID for identification for assembly at the
receiver end.
Flags indicate whether present fragment through the routers, each fragment
must thus provide a unique ID for identification for re-assembly at the
receiver end. Flags indicate whether more fragments will follow. Let

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q=number of header words (1 Word =32-bit). Flag bit 1 indicates whether

more fragments of the packet will succeed this fragment . flag bit 2 identifies
it as a test fragment or not . flag bit 3 checks whether the fragmentation is
permitted or not.
Header checksum checks errors in header transmission.
Time to live indicates number of retransmission hops permitted in case of
failed delivery.
Type indicates whether the packet is transmitting a UDP byte stream or a
TCP stream from transport layer. The important routing protocols that
encapsulate after the IP header in an IP packet are:
IGMP(Internet Group Management Protocol). IGMP is a protocol to manage
data transmission between select host groups. Several hosts join a group.
Group multicasts use routers that uses the IGMP.
ICMP (Internet Control Management Protocol) is a protocol to control
routing between networked hosts.
ICMP data byte stream is inside an IP packet (datagram). Its format is as
follows. First 20 bytes minimum are the IP header. Next follows the fields of
1-byte each for Type and code, Successively. Next two bytes are for
Checksum. Then follows the ICMP messages the format and length of which
is variable.
Interior routing protocols, for example, the RIP(Routing Information
Protocol) and OSPF (Open Shortest Path First) protocol.
Inter-Domain (exterior routing) protocols, for example, EGP (Exterior
Gateway Protocol), BGP (Border Gateway Protocol) and GGP(Gateway to
Gateway Protocol).
Header length The IP header length (data offset)p<214 -q. Here q>5. q equals the number of
(data-offset) words in the header and is called the data offset [Number of words after
which data bits start in the stream.]
Source and Destination IP Source and destination IP addresses IP addresses If q>5, there exist words
addresses option for options. and padding. Padding refers to bits that are used for filling the
remaining part of the available field. For example, option 4 will mean put
time stamp at all the stoppages of the packet during transit to destination
through routers. Time stamping enables packet delay measurements to
calculate Network Performance Quality.

Ethernet:
(ii) The inventor of Ethernet LAN is Robert Metcalfe. At present, about one third of the
LANs in the world are the Ethernet LANs, and in each frame, there is a header like in
a packet. In Ethernet LAN standard is IEEE 802.2(ISO 8802.2).
(iii) It is a protocol for local network of computers, workstation and devices. LAN is used
for sharing local computers, systems and local resources such as printers, hard disk
space, software and data. Table below gives the features of the Ethernet LAN devices.
(iv) Data for transmission fragments into the frames. Each frame has a header. Firstly, the
header has eight bytes, which defines a preamble.
(v) The preamble indicates the start of a frame and is used for synchronization. Then the
header has six bytes of destination address. Six bytes of source address the follows the
destination address. The there are six bytes. These are for the type field.

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(vi) These are meaningful only for the higher network layers and the length definition.
The minimum 72 bytes and maximum 1500 bytes of data follow the length definition.
Lastly, there are 4 bytes for CRC check for the frame sequence check.

Ethernet LAN features:

Feature Ethernet LAN

Topology and transmission mode Bus
Speed 10 Mbps, 100Mbps (unshielded and shielded wire) and 4 Gbps
(in twisted pair wiring mode)
Broadcast Medium Passive, Wired connections-based. Frame format like the IEEE
8023.

SNMP (Simple Network

Yes
Management Protocol)
System Open (therefore allows equipment of different specifications)
Operation Each one connected to a common communication channel in
the network. It listens and if the channel is idle then transmits.
If not idle. waits and tries again. Multi access is like in a packet
switched network

Control Passive, connection-based.

Address Resolution Protocol Yes. There is a media access control (MAC) address for
(ARP) for resolving 32bits transmitting and forwarding frames the same LAN. We can also
use multicast addressing to send frames to all or few select
internet protocol addresses with types or Ethernet devices
the 48-bit destination host media
address.

Connectivity to Internet and Intranet Yes. Outside a LAN the internet Protocol addresses are sent.

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WIRELESS AND MOBILE SYSTEM PROTOCOLS

Infrared Data Association (IrDA):

(vii) IrDA (Infrared Data Association) recommends a protocol suite as standard.

(viii) It supports data transfer rates of up to 4 Mbps.
(ix) It supports bi-directional serial communication over viewing angle between ± 150
and distance of nearly 1 m.
(x) At 5 m, the IR transfer data can be up to data transfer rates of 75 kbps. There
should be no obstructions or wall in between the source and receiver.
(xi) Figure (a) shows a handheld device connected to other computer through using
IrDA protocol.
(xii) Protocol processing hardware device and the protocol software embed
in thesystem, which support line of sight communication using infrared.
(xiii) IrDA supports 5 levels of communication.
o Level l is minimum required communication
o Level 2 is access based communication
o Level 3 is index-based communication
o Level 4 is synchronized communication
o Level 5 is Sync ML (synchronization markup language) communication.
(xiv) IrDA is used. in mobile phones, digital cameras keyboard, mouse, printers to
communicate to laptop computer and for data and pictures download and
synchronization IrDA is also used for control TV, air conditioning, LCD projector,
VCD devices from a distance.
(xv) IrDA supports several protocols at three layers,
(xvi) Lower layer is physical layer 1.0 or 1.1. It supports data transfer rates of 9.6 kbps to
kbps and 115.2 kbps to 4 Mbps in IrDA physical layer 1.0 and 1.1, respectively.
(xvii) Intermediate layer is data-link layer. At data link layer, it specifies IrLMP (IR
link management protocol). Another upper sub layer and IrLAP (IR link access
protocol) lower sublayer. An IRI—AP is HDLC synchronous communication.
(xviii) An IrDA upper layer protocol is Tiny TP [transport protocol]. Another upper
layer protocol is IRLMIAS (IR Link Management Information Access Service
Protocol).
(xix) The upper layer protocol for the session layer is IrLAN, IrBus, IrMC. IrTran,
IrOBEX (object Exchange) and standard serial port emulator protocol IrCOMM (IR
communication). IR Bus provides serial bus access to game joysticks, mice and
keyboard.
(xx) IrDA protocol overhead is between 2% to 50% of Bluetooth device overhead.
(xxi) The communication setup latency is just few milliseconds.
(xxii) The requirement of the line of sight and unobstructed communication is the
limitation.

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Bluetooth:

(xxiii) Bluetooth hardware is connected to embedded system buses and Bluetooth

software embeds in the system to support WPAN using Bluetooth wireless protocol.
(xxiv) Figure (b) shows a handheld device connected Other computers through
wireless protocol using Bluetooth.
(xxv) A large number of CD players and mobile devices are Bluetooth-enabled.
Bluetooth is also used for handsfree listening of Bluetooth-enabled iPod or CD
music player ormobile phone by using Bluetooth-enabled era buds.
(xxvi) Bluetooth is an IEEE standard 802.15.1 protocol.
(xxvii) The physical layer radio communicates at carrier frequencies ill 2.4 GHz
band WithFHSS (frequency hopping spread spectrum).
(xxviii) Data transfer is between two devices or between a device and multiple devices.
(xxix) It supports range up to 10 m low power and up to 100 m high power.
(xxx) Range depends on radio interface at physical layer.
o Bluetooth 1.x data transfer rate supported is 1 Mbps.
o Bluetooth 2.0 enhanced maximum data rate of 3.0 Mbps over 100 m.
(xxxi) Bluetooth protocol supports automatic self-discovery and self-organization of
network in number of devices, Bluetooth device self discovers nearby devices (<10m)
and they synchronize and form a WPAN (wireless personal area network).
(xxxii) Bluetooth protocol supports power control so that the devices communicate at
minimum required power level.
(xxxiii) The physical layer has three sublayers: radio, baseband and link manager or
host controller interface.
(xxxiv) There are two types of links: best effort traffic links and real-time voice traffic links.
(xxxv) The real -time traffic uses reserved bandwidth. A packet is of about 350 bytes.
(xxxvi) The link manager sublayer manages the master and slave link. It specifies data
encryption and device authentication handling, and formation of device pairs for
Bluetooth communication.
(xxxvii) The Host Controller Interface (HCI) interface is a hardware abstraction
sublayer. It is used in place of the link manager sublayer. It provides for emulation of
serial port, for example, 3-wire UART emulation. A Bluetooth device can thus
interface to the COM port of a computer.
(xxxviii) Its communication latency is 3s. It has large protocol stack overhead of 250 kB.

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802.11:
(xxxix) Wireless LAN uses IEEE standards 802.11a to 802.11g. Data transfer rates are
1 and2 Mbps.
(xl) The 802.11b is called wireless fidelity (Wi-Fi). 802.11b support data rates of 5.5
Mbps by mapping 4 bits and 11 Mbps mapping 8 bits simultaneously during
modulation.
(xli) A given set of the LAN-station access points network together and the set is
called extended service set (ESS).
(xlii) There are two types of wireless service sets.
(i) One service set has one wireless Station. Which communicates to an access
point, also called a hotspot. The service set is called basic service set (BSS).
(ii) The other service set has several stations. It is called independent basic service
set (IBSS). It has no access point. It does not connect to the distribution
system. It may have multiple stations, Which also cannot communicate among
themselves. IBSS supports ad-hoc network.
(xliii) 802. 11 provides specifications for physical layer and data link layers.
(xliv) The data link layer specifies a MAC layer. The MAC layer uses carrier sense
multiple access and collision avoidance (CSMA/CA) protocol. A station listening to
the presence of the carrier during a time interval is called distributed inter-frame
spacing (DIES) interval. If the carrier is not sensed (detected) during DIFS, then the
station backs of for a time interval to avoid call list and retries after that interval.
(xlv) A receiver always acknowledges within a short interframe spacing (SIFS).
(xlvi) Acknowledgment is made after Successful CRC (cyclic redundancy check),
there is no acknowledgement within SIFS, then the transmitter retransmits and up to
7retransmission attempts are made.
(xlvii) There is a packet called request to send (RTS), which is first sent. If the Other
end responses by the packet call clear to send (CTS), then the data is transmitted.
MAC layer specifies power management, handover and registration of roaming
mobile nodewithin the backbone network at a new BSS within the ESS.
(xlviii) There are three communication methods at the physical layer. WLAN can use
FHSS or DSSS or Infrared 250 ns pulses.
(xlix) The physical layer has two sublayers.
(l) 802.11b has three sublayers: one is Physical Medium Dependent (PMD) protocol
which specifies the modulation and coding methods; the second is the Physical Layer
Convergence Protocol (PLCP) which specifies the header and payload for
transmission.
(li) It specifies the sensing of the carrier at receiver and how packet formation takes place
at the transmitter and packets assemble at the receiver- It specifies ways to converge
MAC (Medium Access Control) to PMI) at transmitter and separate MAC (Medium
Access Control) from PMD at the receiver.
(lii)An additional sub layer in 802.11b Specifies Complementary Code Keying (CCK).

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ZigBee:

(liii) ZigBee is an IEEE standard 802.15.4 protocol. The physical layer radio operates at
2.4 GHz band carrier frequencies with DSSS (direct sequence spread spectrum),
supports range up to 10 m.
(liv) Data transfer rate supported is 250 kbps, it supports sixteen channels, Figure
15(c) shows a handheld device
(lv) Connected to other devices through wireless protocol using ZigBee.
(lvi) The ZigBee network is self-organizing and supports peer-to-peer and mesh
networks.
(lvii) ZigBee protocol supports large sensors, lighting devices, air conditioning,
industrial controller and other devices for home and office automation and their
remote controland formation of WPAN (wireless personal area network).
(lviii) ZigBee network has a ZigBee router, end devices and coordinator.
(lix) ZigBee router transfers packets from a neighbouring source to a nearby node
in the path to destination, The coordinator connects one ZigBee network with
another, connects to WLAN or cellular network. ZigBee end devices are transceivers
of data.
(lx) Its communication latency is 30ms. Protocol stack overhead is 28 kB.

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