Circuit Electronics

Chapter 6
Sequential Logic

Dr. M. Imran Shahzad

 6-1 Introduction

Asynchronous
Inputs Outputs
Combinational
Circuit
Memory
Elements

Synchronous
Inputs Outputs
Combinational
Circuit
Flip-flops
Clock

Applied Physics, FUUAST, Islamabad 1

 6-2 Flip-Flops and Latches

SR Latch
S R Q0 Q Q’
Initial Value 0 0 0 0 1 Q = Q0

R
0 0
Q
1

0 Q
S 1
0
A B (A+B)’
0 0 1
0 1 0
1 0 0
1 1 0
Applied Physics, FUUAST, Islamabad 2
 Latches

SR Latch
S R Q0 Q Q’
0 0 0 0 1 Q = Q0
0 0 1 1 0 Q = Q0

R
0 1
Q
0

1 Q
S 0
0
A B (A+B)’
0 0 1
0 1 0
1 0 0
1 1 0
Applied Physics, FUUAST, Islamabad 3
 Latches

SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1 Q=0
R
1 0
Q
1

0 Q
S 1
0
A B (A+B)’
0 0 1
0 1 0
1 0 0
1 1 0
Applied Physics, FUUAST, Islamabad 4
 Latches

SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1 Q=0
R
1 1 0 1 1 0 1 Q=0
Q
1

0 Q
S 0
0
A B (A+B)’
0 0 1
0 1 0
1 0 0
1 1 0
Applied Physics, FUUAST, Islamabad 5
 Latches

SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R
0 0 0 1 1 0 1
Q=0
Q 1 0 0 1 0 Q=1
0

1 Q
S 1
1
A B (A+B)’
0 0 1
0 1 0
1 0 0
1 1 0
Applied Physics, FUUAST, Islamabad 6
 Latches

SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R
0 1 0 1 1 0 1
Q=0
Q 1 0 0 1 0 Q=1
0 1 0
1 0 1 Q=1

1 Q
S 0
1
A B (A+B)’
0 0 1
0 1 0
1 0 0
1 1 0
Applied Physics, FUUAST, Islamabad 7
 Latches

SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R
1 0 0 1 1 0 1
Q=0
Q 1 0 0 1 0
Q=1
1 0 1 1 0
1 1 0 0 0 Q = Q’

S Q
1 10
A B (A+B)’
0 0 1
0 1 0
1 0 0
1 1 0
Applied Physics, FUUAST, Islamabad 8
 Latches

SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
R
1 10 0 1 1 0 1
Q=0
Q 1 0 0 1 0
Q=1
1 0 1 1 0
1 1 0 0 0 Q = Q’
1 1 1 0 0 Q = Q’
S Q
1 0
A B (A+B)’
0 0 1
0 1 0
1 0 0
1 1 0
Applied Physics, FUUAST, Islamabad 9
 Latches

SR Latch
0 1
R Q S R Q Q’
0 1 0 1 0 (Set State)

1 Q
S 0
1
A B (A+B)’
0 0 1
0 1 0
1 0 0
1 1 0
Applied Physics, FUUAST, Islamabad 10
 Latches

SR Latch
0 1
R Q S R Q Q’
0 1 0 1 0 (Set State)
0 0 1 0 (After S = 1, R = 0)

1 Q
S 0
0
A B (A+B)’
0 0 1
0 1 0
1 0 0
1 1 0
Applied Physics, FUUAST, Islamabad 11
 Latches

SR Latch
1 0
R Q S R Q Q’
1 1 0 1 0 (Set State)
0 0 1 0 (After S = 1, R = 0)
0 1 0 1 (Reset State)
0 Q
S 1
0
A B (A+B)’
0 0 1
0 1 0
1 0 0
1 1 0
Applied Physics, FUUAST, Islamabad 12
 Latches

SR Latch
0 0
R Q S R Q Q’
1 1 0 1 0 (Set State)
0 0 1 0 (After S = 1, R = 0)
0 1 0 1 (Reset State)
0 Q 0 0 0 1 (After S = 0, R = 1)
S 1
0
A B (A+B)’
0 0 1
0 1 0
1 0 0
1 1 0
Applied Physics, FUUAST, Islamabad 13
 Latches

SR Latch
1 0
R Q S R Q Q’
0 1 0 1 0 (Set State)
0 0 1 0 (After S = 1, R = 0)
0 1 0 1 (Reset State)
0 Q 0 0 0 1 (After S = 0, R = 1)
S 0 1 1 0 0 (Invalid State)
1
A B (A+B)’
0 0 1
0 1 0
1 0 0
1 1 0
Applied Physics, FUUAST, Islamabad 14
 Latches

Active High SR Latch

R S R Q
Q 0 0 Q0 No change
0 1 0 Reset
1 0 1 Set
S Q
1 1 Q = Q’ = 0 Invalid State

Active Low SR Latch

S R Q
S Q 0 0 Q = Q’ = 1 Invalid State
0 1 1 Set
1 0 0 Reset
R Q
1 1 Q0 No change
Applied Physics, FUUAST, Islamabad 15
 Clocked RS Latch

SR Latch with Clock Input

R R S
S
Q Q
CLK CLK

S R Q
Q R
S

CLK S R Q
0 x x Q0 No change
1 0 0 Q0 No change
1 0 1 0 Reset
1 1 0 1 Set
1 1 1 Q = Q’ Invalid
Applied Physics, FUUAST, Islamabad 16
 SR Flip-Flop Characteristic Equation

Analysis / Derivation
S R Q(t) Q(t+1)
0 0 0 0 No change
S Q 0 0 1 1
0 1 0 Reset
0 1 1
R Q
1 0 0 Set
1 0 1
1 1 0 Toggle
1 1 1

Applied Physics, FUUAST, Islamabad 17

 SR Flip-Flop Characteristic Equation

Analysis / Derivation
S R Q(t) Q(t+1)
0 0 0 0 No change
S Q 0 0 1 1
0 1 0 0 Reset
0 1 1 0
R Q
1 0 0 Set
1 0 1
1 1 0 Toggle
1 1 1

Applied Physics, FUUAST, Islamabad 18

 SR Flip-Flop Characteristic Equation

Analysis / Derivation
S R Q(t) Q(t+1)
0 0 0 0 No change
S Q 0 0 1 1
0 1 0 0 Reset
0 1 1 0
R Q
1 0 0 1 Set
1 0 1 1
1 1 0 Toggle
1 1 1

Applied Physics, FUUAST, Islamabad 19

 SR Flip-Flop Characteristic Equation

Analysis / Derivation
S R Q(t) Q(t+1)
0 0 0 0 No change
S Q 0 0 1 1
0 1 0 0 Reset
0 1 1 0
R Q
1 0 0 1 Set
1 0 1 1
RQ 00 01 11R 10
S 1 1 0 X Invalid
0 0 1 0 0 1 1 1 X
1
S 1 1 X X
Q Q(t+1) = S + R’Q
Applied Physics, FUUAST, Islamabad 20
 Clocked RS Latch

D Latch (D = Data) Timing Diagram

S
C
D
Q
C D
R Q
Q

D Q C D Q Output may
0 x Q0 No change change
Q 1 0 0 Reset
1 1 1 Set Q(t+1) = D
Graphical Symbol
Applied Physics, FUUAST, Islamabad 21
 Clocked RS Latch

D Latch (D = Data) Timing Diagram

S
C
D
Q
C D
R Q
Q

C D Q Output may
D Q change
0 x Q0 No change
Q 1 0 0 Reset
1 1 1 Set Q(t+1) = D
Graphical Symbol
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 Latches and Flip-Flops

Clocked latches are level-triggered

 Flip-Flops are edge-triggered

CLK Positive Edge

CLK Negative Edge

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 JK Flip-Flop
 JK Flip-Flop

R
K Q
CLK
S Q
J J Q

K Q
Q(t+1) = JQ’ + K’Q
Characteristic Equation Graphical Symbol

Applied Physics, FUUAST, Islamabad 24

 JK Flip-Flop Characteristic Equation

Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0 No change
J Q 0 0 1 1
0 1 0 Reset
0 1 1
K Q
1 0 0 Set
1 0 1
1 1 0 Toggle
1 1 1

Applied Physics, FUUAST, Islamabad 25

 JK Flip-Flop Characteristic Equation

Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0 No change
J Q 0 0 1 1
0 1 0 0 Reset
0 1 1 0
K Q
1 0 0 Set
1 0 1
1 1 0 Toggle
1 1 1

Applied Physics, FUUAST, Islamabad 26

 JK Flip-Flop Characteristic Equation

Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0 No change
J Q 0 0 1 1
0 1 0 0 Reset
0 1 1 0
K Q
1 0 0 1 Set
1 0 1 1
1 1 0 Toggle
1 1 1

Applied Physics, FUUAST, Islamabad 27

 JK Flip-Flop Characteristic Equation

Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0 No change
J Q 0 0 1 1
0 1 0 0 Reset
0 1 1 0
K Q
1 0 0 1 Set
1 0 1 1
KQ 00 01 11 10
J K 1 1 0 1 Toggle
0 0 1 0 0 1 1 1 0
J 1 1 0 1
1
Q Q(t+1) = JQ’ + K’Q
Applied Physics, FUUAST, Islamabad 28
 JK Flip-Flop

JK Flip-Flop Constructed with D Flip-Flop

J
D Q Q
K
CLK Q Q

J Q
D = JQ’ + K’Q
K Q
Applied Physics, FUUAST, Islamabad 29
 T Flip-Flop
 T Flip-Flop Constructed with JK and D Flip-Flops
R
T T J Q
T D Q Q
K Q Q
CLK
S T QQ
Characteristic Equation
Q
JK FF : Q(t+1) = JQ’ + K’Q
T FF : Q(t+1) = TQ’ + T’Q = T  Q Graphical Symbol

Applied Physics, FUUAST, Islamabad 30

 T Flip-Flop Characteristic Equation
 JK Flip-Flop J K Q(t) Q(t+1)
0 0 0 0 No change
J Q
0 0 1 1
0 1 0 0 Reset
K Q 0 1 1 0
1 0 0 1
Q(t+1) = JQ’ + K’Q Set
1 0 1 1
1 1 0 1
 T Flip-Flop Toggle
1 1 1 0
T Q T Q(t) Q(t+1)
0 0 0
No change
Q 0 1 1
1 0 1
Q(t+1) = TQ’ + T’Q = T  Q Toggle
Applied Physics, FUUAST, Islamabad 1 1 0 31
 Flip-Flops

Master-Slave D Flip-Flop
D D Q D Q Q
D Latch D Latch
(Master) (Slave)
C C

Master Slave
CLK
CLK

D
Looks like it is negative
edge-triggered QMaster

QSlave
Applied Physics, FUUAST, Islamabad 32
Flip-Flop Characteristic Tables

SR Flip-Flop JK Flip-Flop
S R Q(t+1) J K Q(t+1)
0 0 Q(t) No change 0 0 Q(t) No change
0 1 0 Reset 0 1 0 Reset
1 0 1 Set 1 0 1 Set
1 1 ? Invalid 1 1 Q’(t) Toggle

D Flip-Flop T Flip-Flop
D Q(t+1) T Q(t+1)
0 0 Reset 0 Q(t) No change
1 1 Set 1 Q’(t) Toggle
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34
 Flip-Flop Characteristic Equations
SR Flip-Flop JK Flip-Flop

S R Q(t+1) J K Q(t+1)
0 0 Q(t) No change 0 0 Q(t) No change
0 1 0 Reset 0 1 0 Reset
1 0 1 Set 1 0 1 Set
1 1 ? Invalid 1 1 Q’(t) Toggle
Q(t+1) = S + R’Q Q(t+1) = JQ’ + K’Q

D Flip-Flop T Flip-Flop

D Q(t+1) T Q(t+1)
0 0 Reset 0 Q(t) No change
1 1 Set 1 Q’(t) Toggle
Q(t+1) = D Q(t+1) = T  Q
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35
 Flip-Flop Excitation Tables
SR Flip-Flop JK Flip-Flop
Q(t) Q(t+1) S R Q(t) Q(t+1) J K
0 0 0 X 0 0 0 X
0 1 1 0 0 1 1 X
1 0 0 1 1 0 X 1
1 1 X 0 1 1 X 0

D Flip-Flop T Flip-Flop S R Q(t+1)

0J 0 Q(t+1)
K Q(t)
Q(t) Q(t+1) D Q(t) Q(t+1) T
0
D 10Q(t+1)0
Q(t)
0 0 0 0 0 0
10 01 0 10
0 1 1 0 1 1 T Q(t+1)
11 10 1 ?1
1 0 0 1 0 1 0 Q(t)
11 1Q’(t)Q’(t)
1 1 1 1 1 0
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36
 Flip-Flops with Direct Inputs

Asynchronous Reset

D Q R’ D CLK Q(t+1)
0 X X 0
Q
R
Reset

Applied Physics, FUUAST, Islamabad 37

 Flip-Flops with Direct Inputs

Asynchronous Reset

D Q R’ D CLK Q(t+1)
0 X X 0
Q 1 0 ↑ 0
R 1 1 ↑ 1
Reset

Applied Physics, FUUAST, Islamabad 38

 Flip-Flops with Direct Inputs

Asynchronous Preset and Clear

Preset

PR PR’ CLR’ D CLK Q(t+1)

D Q 1 0 X X 0

Q
CLR
Reset

Applied Physics, FUUAST, Islamabad 39

 Flip-Flops with Direct Inputs

Asynchronous Preset and Clear

Preset

PR PR’ CLR’ D CLK Q(t+1)

D Q 1 0 X X 0
0 1 X X 1
Q
CLR
Reset

Applied Physics, FUUAST, Islamabad 40

 Flip-Flops with Direct Inputs

Asynchronous Preset and Clear

Preset

PR PR’ CLR’ D CLK Q(t+1)

D Q 1 0 X X 0
0 1 X X 1
Q 1 1 0 ↑ 0
CLR 1 1 1 ↑ 1
Reset

Applied Physics, FUUAST, Islamabad 41

 6-4 Analysis of Clocked Sequential Circuits
 An Example of a Sequential Circuit

0
0
x
A y 0 A = 0, B = 0, x = 0
1 B

1 x 0 Present Next State Output

0 A
R Q B 1
State x=0 x=1 x=0 x=1
x 0 A B A B A B y y
B
0
S Q 0
1 A 0 0 0 0 0 1 0 0
0 1 1 1 0 1 0 0
0 x 0 1 0 1 0 0 0 0 1
B
R Q A 1
1
1 1 1 0 1 1 0 0
1 x 0
S Q
0 B A 0

CLK t t+1 t

Applied Physics, FUUAST, Islamabad

42
 6-4 Analysis of Clocked Sequential Circuits
 An Example of a Sequential Circuit

1
0
x
A y 0 A = 0, B = 0, x = 1
1 B

0 x 0 Present Next State Output

0 A
R Q B 0
State x=0 x=1 x=0 x=1
x 1 A B A B A B y y
B
1
S Q 1
1 A 0 0 0 0 0 1 0 0
0 1 1 1 0 1 0 0
1 x 1 1 0 1 0 0 0 0 1
B
R Q A 1
1
1 1 1 0 1 1 0 0
0 x 0
S Q
B A 0
0
CLK t t+1 t

Applied Physics, FUUAST, Islamabad

43
 6-4 Analysis of Clocked Sequential Circuits
 An Example of a Sequential Circuit

0
0
x
A y 0 A = 0, B = 1, x = 0
0 B

1 x 0 Present Next State Output

0 A
R Q B 0
State x=0 x=1 x=0 x=1
x 0 A B A B A B Y y
B
0
S Q 1
1 A 0 0 0 0 0 1 0 0
0 1 1 1 0 1 0 0
0 x 0 1 0 1 0 0 0 0 1
B
R Q A 0
0
1 1 1 0 1 1 0 0
1 x 1
S Q
1 B A 1

CLK t t+1 t

Applied Physics, FUUAST, Islamabad

44
 6-4 Analysis of Clocked Sequential Circuits
 An Example of a Sequential Circuit

1
0
x
A y 0 A = 0, B = 1, x = 1
0 B

0 x 0 Present Next State Output

0 A
R Q B 0
State x=0 x=1 x=0 x=1
x 1 A B A B A B y y
B
1
S Q 1
1 A 0 0 0 0 0 1 0 0
0 1 1 1 0 1 0 0
1 x 0 1 0 1 0 0 0 0 1
B
R Q A 1
0
1 1 1 0 1 1 0 0
0 x 0
S Q
1 B A 0

CLK t t+1 t

Applied Physics, FUUAST, Islamabad

45
 6-4 Analysis of Clocked Sequential Circuits
 An Example of a Sequential Circuit

0
1
x
A y 0 A =1, B = 0, x = 0
1 B

1 x 1 Present Next State Output

1 A
R Q B 1
State x=0 x=1 x=0 x=1
0 x 0 A B A B A B Y y
S Q B 0
0 A 0 0 0 0 0 1 0 0
0 1 1 1 0 1 0 0
0 x 0 1 0 1 0 0 0 0 1
1 B
R Q A 0
1 1 1 0 1 1 0 0
1 x 0
S Q
0 B A 1

CLK t t+1 t

Applied Physics, FUUAST, Islamabad

46
 6-4 Analysis of Clocked Sequential Circuits
 An Example of a Sequential Circuit

1
1
x
A y 1 A = 1, B = 0, x = 1
1 B

0 x 0 Present Next State Output

1 A
R Q B 1
State x=0 x=1 x=0 x=1
x 0 A B A B A B y y
B
1
S Q 0
0 A 0 0 0 0 0 1 0 0
0 1 1 1 0 1 0 0
1 x 1 1 0 1 0 0 0 0 1
B
R Q A 1
1
1 1 1 0 1 1 0 0
0 x 0
S Q
0 B A 0

CLK t t+1 t

Applied Physics, FUUAST, Islamabad

47
 6-4 Analysis of Clocked Sequential Circuits
 An Example of a Sequential Circuit

0
1
x
A y 0 A =1, B = 1, x = 0
0 B

1 x 1 Present Next State Output

1 A
R Q B 1
State x=0 x=1 x=0 x=1
x 0 A B A B A B Y y
B
0
S Q 0
0 A 0 0 0 0 0 1 0 0
0 1 1 1 0 1 0 0
0 x 0 1 0 1 0 0 0 0 1
B
R Q A 0
0
1 1 1 0 1 1 0 0
1 x 1
S Q
1 B A 1

CLK t t+1 t

Applied Physics, FUUAST, Islamabad

48
 6-4 Analysis of Clocked Sequential Circuits
 An Example of a Sequential Circuit

1
1
x
A y 0 A = 1, B = 1, x = 1
0 B

0 x 0 Present Next State Output

1 A
R Q B 0
State x=0 x=1 x=0 x=1
x 0 A B A B A B y y
B
1
S Q 1
0 A 0 0 0 0 0 1 0 0
0 1 1 1 0 1 0 0
1 x 0 1 0 1 0 0 0 0 1
B
R Q A 0
0
1 1 1 0 1 1 0 0
0 x 0
S Q
1 B A 1

CLK t t+1 t

Applied Physics, FUUAST, Islamabad

49
 6-4 Analysis of Clocked Sequential Circuits
 An Example of a Sequential Circuit
0/0 1/0 Present Next State Output
State x=0 x=1 x=0 x=1
00 1/0 01
A B A B A B y y
1/1 0/0 0 0 0 0 0 1 0 0
0 1 1 1 0 1 0 0
10 11
0/0 1/0 1 0 1 0 0 0 0 1
0/0 1 1 1 0 1 1 0 0
State Diagram State Table

State Equations
A(t+1) = (A’B + AB’+ AB)x’ + ABx = Bx’ + (B’x)’A = S + R’A

B(t+1) = (A’B’+ A’B + AB)x + A’Bx’ = A’x +(Ax’)’B = S + R’B

Applied Physics, FUUAST, Islamabad
50
 6-4 Analysis of Clocked Sequential Circuits
 An Example of a Sequential Circuit
State Equations
x
A(t+1) = SA + R’A A A
B
y

= Bx’ + (B’x)’A x R Q B
= Bx’ + (B + x’)A A

A(t+1) = Bx’ + Ax’+ AB x S Q B

A
B(t+1) = SB + R’B B
x
= A’x +(Ax’)’B B
R Q A
= A’x +(A’ + x) B x S Q A
B(t+1) = A’x + Bx + A’ B B
CLK
y = xAB’
Applied Physics, FUUAST, Islamabad
51
 6-4 Analysis of Clocked Sequential Circuits
 An Example of a Sequential Circuit
State Equations Present Next State Output
A(t+1) = SA + R’A A State x=0 x=1 x=0 x=1
A B A B A B y y
= Bx’ + (B’x)’A
0 0 0 0 0 1 0 0
= Bx’ + (B + x’)A 0 1 1 1 0 1 0 0
A(t+1) = Bx’ + Ax’+ AB 1 0 1 0 0 0 0 1
1 1 1 0 1 1 0 0
B(t+1) = SB + R’B B
= A’x +(Ax’)’B t t+1 t
= A’x +(A’ + x) B
B(t+1) = A’x + Bx + A’ B
y = xAB’
State Diagram 52
Applied Physics, FUUAST, Islamabad
 Analysis of Clocked Sequential Circuits

The State
● State = Values of all Flip-Flops

x
Example D Q A

AB=00 Q

D Q B

CLK Q

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53
 Analysis of Clocked Sequential Circuits

State Equations
x
D Q A
A(t+1) = DA
Q
= A(t) x(t)+B(t) x(t)
=Ax+Bx
D Q B
B(t+1) = DB
CLK Q
= A’(t) x(t)
y
= A’x
y(t) = [A(t)+ B(t)] x’(t)
= (A + B) x’
Applied Physics, FUUAST, Islamabad 54
 Analysis of Clocked Sequential Circuits
 State Table (Transition Table)
x
Present Next D Q A
Input Output
State State
Q
A B x A B y
0 0 0 0 0 0 B
D Q
0 0 1 0 1 0
CLK Q
0 1 0 0 0 1
0 1 1 1 1 0 y

1 0 0 0 0 1
1 0 1 1 0 0
A(t+1) = A x + B x
1 1 0 0 0 1
1 1 1 1 0 0 B(t+1) = A’ x
y(t) = (A + B) x’
t t+1 t 55
Applied Physics, FUUAST, Islamabad
 Analysis of Clocked Sequential Circuits
 State Table (Transition Table)

Present Next Present Next State Output

Input Output
State State State x=0 x=1 x=0 x=1
A B x A B y A B A B A B y y
0 0 0 0 0 0 0 0 0 0 0 1 0 0
0 0 1 0 1 0 0 1 0 0 1 1 1 0
0 1 0 0 0 1 1 0 0 0 1 0 1 0
0 1 1 1 1 0 1 1 0 0 1 0 1 0
1 0 0 0 0 1
1 0 1 1 0 0 t t+1 t
1 1 0 0 0 1
A(t+1) = A x + B x
1 1 1 1 0 0
B(t+1) = A’ x

t t+1 t y(t) = (A + B) x’
Applied Physics, FUUAST, Islamabad
56
 Analysis of Clocked Sequential Circuits

 State Diagram Present Next State Output

State x=0 x=1 x=0 x=1
AB input/output A B A B A B y y
0 0 0 0 0 1 0 0
0 1 0 0 1 1 1 0
0/0 1/0
1 0 0 0 1 0 1 0
0/1 1 1 0 0 1 0 1 0
00 10
x
D Q A
0/1
Q
1/0 0/1 1/0
D Q B

CLK Q
01 11
y
1/0 57
Applied Physics, FUUAST, Islamabad
 Analysis of Clocked Sequential Circuits

D Flip-Flops
Example: x D Q A
Present Next
y
Input
State State CLK Q
A x y A
0 0 0 0
0 0 1 1 A(t+1) = DA = A  x  y
0 1 0 1
0 1 1 0
1 0 0 1 01,10
1 0 1 0
00,11 0 1 00,11
1 1 0 0
1 1 1 1 01,10
Applied Physics, FUUAST, Islamabad State Diagram 58
 Analysis of Clocked Sequential Circuits

JK Flip-Flops J Q A

x K Q
Example:
Present Next Flip-Flop J Q B
I/P
State State Inputs
A B x A B JA KA JB KB K Q

0 0 0 0 1 0 0 1 0 CLK

0 0 1 0 0 0 0 0 1 JA = B KA = B x’
0 1 0 1 1 1 1 1 0 JB = x’ KB = A  x
0 1 1 1 0 1 0 0 1 A(t+1) = JA Q’A + K’A QA
1 0 0 1 1 0 0 1 1
1 0 1 1 0 0 0 0 0 = A’B + AB’ + Ax
1 1 0 0 0 1 1 1 1 B(t+1) = JB Q’B + K’B QB
1 1 1 1 1 1 0 0 0
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= B’x’ + ABx + A’Bx’ 59
 Analysis of Clocked Sequential Circuits

JK Flip-Flops J Q A

x K Q
Example:
Present Next Flip-Flop J Q B
I/P
State State Inputs
A B x A B JA KA JB KB K Q

0 0 0 0 1 0 0 1 0 CLK

0 0 1 0 0 0 0 0 1 1 0 1
0 1 0 1 1 1 1 1 0 11
00
0 1 1 1 0 1 0 0 1
1 0 0 1 1 0 0 1 1 0
0 0
1 0 1 1 0 0 0 0 0
1 1 0 0 0 1 1 1 1 01 10
1 1 1 1 1 1 0 0 0 1
1 60
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 Analysis of Clocked Sequential Circuits
A
T Flip-Flops
x T Q y

R Q
Example:
Present Next F.F
I/P O/P
State State Inputs T Q
B
A B x A B TA TB y
0 R Q
0 0 0 0 0 0 0
0 0 1 0 1 0 1 0 CLK Reset
0 1 0 0 1 0 0 0
TA = B x TB = x
0 1 1 1 0 1 1 0
y =AB
1 0 0 1 0 0 0 0
1 0 1 1 1 0 1 0
A(t+1) = TA Q’A + T’A QA
= AB’ + Ax’ + A’Bx
1 1 0 1 1 0 0 1
B(t+1) = TB Q’B + T’B QB
1 1 1 0 0 1 1 1
=xB 61
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 Analysis of Clocked Sequential Circuits
A
T Flip-Flops
x T Q y

R Q
Example:
Present Next F.F
I/P O/P
State State Inputs T Q
B
A B x A B TA TB y
R Q
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0 CLK Reset
0 1 0 0 1 0 0 0
0/0 0/0
0 1 1 1 0 1 1 0
00 1/0 01
1 0 0 1 0 0 0 0
1 0 1 1 1 0 1 0 1/1 1/0
1 1 0 1 1 0 0 1
11 10
1 1 1 0 0 1 1 1 0/1 0/0
1/0 62
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 6-7 Design Procedure
 Problem statement (state diagram, state table, or State
Equations).
 Obtain state table from the given information.
 Determine number of required flip-flops and assign
letter symbols to states.
 Choose the type of flip-flops to be used.
 From the state table, drive circuit excitation and
output tables.
 Obtain simplified flip-flops input functions and circuit
output functions.
 Draw the logic diagram.
Applied Physics, FUUAST, Islamabad
63
 Logic Circuit from State Diagram
 Excitation
State DiagramTable Excitation Table
0 1 0
00 11 Present Next Flip-Flop
I/P
State State Inputs
A B x A B JA KA JB KB
1 1 0 0 0 0 0 0 X 0 X

1 0 0 0 1 0 1 0 X 1 X
01 0 10 0 1 0 1 0 1 X X 1
0 1 1 0 1 0 X X 0
Next State
Present State 1 0 0 1 0 X 0 0 X
x=0 x=1
A B A B A B 1 0 1 1 1 X 0 1 X
0 0 0 0 0 1 1 1 0 1 1 X 0 X 0
0 1 1 0 0 1 1 1 1 0 0 X 1 X 1
1 0 1 0 1 1
1 1 1 1 0 0 AB input/output
State Table Applied Physics, FUUAST, Islamabad 64
 Logic Circuit from State Diagram
Bx 00 01 11 10 Bx 00 01 11 10
A B A B
0 0 0 0 1 0 X X 0 1
KB = A ʘ x
A X X X X A X X 1 0
1 1
x x
JA = Bx’
Present Next Flip-Flop
Bx 00 01 11 10 I/P
A B State State Inputs
0 X X X X A B x A B JA KA JB KB
A 0 0 1 0 0 0 0 0 0 0 X 0 X
1
x 0 0 1 0 1 0 X 1 X
KA = Bx 0 1 0 1 0 1 X X 1
Bx 00 01 11 10
A B 0 1 1 0 1 0 X X 0
0 0 1 X X 1 0 0 1 0 X 0 0 X
A 0 1 X X 1 0 1 1 1 X 0 1 X
1
x 1 1 0 1 1 X 0 X 0
JB = x
1 1 1 0 0 X 1 X 1 65
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 Logic Circuit from State Diagram
 Logic diagram

J Q A JA = Bx’

x K Q KA = Bx

J Q B JB = x

K Q KB = A ʘ x

CLK

Applied Physics, FUUAST, Islamabad 66

 6-8 Design of Counters

3-bit Binary Counter 000

001
111
Using T Flip-Flop
110 010

Flip -Flop
Inputs 101 011
100
A B C A B C TA T B TC
0 0 0 0 0 1 0 0 1 State Diagram
0 0 1 0 1 0 0 1 1
Excitation Table
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1 Q(t) Q(t+1) T
1 0 0 1 0 1 0 0 1 0 0 0
1 0 1 1 1 0 0 1 1 0 1 1
1 1 0 1 1 1 0 0 1 1 0 1
1 1 1 0 0 0 1 1 1 1 1 0
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67
6-8 Design of Counters
Flip -Flop TC = 1
Inputs
TB = C
A B C A B C TA T B TC TA = BC
0 0 0 0 0 1 0 0 1 BC 00 01 11 B 10
0 0 1 0 1 0 0 1 1 A
0 0 1 1 0
0 1 0 0 1 1 0 0 1
1 1 A 0 1 1 0
0 1 1 1 0 0 1 1
C
1 0 0 1 0 1 0 0 1
1 1 TB = C
1 0 1 1 1 0 0
1 1 0 1 1 1 0 0 1 BC 00 01 11
B
10
A
1 1 1 0 0 0 1 1 1 0 0 0 1 0
A 0 0 1 0
1
C
TA = BC

Applied Physics, FUUAST, Islamabad 68

 6-8 Design of Counters

3-bit Binary Counter 000

001
111
Using JK Flip-Flop
110 010

Flip-Flop 101 011

Inputs 100

A B C A B C JA KA JB KB JC KC
State Diagram
0 0 0 0 0 1 0 x 0 x 1 x
0 0 1 0 1 0 0 x 1 x x 1 Excitation Table
0 1 0 0 1 1 0 x x 0 1 x
Q(t) Q(t+1) J K
0 1 1 1 0 0 1 x x 1 x 1
0 0 0 X
1 0 0 1 0 1 x 0 0 x 1 x
0 1 1 X
1 0 1 1 1 0 x 0 1 x x 1
x 0 x 0 1 x 1 0 X 1
1 1 0 1 1 1
1 1 1 0 0 0 x 1 x 1 x 1 1 1 X 0
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69
 6-8 Design of Counters
Flip-Flop JC = KC = 1
Inputs JB = KB = C
A B C A B C JA KA JB KB JC KC JA = KA = BC
0 0 0 0 0 1 0 x 0 x 1 x BC 00 01 11 B 10
A
0 0 1 0 1 0 0 x 1 x x 1 0 1 X X
0
0 1 0 0 1 1 0 x x 0 1 x
A 0 1 X X
0 1 1 1 0 0 1 x x 1 x 1 1
C
1 0 0 1 0 1 x 0 0 x 1 x BC 00 01 11 10
1 x x 1 B
1 0 1 1 1 0 x 0 A
0 X X 1 0
1 1 0 1 1 1 x 0 x 0 1 x
x 1 A X X 1 0
1 1 1 0 0 0 x 1 x 1 1
C
BC 00 01 11 10 BC 00 01 11 10
A B A B JB = KB = C
0 0 0 1 0 0 X X X X
A X X X X A 0 0 1 0 JA = KA = BC
1 1
C C
Applied Physics, FUUAST, Islamabad 70
 6-8 Design of Counters
JC = KC = 1
JB = KB = C
JA = KA = BC
BC 00 01 11 B 10
A
0 0 1 X X
A 0 1 X X
1
C
BC 00 01 11 10
Logic Diagram of a 3-bit counter A B
using JK Flip-Flop 0 X X 1 0
A X X 1 0
1
C
BC 00 01 11 10 BC 00 01 11 10
A B A B JB = KB = C
0 0 0 1 0 0 X X X X
A X X X X A 0 0 1 0 JA = KA = BC
1 1
C C
Applied Physics, FUUAST, Islamabad 71
 6-8 Design of Counters
 3-bit Binary Counter 111
000

with missing states 110 001

Using JK Flip-Flop
101 010
Flip-Flop
Inputs 100

A B C A B C JA KA JB KB JC KC 011

0 0 0 0 0 1 0 x 0 x 1 x State Diagram
0 0 1 0 1 0 0 x 1 x x 1 Excitation Table
0 1 0 1 0 0 1 x x 1 0 x
Q(t) Q(t+1) J K
0 1 1 1 0 0 1 x x 1 x 1
0 0 0 X
1 0 0 1 0 1 x 0 0 x 1 x
0 1 1 X
1 0 1 1 1 0 x 0 1 x x 1
x 1 x 1 0 x 1 0 X 1
1 1 0 0 0 0
1 1 1 0 0 0 x 1 x 1 x 1 1 1 X 0
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72
 6-8 Design of Counters
Flip-Flop KB = KC = 1
Inputs JB = C, JC = B’
A B C A B C JA KA JB KB JC KC JA = KA = B
0 x 1 x BC 00
0 0 0 0 0 1 0 x A
01 11 B 10

0 0 1 0 1 0 0 x 1 x x 1 0 0 1 X X
0 1 0 1 0 0 1 x x 1 0 x A 0 1 X X
1
0 1 1 1 0 0 1 x x 1 x 1 C
1 0 0 1 0 1 x 0 0 x 1 x JB = C
BC 00 01 11 10
1 0 1 1 1 0 x 0 1 x x 1 A B
1 1 0 0 0 0 x 1 x 1 0 x 0 1 X X 0
1 1 1 0 0 0 x 1 x 1 x 1 A 1 X X 0
1
BC 00 01 11 10 BC 00 01 11 10 C
A B A B J C = B’
0 0 0 1 1 0 X X X X
A X X X X A 0 0 1 1 JA = KA = B
1 1
C C
Applied Physics, FUUAST, Islamabad 73
 6-8 Design of Counters
KB = KC = 1
JB = C, JC = B’
JA = KA = B
BC 00 01 11 B 10
A
0 0 1 X X
A 0 1 X X
1
C
JB = C
BC 00 01 11 10
Logic Diagram of a 3-bit counter with A B
Missing states using JK Flip-Flop 0 1 X X 0
A 1 X X 0
1
BC 00 01 11 10 BC 00 01 11 10 C
A B A B J C = B’
0 0 0 1 1 0 X X X X
A X X X X A 0 0 1 1 JA = KA = B
1 1
C C
Applied Physics, FUUAST, Islamabad 74
 6-9 Design with State Equations

Sequential Circuits with D Flip-Flops

 The Characteristic Equation of D Flip-Flop is: Q(t+1) = D
 From the excitation Table 6-10, the minterms are:
Present Next Flip-Flop
A(t+1) = DA (A, B, x) = ∑ (2, 4, 5, 6) State
I/P
State Inputs
A B x A B JA KA JB KB
B(t+1) = DB (A, B, x) = ∑ (1, 3, 5, 6)
0 0 0 0 0 0 X 0 X
 Simplified Flip-Flop input 0 0 1 0 1 0 X 1 X
0 1 0 1 0 1 X X 1
functions are:
0 1 1 0 1 0 X X 0
DA (A, B, x) = AB’ + Bx’ 1 0 0 1 0 X 0 0 X
1 0 1 1 1 X 0 1 X
DB (A, B, x) = A’ x + B’ x + ABx’
1 1 0 1 1 X 0 X 0
= x (A’ + B’ ) + ABx’ 1 1 1 0 0 X 1 X 1
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75
 6-9 Design with State Equations

Sequential Circuits with D Flip-Flops

 The Characteristic Equation of D Flip-Flop is: Q(t+1) = D

Example 6-4
 For the given state equations: Flip-flops inputs are:
A(t+1) = C  D DA = C  D

B(t+1) = A DB = A

C(t+1) = B DC = B

D(t+1) = C DD = C

 The circuit can be constructed with four D Flip-Flops and

one exclusive-OR gate.
Applied Physics, FUUAST, Islamabad 76
 6-9 Design with State Equations

Sequential Circuits with JK Flip-Flops

 The Characteristic Equation of JK is: Q(t+1) = JQ’ + K’ Q

Example 6-5
 Design a sequential circuit with JK Flip-Flops to satisfy the
following state equations:
A(t+1) = A’ B’ CD + A’ B’ C + ACD + AC’ D’
B(t+1) = A’ C + C D’ + A’ B C’
C(t+1) = B
D(t+1) = D’

Applied Physics, FUUAST, Islamabad 77

 6-9 Design with State Equations

Sequential Circuits with JK Flip-Flops

 The Characteristic Equation of JK is: Q(t+1) = JQ’ + K’ Q

Example 6-5 (Continued)

A(t+1) = A’ B’ CD + A’ B’ C + ACD + AC’ D’
= (B’ CD + B’ C ) A’ + (CD + C’ D’ ) A
= (B’ C ) A’ + (C ʘ D ) A JA = (B’ C ) & KA = C  D
B(t+1) = A’ C + C D’ + A’ B C’
= (A’ C + C D’ )(B + B’ ) + (A’ C’ ) B
= (A’ C + C D’ )B’ + (A’ C + C D’ + A’ C’ ) B
= (A’ C + C D’ )B’ + (A’ + C D’ ) B
JB = A’ C + C D’ & KB = AC’ + A D
Applied Physics, FUUAST, Islamabad 78
 6-9 Design with State Equations

Sequential Circuits with JK Flip-Flops

 The Characteristic Equation of JK is: Q(t+1) = JQ’ + K’ Q

Example 6-5 (Continued)

A(t+1) = (B’ C ) A’ + (C ʘ D ) A JA = (B’ C ) & KA = C  D

B(t+1) = (A’ C + C D’ )B’ + (A’ + C D’ ) B

JB = (A’ + D’ )C & KB = A(C’ + D)
C(t+1) = B
= B (C + C’ ) = (B)C’ + (B)C JC = B & KC = B’
D(t+1) = D’
= 1. D’ + 0. D J D = 1 & KD = 1

Applied Physics, FUUAST, Islamabad 79

 End of
Chapter 6
Applied Physics, FUUAST, Islamabad 80