MODULE 4: Field Effect Transistors

FET Biasing: Structure, Operation of JFET, JFET Characteristics, JFET Biasing – Fixed, Self
and Voltage Divider bias.
FET Amplifiers: JFET small signal model, Amplifier with Fixed, Self and Voltage Divider
bias configurations.
Self-Study Components: MOSFET structure and characteristics

Field Effect Transistors (FETs) are unipolar devices because, unlike BJTs that use both
electron and hole current, they operate only with one type of charge carrier. The two main types
of FETs are the junction field-effect transistor (JFET) and the metal oxide semiconductor field-
effect transistor (MOSFET). The term field-effect relates to the depletion region formed in the
channel of a FET because of a voltage applied on one of its terminals (gate).

It is a voltage-controlled device, where the voltage between two of the terminals (gate and
source) controls the current through the device. A major advantage of FETs is their very high
input resistance. Because of their nonlinear characteristics, they are generally not as widely
used in amplifiers as BJTs except where very high input impedances are required. However,
FETs are the preferred device in low voltage switching applications because they are faster
than BJTs when turned on and off. The IGBT is generally used in high voltage switching
applications.

The JFET
The JFET (junction field-effect transistor) is a type of FET that operates with a reverse-biased
pn junction to control current in a channel. Depending on their structure, JFETs fall into either
of two categories, n channel or p channel.

The schematic symbols for both n-channel and p-channel JFETs are shown in Figure. (Note:
The arrow on the gate points “in” for n channel and “out” for p channel).
Basic Structure of JFET:
Figure (a) shows the basic structure of an n-channel JFET (junction field-effect transistor).
Wire leads are connected to each end of the n-channel; the drain is at the upper end, and the
source is at the lower end. Two p-type regions are diffused in the n-type material to form a
channel, and both p-type regions are connected to the gate lead. (The gate lead is shown
connected to only one of the p regions, which are internally connected.)

A p-channel JFET is shown in Figure (b). The structure is like n-channel JFET, just the p-
regions and n-regions are interchanged.

Basic Operation of JFET:

To illustrate the operation of a JFET, dc bias voltage is applied to an n-channel device. VDD
provides a drain-to-source voltage and supplies current from drain to source. VGG sets the
reverse-bias voltage between the gate and the source.
The JFET is always operated with the gate-source pn junction reverse-biased. Reverse biasing
of the gate-source junction produces a depletion region along the pn junction, which extends
into the channel and thus increases its resistance by restricting the channel width.

The channel width and thus the channel resistance can be controlled by varying the gate
voltage, thereby controlling the amount of drain current, ID. Figure illustrates this concept with
an n-channel device. The white areas represent the depletion region created by the reverse bias.
It is wider toward the drain end of the channel because the reverse-bias voltage between the
gate and the drain is greater than that between the gate and the source.
JFET Characteristics and Parameters
Drain Characteristic Curve
Consider the case when the gate-to-source voltage is zero (VGS = 0 V). This is produced by
shorting the gate to the source where both are grounded. As VDD (and thus VDS) is increased
from 0 V, ID will increase proportionally, as shown in the graph between points A and B. In
this area, the channel resistance is essentially constant because the depletion region is not large
enough to have significant effect. This is called the ohmic region because VDS and ID are related
by Ohm’s law.

At point B, the curve levels off and enters the active region where ID becomes essentially
constant. As VDS increases from point B to point C, the reverse-bias voltage from gate to drain
(VGD) produces a depletion region large enough to offset the increase in VDS, thus keeping ID
relatively constant.

Pinch-Off Voltage: For VGS = 0 V, the value of VDS at which ID becomes essentially constant
(point B on the curve) is the pinch-off voltage, VP. For a given JFET, VP has a fixed value. As
seen in the curve, a continued increase in VDS above the pinch-off voltage produces an almost
constant drain current until point C is reached. This value of drain current is IDSS (Drain to
Source current with gate Shorted) and is always specified on JFET datasheets. IDSS is the
maximum drain current that a specific JFET can produce regardless of the external circuit, and
it is always specified for the condition, VGS = 0 V.

Breakdown: As shown in the graph in Figure, breakdown occurs at point C when ID begins to
increase very rapidly with any further increase in VDS. Breakdown can result in irreversible
damage to the device, so JFETs are always operated below breakdown and within the active
region (constant current) (between points B and C on the graph). The JFET action that produces
the drain characteristic curve to the point of breakdown for VGS = 0 V is illustrated in Figure.

VGS Controls ID
Let’s connect a reverse-bias voltage, VGG, from gate to source as shown in Figure (a). As VGS
is set to increasingly more negative values by adjusting VGG, a family of drain characteristic
curves is produced, as shown in Figure (b).
Current ID decreases as the magnitude of VGS is increased to larger negative values because of
the narrowing of the channel. Also, for each increase in VGS, the JFET reaches pinch-off (where
constant current begins) at values of VDS less than VP. The term pinch-off is not the same as
pinch-off voltage, Vp. Therefore, the amount of drain current is controlled by VGS, as illustrated
in Figure.

Cutoff Voltage
The value of VGS that makes ID approximately zero is the cutoff voltage, VGS(off). The JFET
must be operated between VGS = 0 V and VGS(off). For this range of gate-to-source voltages, ID
will vary from a maximum of IDSS to a minimum of almost zero.

Relationship between VP and VGS(off)

VGS(off) and VP are always equal in magnitude but opposite in sign. A datasheet usually will
give either VGS(off) or VP, but not both. For example, if VGS(off) = -5 V, then VP = +5 V.

Problem:
For the JFET in Figure, VGS(off) = -4 V and IDSS = 12 mA. Determine the minimum value of VDD
required to put the device in the constant-current region of operation when VGS = 0 V.
JFET transfer characteristics and Forward Transconductance
Transfer characteristics is a plot of input voltage VGS vs the output current ID.

Initially at VGS=0, the current ID will be maximum and is given by IDSS. As the value of VGS
increases in negative direction, the current ID decreases. At VGS =VP = VGS(off), the current ID
becomes zero.

The forward transconductance (transfer conductance), gm, is an ac quantity that is defined as

a change in drain current (ΔID) divided by a corresponding change in gate-to-source voltage
(ΔVGS) with the drain-to-source voltage constant. It is expressed as a ratio and has the unit of
siemens (S).
ΔI𝐷
𝑔𝑚 =
ΔV𝐺𝑆
The approximate value of gm at any point on the transfer characteristic curve is calculated using
the formula,
𝑽𝑮𝑺
𝒈𝒎 = 𝒈𝒎𝟎 (𝟏 − )
𝑽𝑮𝑺(𝒐𝒇𝒇)
Where, gm0 is the value of gm measured at VGS = 0 V.
When a value of gm0 is not available, it can be calculated using the values of IDSS and VGS(off).
𝟐𝑰𝑫𝑺𝑺
𝒈𝒎𝟎 =
|𝑽𝑮𝑺(𝒐𝒇𝒇) |

Problem:
The following information is included on the datasheet for a 2N5457 JFET: typically, IDSS =
3.0 mA, VGS(off) = -6 V maximum, and gfs(max) = 5000 μS. Using these values, determine the
forward transconductance for VGS = -4 V, and find ID at this point.
FET Biasing
The controlling variable for a BJT transistor is a current level, whereas for the FET a voltage
is the controlling variable. The high input impedance of the FET means that the gate current
(𝐼𝐺 ) is effectively zero. The general relationships that can be applied to the dc analysis of all
FET amplifiers are,
IG = 0
And, ID = IS

1. Fixed Bias Configuration

The fixed bias configuration for a FET is a simple method that uses a single DC voltage
source 𝑉𝐺𝐺 to set a constant gate-source voltage 𝑉𝐺𝑆 .

The configuration includes the ac levels 𝑉𝑖 and 𝑉𝑜 and the coupling capacitors (𝐶1 and 𝐶2 ). The
coupling capacitors are “open circuits” for the dc analysis and low impedances (essentially
short circuits) for the ac analysis.
For the dc analysis,
𝐼𝐺 = 0 𝐴
and 𝑉𝑅𝐺 = 𝐼𝐺 𝑅𝐺 = 0 x 𝑅𝐺 = 0 𝑉
The zero-volt drop across 𝑅𝐺 permits replacing 𝑅𝐺 by a short-circuit equivalent, and the
equivalent circuit is as shown in figure.
Applying Kirchhoff’s voltage law in the clockwise direction of the indicated loop,

−𝑉𝐺𝐺 −𝑉𝐺𝑆 = 0
𝑉𝐺𝑆 = −𝑉𝐺𝐺

Since 𝑉𝐺𝐺 is a fixed dc supply, the voltage 𝑉𝐺𝑆 is fixed in magnitude, resulting in the
designation “fixed-bias configuration.”

The drain-to-source voltage of the output section can be determined by applying KVL to the
output loop:
𝑉𝐷𝐷 = 𝐼𝐷 𝑅𝐷 +𝑉𝐷𝑆
𝑽𝑫𝑺 = 𝑽𝑫𝑫 − 𝑰𝑫 𝑹𝑫

Since the source terminal is directly connected to ground,

𝑽𝑺 = 𝟎
The voltage across the drain and source terminals is,
𝑉𝐷𝑆 = 𝑉𝐷 −𝑉𝑆
𝑽𝑫𝑺 = 𝑽𝑫
The gate-to-source voltage is,
𝑉𝐺𝑆 = 𝑉𝐺 −𝑉𝑆
𝑽𝑮𝑺 = 𝑽𝑮
Problem:
1. Determine the following for the network shown in the figure.

2. Self-Bias Configuration
The self-bias configuration eliminates the need for two DC supplies. The controlling gate-to-
source voltage is determined by the voltage across a resistor 𝑹𝑺 .
For the dc analysis, the capacitors can again be replaced by “open circuits” and the resistor 𝑹𝑮
replaced by a short-circuit equivalent since 𝑰𝑮 = 0 A. The resultant DC equivalent circuit is,

The current through 𝑹𝑺 is the source current 𝑰𝑺 , but 𝑰𝑺 =𝑰𝑫 ,

𝑽𝑹𝑺 =𝑰𝑫 𝑹𝑺

Applying KVL to the input loop,

𝑽𝑮𝑺 + 𝑽𝑹𝑺 = 𝟎
𝑽𝑮𝑺 = −𝑽𝑹𝑺
𝑽𝑮𝑺 = −𝑰𝑫 𝑹𝑺
The output voltage 𝑽𝑫𝑺 can be determined by applying KVL to the output loop,
Problem.
1. Determine the following for the network
[Link] divider bias Configuration
The voltage-divider bias arrangement applied to BJT transistor amplifiers is also applied to
FET amplifiers. The basic construction is the same, but the dc analysis of each is quite different.
𝑰𝑮 = 𝟎 𝐀 for FET amplifiers, but the magnitude of 𝑰𝑩 for common-emitter BJT amplifiers can
affect the dc levels of current and voltage in both the input and output circuits.

The network is redrawn for the dc analysis by replacing all the capacitors, including the
bypass capacitor 𝑪𝑺 by an “open-circuit” equivalent
The gate voltage 𝑉𝐺 is the voltage across resistance 𝑅2 given by,
𝑉𝐶𝐶 𝑅2
𝑉𝐺 =
𝑅1 + 𝑅2

Applying KVL to the input loop,

𝑉𝐺 = 𝑉𝐺𝑆 + 𝐼𝑆 𝑅𝑆
But 𝐼𝐷 = 𝐼𝑆
𝑉𝐺 = 𝑉𝐺𝑆 + 𝐼𝐷 𝑅𝑆
𝑽𝑮𝑺 = 𝑽𝑮 − 𝑰𝑫 𝑹𝑺
The output voltage 𝑽𝑫𝑺 can be determined by applying KVL to the output loop,

Problem:
1. Determine ID and VGS for the circuit given in Figure. Assume VD = 7 V.
2. Determine the drain current ID for the circuit given in Fig. Given IDSS = 12 mA
and VGS(off) = -3 V.
Determine ID and VGS for the 2N4341 JFET with voltage-divider bias in Figure, given that for
this JFET the parameter values are such that VD =7.5 V.
 JFET amplifiers
Field-effect transistor amplifiers provide an excellent voltage gain with the added feature of a
high input impedance. They are also low-power-consumption configurations with good
frequency range and minimal size and weight. JFETs, depletion MOSFETs, and MESFETs can
be used to design amplifiers having similar voltage gains. The depletion MOSFET (MESFET)
circuit, however, has a much higher input impedance than a similar JFET configuration.

Although the common-source configuration is the most popular one, providing an inverted,
amplified signal, one also finds common-drain (source-follower) circuits providing unity gain
with no inversion and common-gate circuits providing gain with no inversion.

JFET Small Signal Model

The JFET small-signal model is a low-frequency equivalent circuit for JFET that represents its
behavior under small AC signals.

It consists of a voltage-controlled current source, 𝑔𝑚 𝑉𝑔𝑠 , in parallel with the drain resistance,
𝑟𝑑 , connected between the drain and source terminals. The gate terminal has an infinite input
resistance at low frequencies, so no current flows into it.
The transconductance 𝑔𝑚 represents the change in drain current (∆𝐼𝐷 ) for a change in gate-
source voltage (∆𝑉𝐺𝑆 ).
ΔI𝐷
𝑔𝑚 =
ΔV𝐺𝑆
𝑉𝑔𝑠 is the small-signal voltage between the gate and source.

The input impedance is represented by the open circuit at the input terminals and the output
impedance by the resistor 𝑟𝑑 from drain to source.
Given gfs = 3.8 mS and gos = 20 mS, sketch the FET ac equivalent model

1. CS amplifier Fixed Bias Configuration

The fixed-bias configuration includes the coupling capacitors C1 and C2, which isolate the dc
biasing arrangement from the applied signal and load; they act as short circuit equivalents for
the ac analysis.

For ac analysis, DC supplies are shorted to ground, and all the coupling capacitors are treated
as short circuit. The ac equivalent circuit using small signal model is as shown in figure.
The input impedance is,

Setting Vi = 0 V as required by the definition of Zo will establish Vgs as 0 V also. The result is
gmVgs = 0 mA, and the current source can be replaced by an open-circuit equivalent.

The output impedance is,

The output voltage is given by,

The negative sign in the resulting equation for Av clearly reveals a phase shift of 180° between
input and output voltages.
Problem:
The fixed-bias configuration has an operating point defined by VGSQ = -2 V and IDQ =
5.625 mA, with IDSS = 10 mA and VP = -8 V. The network is with an applied signal Vi. The
value of yos is provided as 40 μS.
 2. CS amplifier Voltage Divider Bias Configuration

For AC analysis, DC supplies are shorted to ground, and all the coupling capacitors are treated
as short circuit. The ac equivalent circuit using small signal model is as shown in figure.

The input impedance is,

Problem:
A certain JFET Voltage Divider Bias amplifier has an input impedance of 100 kΩ, output
impedance of 1.2 kΩ and a gain of -80. Determine the peak output voltage across the load of 5
kΩ if the input applied is 10 mV peak sinusoid.

3. CS amplifier Self Bias Configuration

The fixed-bias configuration has the distinct disadvantage of requiring two DC voltage sources.
The self-bias configuration requires only one DC supply to establish the desired operating
point.
 i. Bypassed RS
The capacitance CS is included in the circuit which bypasses the resistance RS. For AC
analysis, DC supplies are shorted to ground, and all the coupling capacitors are treated as
short circuit. The ac equivalent circuit using small signal model is as shown in figure.

The negative sign in the resulting equation for Av clearly reveals a phase shift of 180° between
input and output voltages.
ii. Bypassed RS
If CS is removed from the circuit, the resistor RS will be part of the ac equivalent circuit.
The input impedance is,

With rd=∞, the output impedance is,

When rd is included in the circuit,

With rd >> RD,

The voltage gain,

Problem:
The self-bias configuration has an operating point defined by VGSQ = -2.6 V and IDQ = 2.6 mA,
with IDSS = 8 mA and VP = -6 V. The network is applied with an AC signal Vi. The value of gos
is given as 20 μS.
Problems:
Sketch the output waveform of the amplifier shown in Fig.#QN# if the input applied is a
sinusoid of 10 mV peak given VGSQ = -3.2 V.

Sketch the output waveform of the amplifier shown in Fig.#QN# if the input applied is a
sinusoid of 10 mV peak. Given IDSS = 12 mA and Vp = -4V
MOSFET
The MOSFET (metal oxide semiconductor field-effect transistor) is another category of field-
effect transistor. Unlike the JFET, the MOSFET has no pn junction structure; instead, the gate
of the MOSFET is insulated from the channel by a silicon dioxide (SiO2) layer.

The two basic types of MOSFETs are enhancement (E) and depletion (D). Of the two types,
the enhancement MOSFET is more widely used. Because polycrystalline silicon is now used
for the gate material instead of metal, these devices are sometimes called IGFETs (insulated-
gate FETs).

Figure: E-MOSFET schematic symbols.

Figure: D-MOSFET schematic symbols.

Depletion Type MOSFET

i. Construction
The basic construction of the n-channel depletion-type MOSFET is provided in the Figure. A
slab of p-type material is formed from a silicon base and is referred to as the substrate. It is the
foundation on which the device is constructed. In some cases, the substrate is internally
connected to the source terminal. The source and drain terminals are connected through
metallic contacts to n-doped regions linked by an n-channel as shown in the figure. The gate is
also connected to a metal contact surface but remains insulated from the n-channel by a very
thin silicon dioxide (SiO2) layer. SiO2 is a type of insulator referred to as a dielectric which
means that there is no direct electrical connection between the gate terminal and the channel
of a MOSFET. It is the insulating layer of SiO2 in the MOSFET construction that accounts for
the very desirable high input impedance of the device.

The reason for the label metal–oxide–semiconductor FET is: metal for the drain, source, and
gate connections; oxide for the silicon dioxide insulating layer; and semiconductor for the basic
structure on which the n- and p-type regions are diffused. The insulating layer between the gate
and the channel has resulted in another name for the device: insulated-gate FET, or IGFET.

ii. Basic Operation and Characteristics

1. When VGS = 0 V (Gate and Source directly connected)

• The gate is at the same voltage as the source—so no electric field is applied between
them.
 • A positive voltage VDD is applied at the drain.
• Because the drain is positive, it pulls electrons from the n-channel toward itself.
• Electrons move → current flows.
• This current is called IDSS, the maximum drain current when VGS = 0 V.
So, with 0 V on the gate, the MOSFET behaves like a JFET and naturally conducts.

2. When VGS is Negative

Example: VGS = –1 V, –2 V, … up to –6 V (pinch-off).
• A negative gate repels electrons in the n-channel (like charges repel).
• It also pulls holes from the p-substrate (opposite charges attract).
• Because electrons and holes move toward each other, they recombine.
• Recombination reduces the number of free electrons left in the channel → less
current.
• The more negative the gate voltage,
→ the more recombination,
→ the narrower the channel,
→ the lower the drain current.

At a sufficiently large negative voltage (approximately –6 V), the channel “pinches off,” and
the current becomes nearly zero. This region (between the cutoff and IDSS) is called the
depletion region.

3. When VGS is Positive

• A positive gate attracts electrons into the channel from the p-substrate.
 • More electrons mean more carriers available for conduction.
• Drain current increases rapidly.
• Even a small change in VGS (like +1 V) produces a big jump in current.
• Too much positive gate voltage can cause the drain current to exceed the device’s
rating, which is dangerous.
Since positive VGS adds carriers to the channel, this region is called the enhancement region.

Enhancement Type MOSFET

i. Construction
An n-channel enhancement-type MOSFET is built on a slab of p-type silicon, which serves as
the substrate. The source and drain terminals are created by diffusing two heavily n-doped
regions into this p-type substrate, and metal contacts connect to these regions. As in depletion-
type MOSFETs, the substrate may either be internally tied to the source or brought out as a
separate fourth terminal for external bias control. A thin insulating layer of silicon dioxide
(SiO₂) is placed on the surface between the source and drain, and a metal gate terminal sits on
top of this insulating layer. The important difference between the enhancement-type and
depletion-type MOSFET is that there is no pre-existing channel between the source and drain
in the enhancement MOSFET. the construction of an enhancement-type MOSFET is quite
similar to that of the depletion-type MOSFET, except for the absence of a channel between the
drain and source terminals.
 ii. Basic Operation and Characteristics
When VGS = 0 V and a voltage is applied between the drain and source of an enhancement-
type n-channel MOSFET, almost no current flows. This is because the device has no built-in
n-channel, unlike depletion MOSFETs or JFETs. Even though the drain and source regions are
n-doped, the p-type substrate between them creates two reverse-biased p–n junctions, which
block current flow. However, when both VGS and VDS are made positive, the positive gate
voltage pushes holes away from the surface of the p-substrate and pulls electrons (minority
carriers) toward the SiO₂ layer. Because the oxide prevents electrons from entering the gate,
they accumulate at the surface and gradually form a thin n-type inversion layer.

When enough electrons gather to form a conductive path, current begins to flow, and this
required gate voltage is called the threshold voltage VT. Beyond VT, increasing VGS increases
the number of electrons in the induced channel, resulting in a rise in drain current. But if VGS
is held constant and VDS is increased, the current eventually reaches a saturation level. This
happens because the gate becomes less positive relative to the drain, reducing the electron
attraction near the drain end and narrowing the channel—a process called pinch-off. Saturation
occurs when VDS = VGS – VT, meaning that higher gate voltages shift the saturation point to
higher VDS values. Beyond this point, further increases in VDS do not significantly increase the
drain current until breakdown occurs.