Module 1

27 November 2025 15:06

Architecture of 8085 Microprocessor

The 8085 is an 8-bit general-purpose microprocessor developed by
Intel. It has a 40-pin dual-in-line package (DIP) and can address
64 KB of memory.
Block Diagram (Explanation)
The architecture consists of the following major components:
Component Function
Accumulator (A) 8-bit register used in arithmetic & logical
operations; part of ALU
General Purpose Used for temporary storage; can form
Registers (B, C, D, E, H, register pairs BC, DE, HL
L)
Program Counter (PC) 16-bit register that holds the address of
the next instruction to be fetched
Stack Pointer (SP) 16-bit register that points to the top of
the stack in memory
Instruction Register & Holds opcode of the current instruction &
Decoder decodes it
Arithmetic Logic Unit Performs arithmetic & logical operations;
(ALU) uses accumulator & flag register
Flag Register Stores status bits after operations (Sign,
Zero, Auxiliary Carry, Parity, Carry)
Temporary Registers Internal use during ALU operation (not
accessible by user)
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 accessible by user)
Timing & Control Unit Generates control signals to coordinate
all internal & external operations
Interrupt Control Unit Manages interrupts (TRAP, RST7.5, RST6.5,
RST5.5, INTR)
Serial I/O Control (SID, For serial communication
SOD)
Address Buffer & Data Separate 8-bit buffers used to send out
Buffer address and data
Address/Data Latch Lower 8 bits of address and data share
(AD0–AD7 multiplexed) common lines to reduce pins
Clock Generator Generates and controls the timing
sequence within the CPU

Working / Operation of 8085 Microprocessor

The operation of the 8085 can be explained in three main cycles:
1. Fetch Cycle
• The Program Counter (PC) gives the address of the next
instruction to the memory.
• This address is placed on the address bus.
• The memory returns the opcode (instruction).
• The opcode goes to the Instruction Register for decoding.
2. Decode Cycle
• The Instruction Decoder interprets the opcode.
• The Control Unit generates necessary control signals to perform
that instruction.
3. Execute Cycle
• Based on the instruction type:
○ ALU performs arithmetic/logical operation
○ Data moves between registers and memory
○ Program Counter updates to next instruction
○ Flags are updated after ALU operations
○ If the instruction is a jump/branch/call, PC is modified
accordingly

Instruction Execution Example

For an instruction like:

ADD B
Operation happens as follows:
1. Opcode of ADD B is fetched from memory.
2. Decoder identifies it as addition of register B with accumulator
A.
3. ALU performs A = A + B.
4. Flags update based on result.

Key Features of 8085 (for extra 1–2 marks)

• 8-bit microprocessor
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 • 8-bit microprocessor
• 16-bit address bus → 64 KB memory access
• 8-bit data bus
• 5 hardware interrupts
• Requires +5V supply
• Clock frequency ~ 3 MHz

Conclusion
The 8085 microprocessor architecture is made up of registers, ALU,
control unit, buses, and memory/IO interface units. The processor
operates by fetching, decoding, and executing instructions
sequentially, with the control unit coordinating all internal and
external activities.

8085 Microprocessor – Pin Functions (40 Pins)

The 8085 has 40 pins classified into Power supply, Clock,
Address/Data bus, Control signals, Interrupts, Serial I/O, and DMA
signals.

Power Supply & Clock Signals

Pin No. Pin Name Function
40 Vcc +5V power supply input
20 Vss Ground (0V reference)
18 X1 Crystal / clock input terminal 1
19 X2 Crystal / clock input terminal 2
37 CLK OUT Clock output to synchronize external peripherals

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 Address & Data Bus
Pin No. Pin Name Function
21–28 AD0 – AD7 Multiplexed lower 8-bit address / data bus
30–37 A8 – A15 Higher 8-bit address bus (only address)
🔹 AD0–AD7 carry address during T1 state and data during T2 & T3
🔹 ALE is used to demultiplex these pins

Control & Status Signals

Pin Pin Name Function
No.
30 ALE (Address Latch Demultiplexes AD0–AD7 by enabling
Enable) latch
32 IO/M̅ Selects I/O or Memory (1 = I/O, 0 =
Memory)
31 S1 Status signal indicating processor state
29 S0 Status signal indicating processor state
34 RD̅ Read signal, enables data read from
memory or I/O
33 WR̅ Write signal, enables data write to
memory or I/O
35 READY Wait control; 0 → processor waits, 1 →
continues
36 HOLD Requests DMA; external device asks for
bus control
39 HLDA (Hold Acknowledgement of HOLD signal
Acknowledge)

Interrupt & Control Signals

Pin Pin Name Function
No.
6 INTR General interrupt request input (maskable)
10 INTA ̅ Interrupt Acknowledge output used on INTR
7 RST 5.5 Maskable vectored interrupt
8 RST 6.5 Maskable vectored interrupt
9 RST 7.5 Maskable vectored interrupt
11 TRAP Highest priority, non-maskable vectored interrupt
5 RESET IN̅ Resets processor (PC=0000H)
12 RESET Indicates processor is reset; used to reset
OUT peripherals

Serial I/O Pins

Pin No. Pin Name Function
4 SID (Serial Input Data) Serial data input
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4 SID (Serial Input Data) Serial data input
3 SOD (Serial Output Data) Serial data output

DMA Signals
Pin No. Pin Name Function
38 IO/M̅ (Already explained)—memory or I/O selector
36 HOLD (DMA request by external device)
39 HLDA (DMA acknowledgment by processor)

Auxiliary Signals
Pin No. Pin Name Function
34 RD̅ Memory/I/O read control
33 WR̅ Memory/I/O write control
30 ALE Latches the lower address from AD0–AD7

Memory / I/O Selection Logic Summary

IO/M̅ RD̅ WR̅ Operation
0 0 1 Memory Read
0 1 0 Memory Write
1 0 1 I/O Read
1 1 0 I/O Write

Important Points
• 40 pins total
• AD0 – AD7 are multiplexed
• TRAP is non-maskable & highest priority
• RESET IN̅ initializes PC to 0000H
• HLDA responds to HOLD for DMA

Conclusion
Each pin of the 8085 plays a specific role in ensuring proper
communication, memory interface, interrupt handling, serial
transmission, and synchronization. Understanding pin functions is
essential for interfacing and system design.

What is isR? Explain intERRupt stRuctuRE of 8085 along With

pRioRitiEs .What aRE vEctoREd intERRupts?

ISR (Interrupt Service Routine)

An Interrupt Service Routine (ISR) is a special subroutine/program
executed automatically when an interrupt occurs.
• When an interrupt is received, the processor suspends the current
program, jumps to the ISR, executes it, and then returns to the
main program.
• ISR contains instructions to handle the interrupt condition (for

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 • ISR contains instructions to handle the interrupt condition (for
example servicing input/output, reading sensor, etc.).

Interrupt Structure of 8085

The 8085 has 5 hardware interrupt input signals, each having
different priorities and characteristics.
List of Interrupts (Highest → Lowest priority)
Priorit Interrup Type Maskable Vector Address
y t
1 TRAP Hardwar Non- 0024H
e maskable
2 RST 7.5 Hardwar Maskable 003CH
e
3 RST 6.5 Hardwar Maskable 0034H
e
4 RST 5.5 Hardwar Maskable 002CH
e
5 INTR Hardwar Maskable Given by external device
e through INTA

Working of Interrupts
1. When an interrupt arrives, the processor finishes the current
instruction.
2. It stores the address of the next instruction (PC) on the stack.
3. It jumps to ISR address (vector address).
4. After servicing, the instruction RET is executed → returns to main
program.

Masking / Unmasking
• RST 7.5, RST 6.5, RST 5.5 can be enabled or disabled (masked).
• TRAP can never be masked.
• The interrupts are controlled by instructions:
○ EI – Enable all maskable interrupts
○ DI – Disable all maskable interrupts
○ SIM – Set interrupt masks for RST 7.5, 6.5, and 5.5
○ RIM – Read interrupt status

Vectored Interrupts
A vectored interrupt is an interrupt that automatically transfers
program control to a fixed memory location (vector address) that
stores the ISR.
In 8085, the vectored interrupts are:
Interrupt Vector Address
TRAP 0024H
RST 7.5 003CH
RST 6.5 0034H
RST 5.5 002CH
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RST 5.5 002CH
RST 7 0038H
RST 6 0030H
RST 5 0028H
RST 4 0020H
🔹 These interrupts do not need external hardware to provide the
address.
Non-vectored interrupt
• INTR is non-vectored → does not have a fixed ISR address.
• The external device must send the op-code of RST instruction
during INTA cycle to guide the CPU to the ISR location.

Summary
• ISR is a routine that executes in response to an interrupt.
• 8085 interrupt structure consists of 5 hardware interrupts with
priority:
TRAP > RST 7.5 > RST 6.5 > RST 5.5 > INTR.
• TRAP is non-maskable; others are maskable.
• A vectored interrupt jumps to a predefined (fixed) memory
address, whereas non-vectored interrupts require external hardware
to supply the ISR address.

Explain thE tERm tstatE, machinE cyclE and instRuction

cyclE With REspEct to ExEcution of instRuction

T-State, Machine Cycle and Instruction Cycle (with respect to

execution of instruction)
When executing an instruction, the 8085 microprocessor follows three
timing concepts:

T-State (Timing State)

• A T-state is the smallest unit of time in a microprocessor
operation.
• It corresponds to one clock period.
• Every operation inside the CPU takes multiple T-states.
Example:
If clock frequency = 3 MHz,
Clock period = 1 / 3 MHz = 0.33 µs per T-state.

Machine Cycle
• A Machine Cycle is a basic operation performed by the processor
during instruction execution.
• Each machine cycle consists of a fixed number of T-states (usually
3 to 6 T-states).
• Common machine cycles include:
Machine Cycle Purpose

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 Opcode Fetch Get instruction opcode from memory
Memory Read Read data from memory
Memory Write Write data to memory
I/O Read Read data from input device
I/O Write Write data to output device
Interrupt Ack. Acknowledge interrupt
Example: Opcode Fetch cycle normally = 4/6 T-states.

Instruction Cycle
• An Instruction Cycle is the total time required to fetch and
execute one instruction.
• It consists of a sequence of one or more machine cycles, and each
machine cycle consists of multiple T-states.
Example:
For instruction MOV A, B
• 1 opcode fetch machine cycle only
• Total = 1 machine cycle = 4 T-states
For instruction MVI A, 32H
• Requires two machine cycles:
✔ Opcode Fetch
✔ Memory Read (for immediate data)
• Total = 2 machine cycles = 10 T-states (4 + 6)

Relation Between the Three Terms

Term Meaning Contains
T-state One clock period —
Machine Cycle Smallest unit of work Multiple T-states
Instruction Time to execute full Multiple Machine
Cycle instruction Cycles
Hierarchy

Instruction Cycle
↓
Machine Cycle(s)
↓
T-States

Conclusion
During the execution of an instruction, the 8085 uses T-states as basic
time units, completes specific operations in machine cycles, and the
entire sequence of these machine cycles forms the instruction cycle.
Hence, instruction execution timing can be measured in terms of T-
states + machine cycles.

dEscRibE vonn nEWmann modEl and functions of thE folloWing

[Link] addREss REgistER, 2. mEmoRy data REgistER 3. instRuction
REgistER. What is a micRopRogRam sEquEncER? Explain it's WoRking
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REgistER. What is a micRopRogRam sEquEncER? Explain it's WoRking
and function
1. Von Neumann Model
The Von Neumann Architecture (also called Princeton Architecture) is a
classical computer design model proposed by John Von Neumann in
1945.
Key Idea
• A computer uses a single memory to store both data and program
instructions.
• The CPU accesses memory through a common bus to fetch instructions
and read/write data.
Main Components
Component Function
Input Unit Feeds data/instructions to computer
Output Unit Displays processed results
Memory (Main Memory) Stores both program instructions and data
ALU (Arithmetic Logic Performs arithmetic and logical operations
Unit)
Control Unit (CU) Controls execution and synchronizes all
units
Registers Temporary storage for execution
Working
1. An instruction is fetched from memory.
2. The control unit decodes it.
3. Data is loaded into registers and processed by ALU.
4. Result is stored back into memory or sent to output.
➡ The Von Neumann model follows the Fetch → Decode → Execute
cycle.

2. Functions of Registers
(a) Memory Address Register (MAR)
• MAR holds the address of memory location from where data or
instruction is to be read or written.
• It acts as an interface between CPU and memory for addressing.
🔹 CU loads MAR with the required memory address.
🔹 MAR sends this address to memory via the address bus.

(b) Memory Data Register (MDR)

(Also called Memory Buffer Register – MBR)
• MDR holds the data that is being transferred to or from memory.
• It acts as a buffer between CPU and memory.
🔹 When reading: memory → MDR → CPU
🔹 When writing: CPU → MDR → memory

(c) Instruction Register (IR)

• IR holds the current instruction fetched from memory.

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 • IR holds the current instruction fetched from memory.
• The opcode of the instruction is then decoded by the control unit.
🔹 IR ensures that the instruction remains available during execution.
🔹 After completion, the next instruction is fetched.

3. Microprogram Sequencer
A microprogram sequencer is a hardware unit in the control section of a
computer used to generate the sequence of microinstructions required
for executing machine instructions.
Why needed?
• The control unit must send correct control signals in the correct
order to different CPU parts.
• A microprogram sequencer ensures this order and branching are
handled automatically.
Working
• Each machine-level instruction is broken into micro-operations.
• These micro-operations are stored in Control Memory (or
Microprogram Memory).
• For each instruction:
1. The sequencer fetches microinstruction from control memory.
2. It generates the necessary control signals to activate ALU,
registers, buses, etc.
3. Based on conditions (like jump, branch, flag status), the sequencer
decides the next microinstruction.
Functions
Function Explanation
Generate next microinstruction Normal sequence, branching,
address conditional jumps
Fetch microinstruction from Load to Control Register
control memory
Generate control signals To operate ALU, registers, buses,
memory
Handle microbranches For decision-making based on flags
or status bits
➡ Therefore, the microprogram sequencer controls execution flow at the
micro-operation level, forming the heart of the microprogrammed
control unit.

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