VLSI CAD
Introduction
VLSI Computer Aided Design (CAD)
What is the need for CAD:
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Large number of devices (Billions of transistors)
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Optimization for high performance
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Time-to-market
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Cost
Tool Suites:
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Commercial
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Cadence, Synopsys, Mentor Graphics to name a few
Open Source:
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OpenLANE: Which is a collection of Open Source VLSI tools like Yosys, abc,
OpenSTA, Fault, Magic, Netgen, IRSIM etc.
VLSI Computer Aided Design (CAD)
VLSI Design flow steps:
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Architectural Design
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Front End Design
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Back End Design
VLSI Design Cycle
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System Specification
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First step in the design process
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Consider Functionality, Performance, Physical Dimensions
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Selection of fabrication technology
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Trade-off between market requirements, technology and economical viability
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Outcome: Size, Speed, Power and Functionality
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Architectural Design
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Choosing the architecture: RISC vs. CISC, Floating point or Fixed point,
Pipelined or non-pipelined, cached or no cache etc
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Outcome: Micro Architectural Specification MAS file
VLSI Design Cycle - continued
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Behavioral or Functional Design
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Behavior of the system blocks in terms of Input, Output and Delay/Timing
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Functional blocks identified. Area, Power, Speed of each block estimated
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Design at functional block level – Functional Block schematic
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Outcome: Timing Diagram
Fig. Courtesy Sherwani
VLSI Design Cycle - Continued
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Logic Design
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Logic operations derived using HDL
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Boolean expressions obtained and minimized/ optimized
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Simulated and functionality and behavior verified
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Technology mapping (binding to a technology library) may be done
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Register Transfer Level description in terms of Verilog is obtained
X = A.B.C.D + (A + D).C + A.(B + C)
Y = A.(B + C) + A.D + B.C
VLSI Design Cycle - Continued
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Circuit Design
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Circuit level design of the logical blocks/ Gates/ Transistor.
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Circuit simulation to verify timing, functionality
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Outcome: Net list
Fig. Courtesy Sherwani
VLSI Design Cycle - Continued
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Physical Design
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Converting Circuit level description(Net list) into Geometric representation
(creation of Layout, masks for photolithography)
Fig. Courtesy Sherwani
VLSI Design Cycle - Continued
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Fabrication, Wafer level testing, Die level testing
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Packaging (Dual In-line Package, Ball Grid Array, Quad Flat Package,
Multi Chip Modules) Testing and Debugging
Packaged Chip
Wafer with Dies Figs. Courtesy Sherwani
Physical Design Cycle
Fig. Courtesy Sherwani
Detailed VLSI Design flow
Front End Design (Architectural Design and Logic Design)
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System Specification
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Micro-Architecture
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RTL Design
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Simulation
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Synthesis
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Process of translation of Design to RTL format
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Static Timing Analysis (STA)
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Design For Testability (DFT)
Detailed VLSI Design flow - Continued
Back End Design (Physical Design)
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Partitioning
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Floor Planning - IO, Core Power Ring, IP (Macros) Power Ring,
Trunks, Straps
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Placement
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Clock Tree Synthesis (CTS)
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Global Routing – Power Planning
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Antenna Diode Insertion
Detailed VLSI Design flow - Continued
Back End Design Continued
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Logical Equivalence Check (LEC)
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Detailed Routing
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Compaction
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RC Extraction
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Static Timing Analysis (STA)
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Physical Verification – Design Rule Check (DRC), Layout Vs.
Schematic (LVS)
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GDSII, LEF generation
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Some kind of verification of the functionality / behavior is done after
most of the steps.
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This verification may be using Simulation (Logical, Circuit) or formal
verification methodologies using Mathematical Model
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Post fabrication, the chips are tested on Testers that apply Test
Signals. The Test vectors may be generated using Automatic Test
Pattern Generators (ATPGs) software. Response of the Chip is
obtained
Design space exploration
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Architectural Exploration – Try various architectures and pick an optimum
design
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Synthesis Exploration
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Front End design space being explored for various delay, power, area
combinations.
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May be performed after architecture is finalized and a optimum design is
chosen
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Design Exploration
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May be done after Routing
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Go back to Synthesis Exploration stage – Proves to be very expensive in
terms of time and money.
Image courtesy: [Link]
Performance Metrics
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Speed
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Higher the better
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Size
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Smaller the better
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Cost
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Lower the better
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Flexibility – In terms of the Modification/ Re-Configuration of the functionality
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More the better
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Market Time
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Shorter the better
Design Styles
ASICs (Application Specific Integrated Circuits) – Functionality can’t be changed,
Least Flexible
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Full Custom
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Transistor level Hand crafted circuits
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High performance – Low Power, High Speed, High Cost, Very long Design Time.
Suitable for large volume
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Standard Cell
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Predesigned Layout of Gates, Latches, Flip-flops, Buffers etc are available. Arrange
them in two dimensional array, wire them to implement the required functionality
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Good Performance in terms of Power, Area and speed. Design time is long
Design Styles -continued
Programmable/ Flexible Designs
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Gate Array
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Prefabricated Sea of Gates (array of Transistors) – Wire them to implement the
required functionality
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Medium in terms of performance (Power, speed, cost, design time)
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FPGA
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Prefabricated Array of Complex Logical Blocks containing Look Up Tables
(LUTs), Muxs, Flip-flops/Latches, Memory Blocks, MAC Units, Switchable
Interconnect grids etc are available. Map the required functionality using a bit-
map
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Re-configurable
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Design effort and time are less, Poor Speed, Power and Area
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Cost effective for small numbers. Exorbitantly costly for large numbers.
Summary comparison of Design Styles
Style
Full-Custom Standard Cell Gate Array FPGA
Cell Size Variable Fixed Height Fixed Fixed
Cell Type Variable Variable Fixed Programmable
Cell Placement Variable In rows Fixed Fixed
Interconnections Variable Variable Variable Programmable
Summary comparison of Design Styles
Style
Full-Custom Standard Cell Gate Array FPGA
Compact to
Area Compact Moderate Large
moderate
High to
Performance High Moderate Low
moderate
Fabrication
All All Routing Layers None
Layers