CISC Architecture
CISC Architecture:
• Complexed Instruction Set Computer
• type of processor design that includes a large number of
complex instructions capable of performing multiple internal
operations in a single instruction.
• Characteristics:
1) The instructions are variable length instructions.
2) The instructions are two operand instructions.
3) Each instruction needs multiple clock cycles for execution.
4) Instructions can operate directly on memory without
requiring registers. Example: ADD A, B where A and B are
memory locations.
5) Complex Addressing Modes and less number of General
purpoe registers.
6) Microprogrammed Control Unit
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CISC: Block diagram:
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CISC Architecture:
• Instruction Set:
The set of instructions is instruction set. The CISC
instruction set contains the following instructions:
a) Data movement Instructions
b) Arithmetic and Logic Instructions
c) Branching Instructions
d) Subroutine Instructions
e) Rotate and Shift Instructions
f) I/O Instructions
g) Special Instructions
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Data transfer Instructions:
• Move data between registers and memory , Memory to
memory and registers to registers.
• Examples:
• MOVE R1, R2 → Copy contents of R2 into R1.
• LOAD R1, X → Load from memory location X into R1.
• STORE R1, X → Store R1 into memory X.
• PUSH R1 / POP R1 → Stack operations.
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Arithmetic & Logic Instructions:
• Arithmetic Instructions:
• Perform arithmetic operations such as addition, subtraction,
multiplication & division.
• Example:
ADD R1, R2 → R1 = R1 + R2.
SUB R1, (X) → R1 = R1 – Memory[X].
MUL R1, R2 → Multiply.
DIV R1, R2 → Divide.
• Logic Instructions:
• Perform logical operations such as AND, OR and NOT in binary
digits. Example:
AND R1, R2
OR R1, (X)
XOR R1, R2
NOT R1
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Branching Instructions:
• These instructions alter the sequential execution of instructions.
• They transfer the execution control from one part of a program
to another part either by conditionally or unconditionally.
• Types:
a) Conditional branching
b) Unconditional Branching
• Example:
JMP LABEL → Unconditional jump.
BEQ LABEL → Branch if equal.
BNE LABEL → Branch if not equal.
BLE LABEL → Branch if less than or equal.
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Subroutine Instructions:
• These instructions are used to execute subroutines .
• Instructions:
a) Call – calls a subroutine
b) Return – returns the control from subroutine to main
program.
• Example:
CALL Sub1
------------
------------
Sub1: Load R1,A
Load R2,B
Add R1, R2
Store R1,C
RET
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Input/Output Instructions:
• Direct instructions for data transfer with I/O ports or memory-
mapped devices.
• Examples:
IN R1, PORT → Input from port.
OUT PORT, R1 → Output to port.
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Special Instructions:
• Deal with processor status and control.
• Examples:
NOP → No operation.
HLT → Halt execution.
SETC / CLRC → Set/clear condition flags.
INT n → Generate software interrupt.
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Shift Instructions:
• These instructions are used to shift the bits of an operand
either left or right by some specified number of bit positions.
• Shift Instructions:
a) Logical shift
b) Arithmetic shift
• Logical Shift:
• It contains two types of shifts. They are:
1) Logical shift left (LShiftL)
2) Logical shift Right(LShiftR)
• The general form LShiftL is
LShiftL Rj, count
• which shifts the contents of register Rj left by a number of bit
positions given by the count operand, and places the result in
register Rj. Vacated positions are filled with zeros.
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Shift Instructions:
• The general form LShiftR is
LShiftR Rj, count
• which shifts the contents of register Rj right by a number of bit
positions given by the count operand, and places the result in
register Rj. Vacated positions are filled with zeros.
• Example:
LShiftL R3,#2
LShiftL R3, #1
LShiftR R2, #2
LShiftR R2, #1
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Shift Instructions:
• Arithmetic Shift:
• A Left Arithmetic Shift of one position moves each bit to the
left by one. The vacant least significant bit (LSB) is filled with
zero and the most significant bit (MSB) is discarded. It is
identical to Left Logical Shift.
• A Right Arithmetic Shift of one position moves each bit to the
right by one. The least significant bit is discarded and the
vacant MSB is filled with the value of the previous (now shifted
one position to the right) MSB.
• Example:
AShiftL R3,#2
AShiftL R3, #1
AShiftR R2, #2
AShiftR R2, #1
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Rotate Instructions:
• Rotate Instructions:
• They Move the bits shifted out of one end of the operand into
the other end. Two versions are
a) Rotate-left and
b) Rotate-right
• Example:
RotateL R4,#2
RotateLC R1, #1
RotateR R2,#2
RotateRC R3,#1
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Addressing Modes:
• refer to the way in which the operand of an instruction is
specified.
• Effective address (EA) is calculated to find the address of the
operands.
• The addressing modes of RISC are
1) Immediate addressing mode
2) Register addressing mode
3) Absolute addressing mode
4) Indirect addressing mode
5) Indexed addressing mode
6) Base addressing mode
7) Relative addressing
8) Auto-increment and Auto-decrement Addressing
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Addressing Modes:
1) Immediate addressing mode:
• The operand is given explicitly in the instruction.
• # symbol is used to represent the immediate operand.
• For example, the instruction,
Add R4, #200
adds the value 200 to register R4 and stores the result into R4
2) Register addressing mode:
• The operand is the contents of a processor registers. Ie, the
name of the registers is given in the instruction.
• For example, the instruction,
Add R2, R3
uses the Register mode for all operands.
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Addressing Modes:
3) Absolute addressing mode:
• The operand is a memory location; ie, the address of the
location is given explicitly in the instruction. For example, the
instruction, Load R2, NUM1
loads the value in the memory location NUM1 into register
R2.
4) Indirect addressing mode:
• Also called register indirect addressing mode.
• The effective address of the operand is the contents of a
register that is specified in the instruction. For example,
consider the instruction,
Load R2, (R5)
• In this, the register R5 denotes the indirect addressing which
contains the address of the memory location.
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Addressing Modes:
Indirect addressing mode:
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Addressing Modes:
5) Indexed addressing mode:
• The effective address of the operand is generated by adding
a constant value to the contents of index register. It is
represented as,
X(Ri)
• The effective address of the operand is given by
EA = X + [Ri]
• Two ways of using index addressing mode:
a) Index register with address of memory location
b) index register with offset value
• Example:
Load R2, 20(R5)
• The EA = [R5]+20, from this address the content is loaded to R2.
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Addressing Modes:
6) Base addressing mode:
• The effective address is the sum of the content of the base
register Ri and Displacement value.
• EA = [B] + Displacement
• For Example,
Load R2, 20(R5)
• Loads the contents of the EA = R5+20 into register R2. Where,
R5 – Base register.
7) Relative addressing mode:
• The effective address is the sum of the value of program
counter and displacement.
• EA= [PC]+displacement
• For Example,
Load R2, 20(PC), which loads the content of [PC]+20 to
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Addressing Modes:
8) Auto-increment addressing mode:
• After accessing the operand, the register is automatically
incremented.
• For Example,
Load R2, (R1)+
• Loads the contents of R1 into register R2. Then the content of
R1 will be incremented.
EA = [R1] (Effective Address is contents of R2)
Operand = M[EA]
R1 = R1 + d (increment by word size d, usually 1, 2, or 4)
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Addressing Modes:
8) Auto-decrement addressing mode:
• After accessing the operand, the register is automatically
decremented.
• For Example,
Store R2, -(R1)
• decrements R1 and stores the content of R2 into register R1.
• R1 = R1 - d (decrement by word size d)
• EA = [R1]
• Operand = M[EA]
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RISC VS CISC:
S.
RISC CISC
NO.
Reduced Instruction Set Complex Instruction Set
1
Computer Computer
The number of instructions are
2 Contains Less Instructions
more as compared to RISC.
Contains Fixed Length Contains Variable Length
3
instructions instructions
Each Instruction needs Only Each Instruction needs
4
one clock cycle multiple clock cycles
Uses both hardwired
Uses only Hardwired
5 and Microprogrammed
Control Unit
Control Unit
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RISC VS CISC:
S.
RISC CISC
NO.
Can perform only Register
Can perform REG to REG or REG to
6 to Register Arithmetic
MEM or MEM to MEM
operations
Requires more number of
7 Requires less number of registers
registers
Simple and limited Complex and more addressing
8
addressing modes. modes.
9 RISC is highly pipelined. CISC is less pipelined.
10 RISC required more RAM. CISC required less RAM
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RISC VS CISC:
S.
RISC CISC
NO.
11 Focus on software Focus on hardware
Registers are used for
The stack is used for procedure
12 procedure arguments and
arguments and return addresses.
return addresses.
These chips are relatively These chips are complex to design.
13
simple to design.
14 They are inexpensive. They are relatively expensive.
Examples of RISC chips Examples of CISC include Intel
15
include SPARC, POWER PC. architecture, AMD.
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