B24EC2T07 - FPGA BASED SYSTEM DESIGN
SYLLABUS
MODULE 1 (10 hours)
Verilog HDL – based design, Overview of FPGA and EDA software: Introduction,
General description, Basic lexical elements and data types, Data types, Program
skeleton, Structural description, Gate-level combinational circuit, Testbench,
Introduction and overview of a general FPGA device, Gate-level greater-than circuit,
Gate-level binary decoder.
MODULE 2 (10 hours)
RT-level combinational circuits: Introduction, Operators, always block for a combina-
tional circuit, if statement, Case statement, General coding guidelines for an always
block, Parameter and constant, Design examples.
MODULE 3 (10 hours)
RT-level regular sequential circuits: Introduction to Regular Sequential Circuit, HDL
code of the FF and register, Test bench for sequential circuits, Design examples: shift
register, Binary counters. Testbench for sequential circuits, Case study: LED time-
multiplexing circuit, Stopwatch, Programmable square-wave generator, PWM and LED
dimmer, Rotating LED banner circuit.
MODULE 4 (8 hours)
FSM: Introduction, FSM representation and code development, Mealy and Moore
outputs, Design examples: Rising-edge detector, Debouncing circuit, Testing circuit, Case
study: Dual-edge detector Alternative debouncing circuit, Parking lot occupancy counter.
MODULE 5 (8 hours)
FSMD: Introduction, ASMD chart, Code development of an FSMD, Debouncing circuit
based on RT methodology, Code with explicit data path components, Testing circuit,
Design examples: Fibonacci number circuit, Division circuit, Binary-to-BCD conversion
circuit, Period counter, Accurate low-frequency counter.
Continuous Internal Evaluation Pattern:
Attendance :10 marks
Continuous Assessment Test (2 numbers) :25 marks
Assignment/Class work :15 marks
Text Books
1. Pong P. Chu, "FPGA Prototyping by Verilog Examples", John Wiley & Sons, 2008
Reference Books
1. FPGA-Based System Design – Wayne Wolf, Verlag: Prentice Hall
2. Modern VLSI Design: System-on-Chip Design (3rdEdition) Wayne Wolf, Verlag
3. Field Programmable Gate Array Technology- S. Trimberger, Edr, 1994, Kluwer
Academic
4. Digital Design Using Field Programmable Gate Array, P.K. Chan & S. Mourad, 1994,
Prentice Hall
5. Samir Palnitkar, "Verilog HDL: A Guide to Digital Design and Synthesis", Second
Edition, Prentice Hall PTR, 2003
6. B. Bala Tripura Sundari, T. R. Padmanabhan, "Design Through Verilog HDL", Wiley
India, 2012
Verilog HDL
Verilog HDL (Hardware Description Language) is used to model electronic systems
and digital circuits at various levels of abstraction, from algorithmic to gate level.
It enables designers to describe the structure and behaviour of hardware using a
syntax similar to the C programming language.
Verilog is commonly used in the design and verification of digital circuits such as
FPGAs and ASICs.
The language supports both simulation for functional verification and synthesis for
hardware implementation.
Problem
Design a 1 bit equality comparator.
SOP equation
y=a’b’+ab
p0=a’b’
p1=ab
y=p0+p1
Verilog code using gate level implementation style
"Always think in terms of the underlying hardware when designing Verilog code to
ensure efficient, synthesizable, and predictable digital circuit behaviour."
Comparison between C code and Verilog code
Comparison between C code and Verilog code
Feature C Code Verilog Code
Executes Sequentially In parallel (hardware)
Time of operation One-time when run Always active in hardware
Resource used CPU instruction Logic gate in a chip
Purpose Algorithm Circuit design
implementation
Identifier
In Verilog, an identifier is the name used to represent variables, modules, ports,
wires, registers, parameters, etc.
Rules for Identifiers
Must begin with a letter (a–z or A–Z) or underscore _.
Can contain letters, digits (0–9), and underscores.
Cannot start with a digit.
Are case-sensitive (data, Data, and DATA are all different).
Cannot use Verilog reserved keywords (e.g., module, input, wire).
Types of Comments in Verilog
1. Single-line comment
Starts with // and continues
to the end of the line.
2. Multi-line (block) comment
Enclosed between /* and */.
Can span multiple lines.
Logic Values
Symbol Meaning
0 Logic 0
1 Logic 1
x Unknown (high-impedance
or conflict), used in
simulation, don't synthesize
z High impedance (tri-state)
Data types
In Verilog, data types are used to declare signals, variables, and constants that
represent digital logic. Unlike high-level languages, Verilog data types are closely
tied to hardware structures.
1. Net Data Types (represent physical connections)
Used for wires and interconnections.
Type Description
wire Most common; used to
connect components
tri Tri-state net
wand Wired AND
wor Wired OR
2. Variable Data Types (hold values in procedural blocks)
Used in always or initial blocks.
Type Description
reg Stores value until updated
explicitly
integer Signed 32-bit integer
real Floating-point (for simulation
only)
time Used for timing simulation
3. Vector Data Types
Used to define multi-bit buses.
4. Parameter and Constant Types
Used to define constants or configurable values.
2-dimensional array
In Verilog, a 2-dimensional array is useful for representing memory-like structures
such as register files, ROMs, or RAMs. It's an array of vectors, where each entry can
hold multiple bits.
Syntax for Declaring 2D Arrays
reg [7:0] means each element is 8 bits
[0:15] means 16 elements indexed from 0 to 15
Example
Number representation
[size]'[base][value]
size -- (Optional) number of bits (e.g., 4, 8, 16)
' -- Required separator
base Radix
b Binary
d Decimal
h Hexadecimal
o Octal
value -- Numeric value (can include x for unknown, z for high impedance)
Examples
Verilog Number Meaning
4'b1010 4-bit binary = decimal 10
8'd255 8-bit decimal = 11111111 in binary
16'h1A3F 16-bit hexadecimal
6'o77 6-bit octal = 111111 binary
1'bx 1-bit unknown
1'bz 1-bit high impedance
Examples
If no base is specified, Verilog assumes the number is decimal.
If no size is specified: The number is 32 bits by default for constants. Verilog
extends or truncates the constant to match the size of the variable it's assigned to.
Coding methods
1. Gate-Level Modelling
Describes hardware using basic gates like and, or, not, etc.
Very close to actual hardware — used in small circuits or learning.
2. Dataflow Modelling
Uses continuous assignments (assign) to describe logic equations.
Good for combinational logic using Boolean expressions.
3. Behavioural Modelling
Describes behaviour using procedural blocks like always, initial.
Used for complex logic (FSMs, counters, etc.).
Can be combinational or sequential depending on sensitivity list.
4. Structural Modelling
Builds systems by interconnecting modules, similar to schematic-level.
Useful in hierarchical design.
5. Mixed Modelling
Most real-world designs use a mix of the above methods in different parts of the
code.
Summary
Gate level implementation of a 2 bit equality comparator
Product
a[1] a[0] b[1] b[0]
term
0 0 0 0 p0
0 1 0 1 p1
1 0 1 0 p2
1 1 1 1 p3
Verilog Code
Structural description using module instantiation (1 bit equality comparator)
Verilog Code
Verilog Code – connection by ordered list
Pros: Less typing.
Cons: Less readable and error-prone if
module definition changes.
Named connections are generally preferred
for clarity and maintainability,
especially in larger designs.
primitive instantiation
Syntax
<primitive_name> instance_name (output, input1, input2, ...);
In Verilog, primitive instantiation
refers to using built-in logic primitives
such as gates (and, or, not, xor, etc.)
directly in your code without
defining a module for them.
User-Defined Primitive (UDP)
A User-Defined Primitive (UDP) in Verilog is a way to define simple combinational or
sequential logic using truth tables, instead of full behavioral or structural code. UDPs are
useful for modeling logic gates or flip-flops compactly.
Syntax
UDP for 2-Input MUX
Limitations
UDPs cannot contain multiple outputs.
Cannot use procedural blocks (e.g., always, initial).
Sequential UDPs must define output as reg.
Testbench
Simulation Command (Icarus Verilog)
iverilog -o eq2_tb eq2.v tb_eq2.v
vvp eq2_tb
gtkwave eq2_tb.vcd
Internal structure of an FPGA
Block diagram of a configurable logic block
FPGA Development Flow
Back-annotation in FPGA design
refers to the process of feeding post-
synthesis or post-layout timing
information back into simulation to
verify the real-world behavior of a
digital design.
Problem
Design a gate level greater than circuit
Steps
1. Design truth table for a 2bit greater than circuit and logic expression in SOP format
2. Check functionality using testbench
3. Use 2-bit greater than circuit 2-bit equality comparator and minimum number of
gates to construct a 4bit greater than circuit
4. Check functionality using testbench
Truth table for 2-bit greater than circuit
Verilog code for 2-bit greater than circuit
Testbench
Use 2-bit greater than circuit 2-bit equality comparator and minimum number of
gates to construct a 4bit greater than circuit
Verilog code
Testbench
Problem
Design a gate level binary decoder
Steps
1. Design a 2 to 4 decoder with enable and derive HDL code using only logical
operations
2. Design a testbench for the 2 to 4 decoder
3. Use 2 to 4 decoder to derive 3 to 8 decoder
4. Design a testbench for the 3 to 8 decoder
5. Use 2 to 4 decoder to derive 4 to 16 decoder
6. Design a testbench for the 4 to 16 decoder
2 to 4 decoder with enable
Truth table
Verilog code
Testbench
Design 3 to 8 decoder using 2 to 4 decoder
Verilog code
Testbench
Use 2 to 4 decoder to derive 4 to 16 decoder
Verilog code
Testbench
Problem
Design an 8-bit, 2-input multiplexer using basic logic gates (AND, OR, NOT) and
component instantiation in Verilog.
Solution
Each input is 8 bits wide, and the selection is controlled by a single-bit select signal.
Implement a 1-bit 2:1 multiplexer as a separate module and instantiate it 8 times to
build the 8-bit version.
Verilog code - 1-bit 2:1 Multiplexer using Gates
Verilog code for 8-bit, 2-input multiplexer
Testbench
Problem
Design a 1-bit, 4-input multiplexer using basic logic gates (AND, OR, NOT) and
component instantiation in Verilog.
Steps
1. Use two 1-bit 2:1 multiplexers and one final 2:1 multiplexer to build the 4-input
version (hierarchical design).
2. Implement the 1-bit 2:1 multiplexer as a separate module using only gate-level
logic.
3. Use component instantiation to construct the 4-input version.
Block schematic
Verilog code
Problem
Design a digital circuit and corresponding Verilog code to implement the following
pseudo-code logic using gate-level logic and structural modeling (i.e., module
instantiation):
a – 4-bit input signal ([3:0]), y – 4-bit output signal ([3:0])
Design Constraints: Use only gate-level logic, Use module instantiation, Assume the
availability of the following reusable modules: comp4: 4-bit comparator module with
lt (less-than) output, mux4: 4-bit 2:1 multiplexer
Block diagram
Verilog code – top module
Verilog code – mux4
Verilog code – comp4
Problem
Design a digital circuit and corresponding Verilog code to implement the following
pseudo-code logic using gate-level logic and structural modeling (i.e., module
instantiation):
Inputs:
a – 4-bit input signal ([3:0])
b – 4-bit input signal ([3:0])
Output:
y – 4-bit output signal ([3:0])
Block diagram
Verilog code – top module
Problem
Design a digital circuit to implement a 4-bit input to 4-bit output mapping as defined by
the given graph. Your design must use basic gates and structural modeling (i.e., by
instantiating logic modules).
Specifications:
Input:
x – 4-bit input signal ([3:0])
Output:
y – 4-bit output signal ([3:0])