Scribd
Upload
4 views9 pages

Module 1 Verilog Notes

Uploaded by

Yohan Babu
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
4 views9 pages

Module 1 Verilog Notes

Uploaded by

Yohan Babu
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

MODULE 3 KTU ECT 203 LOGIC CIRCUIT DESIGN

BASIC ADDERS & SUBTRACTORS:

HALF ADDER:

LOGIC DIAGRAM: TRUTH TABLE:

A B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

VERILOG SOURCE CODE:

Dataflow Modeling:
module ha_dataflow(a, b, s, ca);
input a;
input b;
output s;
output ca;
assign s=a^b;
assign ca=a&b;
endmodule

SIMULATION OUTPUT:

HALF SUBSTRACTOR:

LOGIC DIAGRAM: TRUTH TABLE

A B DIFFERENCE BORROW
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
VERILOG SOURCE CODE:

Dataflow Modeling:
module hs_dataflow(a, b, dif, bor);
input a;
input b;
output dif;

SHILPHY P G, AP ECE
MODULE 3 KTU ECT 203 LOGIC CIRCUIT DESIGN

output bor;
wire abar;
assign abar=~a;
assign dif=a^b;
assign bor=b&abar;
endmodule

SIMULATION OUTPUT:

FULL ADDER:

LOGIC DIAGRAM: TRUTH


TABLE:
A B C SUM CARRY
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
VERILOG SOURCE CODE: 1 1 1 1 1

Dataflow Modeling:
module fulladddataflow(a, b, cin, sum, carry);
input a;
input b;
input cin;
output sum;
output carry;
assign sum=a^b^cin;
assign carry=(a & b) | (b & cin) | (cin & a);
endmodule

SHILPHY P G, AP ECE
MODULE 3 KTU ECT 203 LOGIC CIRCUIT DESIGN

SIMULATION OUTPUT:

FULL SUBSTRACTOR:

LOGIC DIAGRAM: TRUTH


TABLE:
A B C DIFFERENCE BORROW
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
VERILOG SOURCE CODE:

Dataflow Modeling:
module fulsubdataflow(a, b, cin, diff, borrow);
input a;
input b;
input cin;
output diff;
output borrow;
wire abar;
assign abar= ~ a;
assign diff=a^b^cin;
assign borrow=(abar & b) | (b & cin) |(cin & abar);
endmodule

SIMULATION OUTPUT:

FULL ADDER USING TWO HALF ADDERS:

A B C SUM CARRY

SHILPHY P G, AP ECE
MODULE 3 KTU ECT 203 LOGIC CIRCUIT DESIGN

LOGIC DIAGRAM: 0 0 0 0 0
TRUTH TABLE: 0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

VERILOG SOURCE CODE:

Dataflow modeling:
module fa_2ha(a,b,c,sum,carry);
input a,b,c;
output sum,carry;
wire p;
wire [0:2]q;
assign p=a^b;
assign q[0]=a&b;
assign q[1]=b&c;
assign q[2]=c&a;
assign sum=p^c;
assign carry=q[0]|q[1]|q[2];
endmodule

OR

module full_2halfadder(
input a,
input b,
input c,
output sum,
output carry
);
wire p;
assign p=a^b;
assign sum=p^c;
assign carry=a&b|b&c|c&a;
endmodule

SIMULATION OUTPUT:

SHILPHY P G, AP ECE
MODULE 3 KTU ECT 203 LOGIC CIRCUIT DESIGN

FULL SUBTRACTOR USING TWO HALF SUBTRACTORS:

LOGIC DIAGRAM: TRUTH TABLE:

A B C DIFFERENCE BORROW
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
VERILOG SOURCE CODE:

module full_2halfsub(
input a,
input b,
input bin,
output diff,
output bout
);
wire p;
wire abar;
assign abar=~a;
assign p=a^b;
assign diff=p^bin;
assign bout=(abar & b) | (b & bin) |(bin & abar);
endmodule

SIMULATION OUTPUT:

ENCODER:
LOGIC DIAGRAM: TRUTH TABLE:

D0 D1 D2 D3 D4 D5 D6 D7 X Y Z
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1

SHILPHY P G, AP ECE
MODULE 3 KTU ECT 203 LOGIC CIRCUIT DESIGN

0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1

VERILOG SOURCE CODE:


00000000
Dataflow Modeling:
module encod_data(d, x, y, z);
input [7:0] d;
output x;
output y;
output z;
assign x=d[4]|d[5]|d[6]|d[7];
assign y=d[2]|d[3]|d[6]|d[7];
assign z=d[1]|d[3]|d[5]|d[7];
endmodule
SIMULATION OUTPUT:

DECODER:

LOGIC DIAGRAM: TRUTH TABLE:

A B C Z(0) Z(1) Z(2) Z(3)

0 0 1 0 1 1 1
0 1 1 1 0 1 1
1 0 1 1 1 0 1
1 1 1 1 1 1 0

SHILPHY P G, AP ECE
MODULE 3 KTU ECT 203 LOGIC CIRCUIT DESIGN

VERILOG SOURCE CODE:

Dataflow Modeling:
module decoderdataflow(a,b,en, z);
input a,b,en;
output [0:3] z;
wire abar,bbar;
assign abar=~a;
assign bbar =~b;
assign z[0]=(abar & bbar & en);
assign z[1]=(abar & b & en);
assign z[2]=(a & bbar & en);
assign z[3]=(a & b & en);
endmodule
SIMULATION OUTPUT:

LOGIC DIAGRAM:

MULTIPLEXER:

SHILPHY P G, AP ECE
MODULE 3 KTU ECT 203 LOGIC CIRCUIT DESIGN

LOGIC DIAGRAM:
TRUTH TABLE:
1
D0 2 9
8

SELECT OUTPUT
1
D1 2
8
9

2
INPUT
3

4
5
1 Y S1 S0 Y
1
D2 2
8
9
0 0 D0
D3
1
2 9
0 1 D1
8

1 0 D2
2

1 1 D3
1

S1 S0

VERILOG SOURCE CODE:

Dataflow Modeling:
module muxdataflow(s, i, y);
input [1:0] s;
input [3:0] i;
output y;
wire s2,s3,s4,s5,s6,s7;
assign s2 = ~s[1];
assign s3 = ~s[0];
assign s4 = i[0]&s2&s3;
assign s5 = i[1]&s2&s[0];
assign s6 = i[2]&s[1]&s3;
assign s7 = i[3]&s[1]&s[0];
assign y = s4 | s5 | s6 | s7;
endmodule
SIMULATION OUTPUT:

DEMULTIPLEXER:
LOGIC DIAGRAM: `
TRUTH TABLE:

SHILPHY P G, AP ECE
MODULE 3 KTU ECT 203 LOGIC CIRCUIT DESIGN

S1 S0

INPUT OUTPUT
D S0 S1 Y0 Y1 Y2 Y3

1
1 0 0 1 0 0 0
2 1 0 1 0 1 0 0

2
Din 2
3
1 1 0 0 0 1 0
4
5
1
Y0 1 1 1 0 0 0 1
2
3
1
4 Y1
5

2
3
1
4 Y2
5

2
3
1
4 Y3
5

Enable

VERILOG SOURCE CODE:

Dataflow Modeling:
module demuxdataflow(s0,s1,i,y);
input s0,s1,i;
output [3:0] y;
wire s2,s3;
assign s2=~s0;
assign s3=~s1;
assign y[0]=i&s2&s3;
assign y[1]=i&s2&s1;
assign y[2]=i&s0&s3;
assign y[3]=i&s0&s1;
endmodule

SIMULATION OUTPUT:

SHILPHY P G, AP ECE

You might also like