Department of Computer Science and Engineering
QUESTION BANK
Sub : CS25C06 - Digital Principles and Computer Organization
Year/Sem : I/II
UNIT I- DIGITAL LOGIC
PART-A(2 mark)
1. Convert (1947) 10 into its equivalent octal and hexadecimal representations.
2. Perform subtraction using 1’s complement (11010)2 - (10000)2
3. Represent the decimal numbers -200 and 200 using 2’s complement binary form.
4. What is 1’s complement and 2’s complement.
5. State the rules for binary addition and subtraction.
6. State the DeMorgan’s theorem.
7. Define Boolean algebra.
8. What is mean by K-map.
9. What is Don’t care condition.
10. State the limitation of K-map.
11. Advantage and disadvantage of K-map.
12. Define minterm and maxterm.
13. Define Canonical form and Standard form.
14. What are the basic digital logic gates.
15. Which gates are called as Universal gates and give its advantage.
16. Simply the following Boolean expression to a minimum number of
literals:AB+A’C+BC
17. State the associative law of Boolean algebra.
18. Write logic symbol,expression and truth table of NAND,NOR.
19. Realize:OR gate using NAND.
20. Realize:AND gate using NOR.
21. Define SOP and POS.
22. Draw the logic diagram of AB+B’C
23. State the rules for K-map simplification
24. Define an Integrated circuits.
25. What are the advantages of Integrated circuits.
PART-B (13 mark)
1. Illustrate the rules for binary addition and subtraction using 2'complemented arithmetic.
Give example.
2. State and prove postulates and theorems of Boolean algebra.
3. Simplify the Boolean function using K-map method
F(W, X, Y, Z) = ∑ (0, 2, 4, 6, 8, 10, 12, 14).
4. Simplify the Boolean function using K-map.
F(W, X, Y, Z) = ∑ (1, 3, 7, 11, 15)+D(0, 2, 5).
5. Simplify the following function using Karnaugh Map.
F(W, X, Y, Z) = ∑ (0, 1, 2, 4, 5, 6, 8, 9, 12, 13, 14).
6. Reduce the Boolean function using K-map technique and implement using gates
F(W, X, Y, Z)= ∑ (0, 1, 4, 8, 9, 10) which has the don't care conditions
d(w, x, y, z) = (2, 11).
7. Simplify the following using K-map and implement it with two-level NAND gate circuit
F(A, B, C, D) = AB’+ ABD + ABD’ +A’C’D’ + A’BC’
8. Explain about different types of logic gates
[Link] and prove Demorgan’s theorem.
[Link] the following Boolean functions and draw it's Logic diagram.
(i) Y(A, B, C, D) = ∑m (0,5,7,8,9,10,11,14,15) +d (1,4,13)
(ii) Y(A,B,C,D) = πM (4,5,6,7,8,12) + d (1,2,3,9,11,14)
[Link] the Boolean function fusing the don't care condition in
(i) SOP (1) POS forms.
F(A,B,C,D) = A’B’D’ + A’C’D’ + A’BC.d(A, B, C, D) = A’BC’D + ACD + AB’D’
[Link] the following using K-map and implement it with NAND gate circuit
F(A,B,C,D)= AB’+ ABD + ABD’ +A’C’ D’ + A’BC’
[Link] the following with K-map and implement it with NOR gate circuit.
F(A, B, C, D) = πM (2,3,6,7,8,9,12,13)
[Link] 2's complement: 147-89
Find 1's complement: -42-68
[Link] the following in canonical SOP, and give its POS verify with truth table and draw
its logic diagram F(A,B,C,D)=AB+C’D+AB’C.
16.F(A,B,C)=AC+AB+BC convert to standard SOP and give minterms and truth table,logic
diagram
UNIT II- COMPUTER ARCHITECTURE
PART-A (2 mark)
[Link] are the Functional Units of Computer System.
[Link] Computer Architecture.
[Link] is the Von-Neumann Bottleneck.
[Link] are the features of Von –Neumann Architecture.
[Link] is the defining features of Harvard Architecture.
[Link] is the difference between the Von-Neumann Architecture and Harvard Architecture.
[Link] are the steps involved in Instruction Cycle.
[Link] is MIPS.
[Link] is MFLOPS.
[Link] is CPI.
[Link] Throughput.
[Link] Volatile and Non-Volatile Memory.
[Link] CPI.
PART B (13 mark)
[Link] neat sketch explain the functional units of Computer.
[Link] the important features of Von-Neumann Architecture.
[Link] in detail about Harvard Architecture.
[Link] the Phases of Instruction Execution.
[Link] are the Performance Metrics of a Computer.
[Link] the classes of computer.