VLSI - Model Questions (First Series)
State Moore’s law. Explain the significance of Moore’s law in semiconductor
industry
Draw the circuit diagram and VTC of a Resistive load NMOS Inverter. What are
the advantages of active pull up over passive pull up.
Why PMOS transistor can pass only strong ones and NMOS can pass strong zeros
List the advantages of CMOS logic
Why pMOS size is greater then nMOS size in a symmetric CMOS inverter ?
Explain with relevant waveforms
i) Propagation delay times τPHL and τPLH ii) Rise time and fall time
Explain how the rise time and fall time of CMOS inverter is estimated
Draw the circuit diagram and VTC of a CMOS Inverter. Explain its characteristics
under five regions of operation.
Explain the static and dynamic power dissipation in a CMOS circuit
What are the different types of power dissipation in a CMOS inverter? Derive the
expression for switching power dissipation with the help of circuit diagram and
relevant waveforms
Derive expression for i) VIH ii) VIL and ii) Vth of a CMOS inverter.
Draw the CMOS implementation of
i) 3 input NOR gate.
Realise the function f= AB’C+A C(DE+A’B) using standard CMOS logic.
Implement the logic function (AB + C(A+D))′ using CMOS logic
Realize an XOR gate using CMOS logic
What is meant by pass transistor logic? What are the differences in transmission
characteristics of NMOS and PMOS transistors?. What are its demerits and how it
can be remedied?
Implement the function u = A’B+AB’ and v = AB+A’B’ using complementary
pass transistor logic.
What is transmission gate?. Explain the structure and working of a transmission
gate. State the advantages of transmission gates.
Implement the following functions using using transmission gate logic.
i) 3 input XNOR gate ii) 3 input XOR gate ii) 4 : 1multiplexer
Implement using nMOS pass transistors.
i) 3 input XNOR gate ii) 3 input XOR gate ii) 4 : 1 multiplexer
.Explain the principle of operation of Dynamic logic (P-E logic) with neat diagram.? What
are the advantages and disadvantages? Compare static and dynamic CMOS
Design a Dynamic CMOS circuit to implement .
Discuss the signal degradation issue that occurs while cascading dynamic logic gates.
How can overcome it by using i) Domino logic ii) NP domino logic?
Design a CMOS domino circuit to implement the expression
i) Y =C(A+B). ii)Y =AB+(C+D)(E+F)+GH
Draw two input domino AND and OR gate.
What is NP domino logic (NORA CMOS Logic)?