PIC

Microcontrollers
 EMBEDDED SYSTEMS
PIC

Peripheral Interface Controller earlier known as “Programmable Intelligent Computer”

PIC is a family of specialized microchips manufactured by Microchip Technology.

Available in 8-bit, 16-bit, and 32-bit.

Processor core, memory and input/output peripherals for interfacing- all integrated on a single
chip.

PIC chips are ideal for implementing task-specific computing functions in embedded systems
such as motor controls, sensors, actuators etc.

8/26/2024
2
 PIC Characteristics

• RISC- Reduced Instruction Set Computer architecture- 33 to 77 instructions

• Harvard Architecture- Separate code and data memory spaces

• Harvard architecture improves instruction fetch speed

• Memory Organization-
• Flash- Program memory
• SRAM and EEPROM- Data memory

• 1 to 80+ general purpose I/O pins

8/26/2024
3
 PIC Characteristics

• Built-in peripherals like Timers, ADC, comparators, PWM, UART, SPI/I2C

• Low power consumption down to nano-watts

• Wide operating voltage range from 1.8V to 5.5V

• Cost efficient and reliable solutions

• Easy to program using MPLAB X IDE and C compilers

8/26/2024
4
 PIC Families

• PIC 10/12/16/18/24/32

• 8-bit, 16-bit, and 32-bit

• In family names, there are suffixes used in between which tell –

• PIC18FXXX – ‘F’ implies Flash Program Memory
• PIC16CXXX – ‘C’ implies EPROM Program Memory
• PIC18LFXXX – ‘LF” implies Low Voltage operation

8/26/2024
5
 8-bit PIC microcontrollers families
Features Baseline Midrange Enhanced Midrange Advanced

PIC12Fxxx,
Families PIC 10, PIC 12, PIC1 6 PIC10, PIC12 PIC 18
PIC16Fxxx

Program Memory Max 3 KB Max 14 KB Max 28 KB Max 128 KB

Data Memory Max 138 Bytes Max 368 Bytes Max 1-5 KB Max 4 KB

Performance 5 MIPS 5 MIPS 8 MIPS 16 MIPS

Addition to midrange
Addition to baseline
•Multiple Peripheral
•8-bit ADC •CAN
•I2C/SPI communication
Features •Internal Oscillator •USB
•PWM •High Performance
•Comparator •ETHERNET
•UART •PWM with

8/26/2024
•10-bit ADC independent Time-
Space
6
 PIC Architecture

8/26/2024
7
 PIC Architecture

1. Memory Structure

• Program Memory

• Data Memory
• RAM
• EEPROM
• Consists of multiple register banks.
• Each bank consists of general-purpose registers and special function registers.

• SFR- Special Function Registers- The special function registers consist of control registers to control different
operations of the chip resources like Timers, Analog to Digital Converters, Serial ports, I/O ports, etc.

8/26/2024
8
PIC Architecture

2. I/O Ports

• PIC16 series consists of five ports, such as Port A, Port B, Port C, Port D, and Port E.

• Port A: It is a 16-bit port, which can be used as an input or output port based on the status of the TRISA register.

• Port B: It is an 8-bit port, which can be used as both an input and output port. 4 of its bits, when used as input, can be
changed upon interrupt signals.

• Port C: It is an 8-bit port whose operation (input or output) is determined by the status of the TRISC register.

• Port D: It is an 8-bit port, which apart from being an I/O port, acts as a slave port for connection to the microprocessor
bus.

• Port E: It is a 3-bit port that serves the additional function of the control signals to the A/D converter.

8/26/2024
9
PIC Architecture

3. Timers

• 3 timers- T0, T1, T2

• Timer 0 and Timer 2 are 8-bit timers

• Time-1 is a 16-bit timer, which can also be used as a counter.

4. A/D Converter

• 10-bit Analog to Digital Converter.

• The operation of the A/D converter is controlled by these special function registers: ADCON0 and ADCON1.

• It requires an analog reference voltage of 5V for its operation.

8/26/2024
10
PIC Architecture
5. Oscillators

• Internal/External oscillators like crystals or RC oscillators.

• The different modes are low-power mode, crystal mode, and the high- speed mode.

• In the case of RC oscillators, the value of the Resistor and Capacitor determines the clock frequency.

• The clock frequency ranges from 30 kHz to 4 MHz.

6. CCP module:

• Capture- It is used to measure the frequency, pulse, or duty cycle of the input pulse..

• Compare- Analog comparator, used to generate a square wave.

• PWM – It is used for different applications like controlling the speed of DC motor, changing the intensity of the LED, generation of
Sine wave, etc.

8/26/2024
11
PIC Architecture

7. Interrupts
• INT0, INT1, and INT2 pins are used for External Interrupt.
• The application of this interrupt is to respond to external events such as button presses, sensor outputs, or
other signals that require immediate attention.

• Positive edge Trigger or Negative Edge Trigger.

8. WDC- Watch-Dog Timer

• Resets the microcontroller in case of any software hang

8/26/2024
12
 PIC 16 Memory Organization
Harvard Architecture- Separate Program and Data Memory

1. Program Memory

• Flash or EPROM

• 13-bit Program counter - can address up to 8k of

program memory.

• 2KB or 4kB or 8kB program memory.

• 2K memory --> 11-bit address

• 4K memory --> 12-bit address

• 4K memory --> 12-bit address

• After reset, the program counter points to 0000 H.

• At interrupt, the program counter points to 0004 H

8/26/2024
13
PIC 16 Memory Organization
Harvard Architecture- Separate Program and Data Memory

2. Data Memory

8/26/2024
14
PIC 16 Memory Organization
Harvard Architecture- Separate Program and Data Memory

2. Data Memory

• The Data Memory is the part of the PIC that the Special Function Registers(SFR) and the General-
Purpose Registers (GPR) are stored.

• The Data Memory is divided into 4 banks, each one having 128 bytes length.

• To access each bank, the RP0 and RP1 bits of the STATUS register needs to be accessed.

• The lower locations of each bank are reserved for the Special Function Registers.

• Above the Special Function Registers are General Purpose Registers, implemented as static RAM.

• The Special Function Registers are used by the CPU and Peripheral functions to control the device
operation.

8/26/2024
15
Status Register
IRP RP1 RP0 TO PD Z DC C

Status Register (STATUS) is a special register that contains various bits providing information about the
current state of the microcontroller.

• C (Carry Flag): This bit is set (C=1) if carry is generated from the MSB during an arithmetic or logical operation.

• DC (Digit Carry): It is set (DC=1) if carry is generated from the lower nibble to upper nibble during an operation.

• Z (Zero Flag): This bit is set (Z=1) if the result of an operation is zero.

• PD (Power-down Bit): When this bit is zero, it indicates that the microcontroller is in a low-power consumption state

• TO (Time-out Bit): This bit is associated with the Watchdog Timer. It is zero if the Watchdog Timer has overflowed.

• RP0 and RP1 (Register Bank Select bits): These bits are used to select one of the four register banks in the RAM.

• IRP: Register Bank Select bit (used for indirect addressing) 0 = Bank 0, 1 1 = Bank 2, 3
8/26/2024
16
 W Register

• 8 bit wide

• Similar to Accumulator

• It contains one of the source operands in any arithmetic and logical

operation.

• It serves as the destination for the result.

8/26/2024
17
 FSR Register
FSR- File Select Register

• It is the pointer used for indirect addressing.

• In the indirect addressing mode, the 8-bit register file address is first written into FSR.

• INDF- Indirect File Register Instruction- access the register pointed to by the FSR.

• E.g.
• Register file 05 contains the value 10h
• Register file 06 contains the value 0Ah
• Load the value 05 into the FSR register
• A read of the INDF register will return the value of 10h
• Increment the value of the FSR register by one (FSR = 06)

18
• A read of the INDF register now will return the value of 0Ah.
8/26/2024
 Addressing Modes

1. Immediate addressing mode

2. Register operand addressing mode

4. Direct addressing

5. Indirect addressing.

8/26/2024
19
 Addressing Modes
1. Immediate Addressing Mode-

• The immediate data is specified in the instruction.

• The immediate addressing mode is used to load the data into PIC registers and W register.

• E.g MOVLW 32H (Move literal specified immediately in instruction to working register W).

2. Register Operand Addressing Mode-

• Operand is a Register which holds the data to be executed.

• E.g. CLR W

8/26/2024
20
 Addressing Modes

3. Direct Addressing Mode-

• Direct addressing is done through a
9-bit address. Selected Bank

• This address is obtained by

connecting 7 bits of direct address of
an instruction with two bits (RP1,
RP0) from STATUS register. Selected Location

8/26/2024
21
 Addressing Modes

4. Indirect Addressing Mode-

• Derives address from IRP bit of STATUS and

FSR registers.
Selected Bank
• Addressed location is accessed via INDF
register which in fact holds the address
Selected Location
indicated by FSR.

• Any instruction which uses INDF as its register,

accesses data indicated by a FSR register.

8/26/2024
22
 ARM
Microcontrollers

8/26/2024
23
 Overview of ARM

• ARM- Advanced RISC Machine

• Founded in November 1990- Acorn Computers
• Designs the ARM range of RISC processor cores
• Licenses ARM core designs to semiconductor partners who fabricate and sell to their
customers.
o ARM does not fabricate silicon itself
• Develop technologies to assist with the design-in of the ARM architecture
o Software tools, boards, debug hardware, application software, bus architectures,
peripherals etc
8/26/2024
24
8/26/2024
25
 RISC Design Rules
1. Instructions 3. Registers
o Reduced Number of Instructions o Have a large general-purpose register set
o Execute in a single cycle o Any register can contain either data or
o Each instruction is a fixed length address

2. Pipelining 4. Load-Store Architecture

o Parallel Processing- Executing multiple o Separate load and store instructions
instructions at a time.
transfers data between the register bank
o The processing of instructions is broken and external memory
down into smaller units that can be executed
in parallel by pipelines.
8/26/2024
26
 ARM Features

• RISC architecture

• 32-bit general purpose processor

• High performance , low power consumption and small size

• Large Register File

• Load/store architecture

• Pipelining – 3 stage (Fetch-Decode-Execute) or 5 stage (Fetch-Decode-Execute-Memory-Write)

• Uniform and fixed-length(32 bit) instruction-(ARM)

• 32-bit ARM Instruction Set and 16-bit Thumb Instruction Set that improves code density by about 30%
8/26/2024
27
 ARM Features
• Jazelle cores – For executing 8-bit Java bytecode

• Inline barrel shifter

o hardware component that preprocesses one of the input registers before it is used by an instruction

o expands the capability of many instructions to improve core performance and code density

• Conditional execution
o Instruction is only executed when a specific condition has been satisfied, so improves performance and code
density by reducing branch instructions

• Enhanced instructions
o Enhanced digital signal processor (DSP) instructions were added to the standard ARM instruction set to support

28
fast 16×16-bit multiplier operations
8/26/2024
 • Arithmetic Logic Unit-
ARM o The ALU performs all the arithmetic and logical
Architecture operations of the processor.
o The ALU receives two 32-bit inputs, one from a register
and other from the shifter.
o The ALU can alter the status flag according to the
results of the operation it performed.

• Barrel shifter-
o The barrel shifter is a functional unit which can perform
five different kinds of shift and rotate operation:
▪ Logical left shift, Logical right shift, Arithmetic shift right,
Rotate right and Rotate right extended.

8/26/2024
29
 ARM Architecture
• Booth multiplier-
o 32 bit booth multiplier for multiplication.
o Booth’s algorithm is a multiplication algorithm that multiplies two signed binary numbers in 2’s complement
notation.

• Control unit-
o The control unit sends control signals to different components of the processor to control their operations.

• Register file-
o There are two types of registers – General purpose registers and Special Function Registers (GPR and SFRs)
o GPRs are used to store user data or address
o Special purpose registers which control the processor functionalities and manage I/O operations.
8/26/2024
30
 ARM Vs x86
Aspect ARM x86
Architecture RISC CISC
Power Efficiency More Less
Pipelining Present, More efficient Less efficient
Execution Speed Fast Slower than ARM
Performance Optimization Software Focused Approach Hedware Focused Approach

Design Simple Hardware, Complex Compiler Complex Hardware, Simple

Compiler
Market Presence Dominant in Mobile devices and IoT Desktops, Laptops

8/26/2024
31
 ARM Operating Modes

• The ARM has

seven basic
operating
modes.

• Each mode has

access to own
stack and a
different subset
of registers.

8/26/2024
32
 ARM Registers
• ARM has 37 registers, each register is 32 bits in size

• 16 data registers (r0 to r15)and 2 processor status registers-

o cpsr – Current Program status register
o Spsr- Saved Program status register

• Register r13 -Stack pointer (sp)- stores the top of the stack in the
current processor mode.

• Register r14 - Link register (lr) - stores return address after

a subroutine.

• Register r15- Program counter (pc) and contains the address of the
next instruction to be executed.

• Registers r0 to r13 are orthogonal—any instruction that can apply

to r0, can equally well apply to any of the other registers

8/26/2024
33
Program
Status
Register

8/26/2024
34
 • Pipelining- Execution of multiple instructions at the
3 Stage same time.

Pipelining in • Parallel Processing- The processing of instructions is

broken down into smaller units that can be executed in
ARM parallel by pipelines.

• There are three stages in this pipeline method:

o Fetch – The instruction is fetched from the memory
and stored in the instruction register.
o Decode – The instruction is moved to the decoder
which decodes the instruction. It activates the
appropriate control signals and takes the
necessary steps for the the next execution stage.
o Execute – The instruction is executed. Data
transfer, logical and arithmetic operations all take
place during this stage.

8/26/2024
35
 3 Stage Pipelining in ARM
• Pipelining Benefits-
o In a microprocessor without pipe lining, each simple instruction takes three cycles to complete.
o And only when one instruction execution is complete, another instruction is fetched.
o But in three stage pipe lining, as soon as the instruction fetch of one instruction is over, the next
instruction is fetched.
o The different stages of the consecutive instructions happen simultaneously increasing the
throughput and operational speed.

8/26/2024
36