| DeMario e we CMEC ME emer CT CMS Rolie VAS l= a=] respectively. The instruction SUB Ry, R2 is in memory location 6000 H. If the size of an instruction is 8 bytes, then after the execution of the instruction the value of PC and R; will be Mx, Ra=ja cae oe SS Baebes Ss) i “ Gone bv F] (eae he TE ey a Beer eed Cc) Tee ee hg (2) D } PC = 6000 H, Ri=5hte) (Ce PURPA A PM MUU eet MELEE Srocem-auoulem melee Ayam sm PliceMmoneleuMmOeuriarrtel memory is byte addressable. The value of byte stored at location 2023 Hand 2025 H. trey ae) ey Te rae A) en 2 EOTn aN c} 32 and FA D } RYETORO) wis)vy is Pe ow eee are WMC Oe eee gece Sew ON we WUC een ook eL eee eC OM ONE korn ae Ont la POMPOM E Care mU Naat mH eceCRu eee aul ie am Cees Cl le into register Rx. To maximize the range of the direct addressing field (Addr), you Pate Biber. ke et eee PAR er a Oe er ReCRU IMT BE tne of bits required. How many it a the LDI instruction___? ; — A aaa ees . sco) < Ja - ss eae coe Gait) omc] tebleor fill = [6-15 42) = @hib Sor “Sb ror| So MUL elec TES e aT Coe (Oem CO)etiL LOM UEC Volt Te Moca eC Co) fo Saee merce ao ierotonea ee mu ea atten rs PUSH 20; PUSH 5; i 5; ADD; ADD; PUSH 20; MULTIPLY 8 (600) tisiNAT] Consider a system which has 2048 k words. Each word has the ==] size of 32 bits then what is the capacity of memory in MB (Mega Byte) PT a aoe Word = 32-bit paces yay Sac) 2 BIRhte) Consider the following table for two systems A and B: Brod prawn io Bee Bic Pra) x and y are number of bits used ey ne he memory location in system A and B respectively. Value of x andy El . oa B ey eR | ce ic) ee ys CD) x= 34,y=34 fo)S| Ae eure eRy Alem elaeeunaues STC ee eRe ICC a Ce oem ECB Mens mylar) PS eeRe MET ate eyaa Ce) Zero flag(z): If the result of any arithmetic or logical operation is zero i.e. ER Ce ee oeek ei ee a Oe eo era e Anes Auxiliary carry: (AC) this flag is set to 1 only when a carry is produced peepee Carry flag(C): This flag is set to 1 only when any intermediate carry is produced. Else it is reset to 0EN) The memory location 100 to 110 have data value from 1 to 11 in sequence Peace RC eee ee ee Ree ee A COM AIR ec eth Cai Consider the following two address instructions. Se Cees oon eee Dee Se ae eee eee Ae SE The value of Ls after executing Sr sequence of instructions, seven times is _. ery Cty er 24 3&3) re 5 LS ee) eto} Cat) Coan] i Cree hal im ne : joorteZzt¥h St 6+ 748 107 7 c t B (1035) ) ; i aan iil ilCa) es Suppose we execute the following MIPS instructions 1. Loadi; Temp0, 2 // 2-Temp0 nliled Pareto a enracioe eter EMM eRe) //Set Temp Ta ean ian 4. BEQ pny 5 7/ if Temp2 = RO then skip ion) == °) Bea oe 5. ADDi: Temp1, Tenis 3//Temp1 = Temp2+3 (ee [Link]; R4, 42 E>) Assume that RO _ initialized om is the value of register Temp1 after completion of the code? O° nam oO CB 0SY Consider the following Program Segment for a hypothetical CN. oG Instruction Meaning Instruction size (in words) Pe) PTE] 3 oxy ¢ [5-17 Payee) RATE Ee vine rar 1 Ry yp = ld any TC Ee en ny Rrrereen ers an | PPtaeita Cle aye eee aOR meee selene are PRsea eeu Cone a Pes creme oe 9 SRR) TTP MaTele Me) oLedaevile Recon Beem. fo Register to/from memory transfer: 5 clock cycle NTC sm Ka Cle eae ee mCm can Chae isms | ABO)[NAT] Ad Consider the follow Tne LYE Sen OR se Lee ee Ort) SAADD R2, RO, RO Aen SADDI R3, RO, #254 Re 25¢]// R3 — RO+ 256 ee 5,Loop: MUL R1, R1,# ieee WAGs Sa ea) Eva vase heen as CRE” oe NE R2, R3, Th reer =<. fut ors EB) Pet ca al How many instructions are executed dynamically to complete the above (oto) (od Pe rca Wy] ore) aa Teoayy ELON U CM ehyolelei ite MO MOM ICS ea Oo eLOLUcRe CCCI MeCN EM eee a RISC instruction set architecture. Instruction is stored in the memory location with starting address of 2000 decimal on-words. oak oman) aay Pty OUR CU ee mest mig , Ry = er) ts = 50, R, = 60 respectively. What is the memory Pees (in decimal) ri Tees ae mem eo canic| 5)TW 56 Consider the following code: LoadiRO,9 %&=9 //\oad immediate Loadi R4,0 %&= 2 WU ACeGu tse) Loadi R3,3 fa=3 PACs ea AVE n Te ela nee Addi RO, RIE ro 1th ena GCI Se eres cecal 5) //R3 — R3+-1 Jump Loop Exit: Store RO, F al The value of memory location F at the end of the program will caeey aa) is) aPsoo — Co ee ce Fost, ae a oer Cait ST ed rats PoeS| Which information is/are not correct? A) Sign flag(s): If sign bit is 1 then the sign flag is set to 1 and if the sign bit is PoeeR eMC Ta Sea Cian oad rB Zero flag(z): If the result of any arithmetic or logical operation is zero i.e. El Ree ee ween mE ete eee ee ete ace) ra eee Auxiliary carry: (AC) this flag is set to 1 only Poni eae ie Rea BOC a Carry flag(C): This flag is set to 1 only when any intermediate carry is pyaeel (acre ee eee Cnt) hy ()2(0)bite) Pry Consider 64 bit hypothetical CPU which support 256 KB Pett. =] space processer is enhanced with word addressable memory. OMAN CUM Coe UME Wet BE e RO men ene Pitan eee i aybite) How many 128x8 bit RAMs are required to design 32K x 32 bit RAM? ® Se ° ° 512 ste 128 Ky 96 a Cope 1 ae ace CA Po Caen ae era oan Eas a es oyNey To execute a program, instructions has to be brought from memory using bus to CPU. If the bus has 8 lines then almost one 8-bit (1byte) can be transferred at a time. The how many memory access are required in this cases to transfer a 32 bit instruction from memory to the CPU? a Ae eaten Ae ane OER Ba an ans ‘es -@ hs,[McQ] OE (emer u ney oG S,: In little endian, lower address contain lower byte and higher address contain higher byte. PH Bre oe MOC ome le ele ree eB om ce Tuto address contain lower byte. S° Only S, is true Ceara eee coe re Tee NOTH rm anes Catalbt) Consider the statements AH AH Accumulator Stores the results of calculations made by ALU. Program counter keeps track of the memory location of the current instruction by which process is currently dealing with. eT eal Only S, is true Ceara eee coe re Tee NOTH rm anes CatalS| Which of the statements is/are true? hed Saat Memory address register stores the memory locations in instruction that needed to be fetched from memory. Memory data register stores the instruction fetched from memory or any data that is to be transferred to and stored in PCN Instruction register stores the most recently fetched instruction. Instructions buffer register contains the instruction which are not to be executed immediately.VV] PSOE SYA ied Ra a with 1 word long instruction. It has 25 register, eac cy oe dina is 32 bits long. Machine support_450 i rie Sint Ao EN an immediate operand in addition to two register SCCM Cm Berm oe ORE unsigned integer. Then the maximum value of the a immediate operand is (81q)hy sd we lo Ptape| fe) [Rege | Trnenaticle Ca kat a as”INAT] ee SURO mang Ree Ree PET 4000 respectively. The memory location 2000 and 4000 have data values 10 and 20 respectively. Consider the following instructions. ar — PNB Oem On displacement addressing Re eae +@) Add Ro, Ro, (Ri) ; Register Indirect eC) SUC e Me OmrT Como Cantar len Moms rianas (ein mae rey nee ice ee) |ET ee es mae eee kee Perry fering errr) Pr Poo) 1, MOV ro, 9000_| fo M[9000] 5 PAYNE ck OO i Ey i ee Sel 1, MOV 13000, ro | M[13000] «ro Cee eS eiod ee et peo Instruction Fetch and Decode: 2 clock cycle per word MUL with both operand and stored in Register: 3 eto Register to/From memory transfer: 4 clock cycle The total number of clock cycle required to execute Pens ; Ass (37) hi