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Exp 09

The document outlines an experiment to design a 2-input XOR gate using VHDL, detailing the theory behind XOR gates, their truth table, and the necessary apparatus. It includes the VHDL program and test bench code, demonstrating successful simulation results that matched the expected behavior of an XOR gate. The experiment enhances understanding of digital circuit modeling and testing with hardware description languages.

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jacjon703
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2 views3 pages

Exp 09

The document outlines an experiment to design a 2-input XOR gate using VHDL, detailing the theory behind XOR gates, their truth table, and the necessary apparatus. It includes the VHDL program and test bench code, demonstrating successful simulation results that matched the expected behavior of an XOR gate. The experiment enhances understanding of digital circuit modeling and testing with hardware description languages.

Uploaded by

jacjon703
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

EXPERIMENT NO: 09

NAME OF THE EXPERIMENT: Write a VHDL program to design a XOR Gate.


OBJECTIVE: To design a 2 input XOR Gate.
THEORY:
An XOR (Exclusive OR) gate is a digital logic gate that outputs true (1) only when an odd
number of inputs are true. For a two-input XOR gate, the output is high (1) if one input is high
and the other is low. If both inputs are the same—either 0 or 1—the output is low (0). The
Boolean expression for a two-input XOR gate is Y = A ⊕ B, where A and B are inputs. XOR
gates are commonly used in arithmetic circuits, such as adders and parity checkers, due to their
ability to detect differences between inputs. They are essential in applications involving
comparison, addition, and conditional logic.
Truth Table:
A B Y

0 0 0

0 1 1
Figure 1. XOR Gate
1 0 1

1 1 0

APPARATUS REQUIRED: Computer with Vivado Xilinx software.

VHDL PROGRAM TO DESIGN 2-INPUT XOR GATE:


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity XOR_gate is
Port (
A, B : in STD_LOGIC;
XOR_Output : out STD_LOGIC );
end XOR_gate;
architecture Behavioral of XOR_gate is
begin
XOR_Output <= A xor B;
end Behavioral;
TEST BENCH CODE OF XOR GATE:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity XOR_gate_tb is
end XOR_gate_tb;
architecture Behavioral of XOR_gate_tb is
signal A, B, XOR_Output : STD_LOGIC;
begin
UUT: entity work.XOR_gate
port map ( A => A,B => B,XOR_Output =>
XOR_Output );
stim_proc: process
begin
A <= '0';B <= '0';wait for 10 ns;
A <= '0';B <= '1';wait for 10 ns;
A <= '1';B <= '0';wait for 10 ns;
A <= '1';B <= '1';wait for 10 ns;
end process;
end Behavioral;

OUTPUT:

Figure 2. Schematic Diagram of XOR Gate.


Figure 3. Output Waveform of XOR Gate.

RESULTS & DISCUSSIONS:


The VHDL program for the XOR gate was successfully written, compiled, and simulated using
a VHDL simulation tool. The simulation results matched the expected truth table of an XOR
gate, where the output was high (1) only when the inputs were different. Various input
combinations were tested, and the output accurately reflected XOR logic behavior. This
experiment enhanced understanding of basic logic gate implementation using VHDL. It also
demonstrated how hardware description languages can be used to model and test digital circuits
effectively. The successful simulation confirmed the correctness of the code and the
functionality of the designed gate.
PRECAUTIONS:
i. The VHDL code was written correctly.
ii. The code was run when it checked completely.
iii. The output was observed thoroughly.

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