REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

IFET COLLEGE OF ENGINEERING

(An Autonomous Institution)
(Common to CSE, IT, AI&DS & AI&ML)

Subject Code/ Name: 23EC2302- Digital Principles and Computer Organization

Year/Sem: I/ II

UNIT III COMPUTER ARITHMETIC & ADDRESSING

Basic Functional Units and Bus Structures - Instruction execution cycle, Performance: Metrics for
Performance Measurement - Algorithms for fixed point and floating-point addition- subtraction-
multiplication and division operations and its hardware – Various Addressing Modes- Instruction
Formats- Basic Machine Instructions.

3.0 INTRODUCTION
This unit covers fundamental aspects of computer architecture, including the basic functional units and
bus structures, the instruction execution cycle, performance metrics, algorithms for fixed-point and
floating-point arithmetic operations, addressing modes, instruction formats, and basic machine
instructions.

3.1 INTRODUCTION TO COMPUTER ARCHITECTURE

 A computer is a machine that can be instructed to carry out sequences of arithmetic or logical
operations automatically via computer programming.
 In computer, the CPU executes each instruction provided to it, in a series of steps; this series of
steps is called Machine Cycle, and is repeated for each instruction.
 One machine cycle involves fetching of instruction, decoding the instruction, transferring the data,
executing the instruction.
 A computer organization describes the functions and design of the various units of a digital system.
 A general-purpose computer system is the best-known example of a digital system. Other examples
include telephone switching exchanges, digital voltmeters, digital counters, electronic calculators
and digital displays.
Computer architecture
 Computer architecture deals with the specification of the instruction set and the hardware units that
implement the instructions.
 Computer hardware consists of electronic circuits, displays, magnetic and optic storage media and
also the communication facilities.
3.2 BASIC FUNCTIONAL UNITS
 Functional units are a part of a CPU that performs the operations and calculations called for by the
computer program.
 Functional units of a computer system are parts of the CPU (Central Processing Unit) that performs
the operations and calculations called for by the computer program.
 Computer system has five basic units that help the computer to perform operations, which are given
below (Figure 3.1):
REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

 Input Unit
 Output Unit
 Storage Unit
 Arithmetic Logic Unit (ALU)
 Control Unit
Input device
 Input units are used by the computer to read the data. The most commonly used input devices are
keyboards, mouse, joysticks, trackballs, microphones, etc.
 However, the most well-known input device is a keyboard. Whenever a key is pressed, the
corresponding letter or digit is automatically translated into its corresponding binary code and
transmitted over a cable to either the memory or the processor.
 Input unit connects the external environment with internal computer system. It provides data and
instructions to the computer system. Commonly used input devices are keyboard, mouse, magnetic
tape etc.
 Input unit performs following tasks:
 Accept the data and instructions from the outside environment.
 Convert it into machine language.
 Supply the converted data to computer system.

Fig.3.1 Basic functional units of a computer

Central processing unit
 It is Central Processing Unit of the computer. The control unit and ALU are together known as
CPU. CPU is the brain of computer system. It performs following tasks:
 It performs all operations.
 It takes all decisions.
 It controls all the units of computer.
REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

 Central processing unit is an electronic circuitry within a computer that carries out the instructions
given by a computer program by performing the basic arithmetic, logical, control and input/output
(I/O) operations specified by the instructions.
Memory unit
 The Memory unit can be referred to as the storage area in which programs are kept which are
running, and that contains data needed by the running programs.
 The Memory unit can be categorized in two ways namely, primary memory and secondary memory.
 It enables a processor to access running execution applications and services that are temporarily
stored in a specific memory location.
 Primary storage is the fastest memory that operates at electronic speeds. Primary memory contains
a large number of semiconductor storage cells, capable of storing a bit of information. The word
length of a computer is between 16-64 bits.
 It is also known as the volatile form of memory, means when the computer is shut down, anything
contained in RAM is lost.
 Cache memory is also a kind of memory which is used to fetch the data very soon. They are highly
coupled with the processor.
 The most common examples of primary memory are RAM and ROM.
 Secondary memory is used when a large amount of data and programs have to be stored for a long-
term basis.
 It is also known as the Non-volatile memory form of memory, means the data is stored permanently
irrespective of shut down.
 The most common examples of secondary memory are magnetic disks, magnetic tapes, and optical
disks.
Arithmetic & logical unit
 Most of all the arithmetic and logical operations of a computer are executed in the ALU (Arithmetic
and Logical Unit) of the processor. It performs arithmetic operations like addition, subtraction,
multiplication, division and also the logical operations like AND, OR, NOT operations.
Control unit
 The control unit is a component of a computer's central processing unit that coordinates the
operation of the processor. It tells the computer's memory, arithmetic/logic unit and input and output
devices how to respond to a program's instructions.
 The control unit is also known as the nerve center of a computer system.
 Let's us consider an example of addition of two operands by the instruction given as Add LOCA,
RO. This instruction adds the memory location LOCA to the operand in the register RO and places
the sum in the register RO. This instruction internally performs several steps.
Output Unit
 The primary function of the output unit is to send the processed results to the user. Output devices
display information in a way that the user can understand.
 Output devices are pieces of equipment that are used to generate information or any other response
processed by the computer. These devices display information that has been held or generated
within a computer.
 The most common example of an output device is a monitor.
REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

3.3 BUS STRUCTURES

Bus
 A bus is a communication pathway connecting two or more devices. A key characteristic of a bus
is that it is a shared transmission medium.
 Multiple devices connect to the bus, and a signal transmitted by any one device is available for
reception by all other devices attached to the bus. If two devices transmit during the same time
period, their signals will overlap and become garbled. Thus, only one device at a time can
successfully transmit.
 Typically, a bus consists of multiple communication pathways, or lines. Each line is capable of
transmitting signals representing binary 1 and binary 0. Over time, a sequence of binary digits can
be transmitted across a single line. Taken together, several lines of a bus can be used to transmit
binary digits simultaneously (in parallel).
 For example, an 8-bit unit of data can be transmitted over eight bus lines. Computer systems contain
a number of different buses that provide pathways between components at various levels of the
computer system hierarchy. A bus that connects major computer components (processor, memory,
I/O) is called a system bus. The most common computer interconnection structures are based on
the use of one or more system buses.
 A system bus consists, typically, of from about fifty to hundreds of separate lines. Each line is
assigned a particular meaning or function. Although there are many different bus designs, on any
bus the lines can be classified into three functional groups: data, address, and control lines. In
addition, there may be power distribution lines that supply power to the attached modules.

Fig.3.2 Bus interconnection schemes

Functional groups of bus (Figure 3.2)
Data lines (data bus) - The data lines provide a path for moving data among system modules. These lines,
collectively, are called the data bus.
Address lines (address bus) - The address lines are used to designate the source or destination of the data
on the data bus.
Control lines (control bus) - The control lines are used to control the access to and the use of the data and
address lines.
Because the data and address lines are shared by all components, there must be a means of controlling their
use. Control signals transmit both command and timing information among system modules. Timing
REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

signals indicate the validity of data and address information. Command signals specify operations to be
performed. Typical control lines include:
Memory write: causes data on the bus to be written into the addressed location.
Memory read: causes data from the addressed location to be placed on the bus.
I/O write: causes data on the bus to be output to the addressed I/O port.
I/O read: causes data from the addressed I/O port to be placed on the bus.
Transfer ACK: indicates that data have been accepted from or placed on the bus.
Bus request: indicates that a module needs to gain control of the bus.
Bus grant: indicates that a requesting module has been granted control of the bus.
Interrupt request: indicates that an interrupt is pending.
Interrupt ACK: acknowledges that the pending interrupt has been recognized.
Clock: is used to synchronize operations.
Reset: initializes all modules.
Bus Structures
 A bus is a group of lines that serves as a connecting path for several devices.
 A bus may be lines or wires.
 The lines carry data or address or control signal.
There are 2 types of bus structures:1) Single bus structure and 2) Multiple bus structure.
1) Single bus structure (Figure 3.3)
 Bus can be used for only one transfer at a time; only 2 units can actively use the bus at any given
time.
 Bus control lines are used to arbitrate multiple requests or use of the bus.

Fig.3.3 Single bus structure

Advantages:
1. Low cost.
2. Flexibility for attaching peripheral devices.
2) Multiple bus structure (Figure 3.4)
 Systems that contain multiple buses achieve more concurrency in operations.
 Two or more transfers can be carried out at the same time.
Advantages: Better performance.
Disadvantages: Increased cost.
REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

Fig.3.4 Multiple bus structure

3.4 INSTRUCTIONS
 The primary function of a computer system is to execute a program, sequence of instructions. These
instructions are stored in computer memory.
 These instructions are executed to process data which are already loaded in the computer memory
through some input devices.
 After processing the data, the result is either stored in the memory for further reference, or it is sent
to the outside world through some output port.
 The computer works based on some given instruction. Let us consider an example:
Add LOCA, R0
This instruction adds the operands at memory location LOCA to the operand in the register R0 and places
the sum into the register [Link] seems that this instruction is done in one step, but actually it internally
performs several steps
First, the instruction is fetched from the memory into the processor. Next, the operand at LOCA is fetched
and added to the contents of [Link] above instruction can be written also as-
Load LOCA, R1
Add R1, R0

3.4.1 INSTRUCTION REPRESENTATION

Instructions are kept in the computer as a series of high and low electronic signals and may be
represented as numbers. In Fact, Each piece of an instruction can be considered as an individual number,
and placing these numbers side by side forms the instruction.
Since registers are referred to in instructions, there must be a convention to map register names into
numbers. In MIPS assembly language, registers $s0 to $s7 map onto registers 16 to 23, and registers $t0 to
$t7 map onto registers 8 to 15. Hence, $s0 means register 16, s1 means register 17, $s2 means register
18,…., $t0 means register 8, $t1 means register 9, and so on.
Instruction format
 Instruction format is a form of representation of an instruction composed of fields of binary numbers
Machine language
 Assembly language instruction use exactly 32 bits and the same size as a data word.
 All MIPS instructions are 32 bits long so need to focus some numeric version of instruction called
machine language.
REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

 Machine language is a binary representation used for communication within a computer system.
 Instructions used in machine language are called machine code.

Hexadecimal number
 Computer can use binary numbers to read and write data. In binary number format for small value
also it requires large amount of bits.
 So can use higher base that can be easily converted into binary.
 All computer data sizes are multiples of 4, in that hexadecimal numbers are popular.
 Base value of hexadecimal number is 16 and it is the power of 2.
 So can convert by replacing each group of four binary digits by a single hexadecimal digit and vice
versa.
 To avoid confusion between various numbers, can use subscript values for example Decimal
numbers with ten, Binary numbers with two, and Hexadecimal numbers with hex (Table 3.1). (If
there is no subscript, the default is base 10.)

Table 3.1 Hexadecimal to binary conversion

Hexadecimal Binary Hexadecimal Binary
0hex 0000two 8 hex 1000 two
1 hex 0001 two 9 hex 1001 two
2 hex 0010 two A hex 1010 two
3 hex 0011 two B hex 1011 two
4 hex 0100 two C hex 1100 two
5 hex 0101 two D hex 1101 two
6 hex 0110 two E hex 1110 two
7 hex 0111 two F hex 1111 two

MIPS Fields
1. R- Format

op Rs Rt rd Shamt funct
6 bit 5 bits 5 bits 5 bits 5 bits 6 bits
• op: Basic operation of the instruction, traditionally called the opcode.
• rs: The first register source operand.
• rt: The second register source operand.
• rd: The register destination operand. It gets the result of the operation.
• shamt: Shift amount.
• funct: Function. This field, often called the function code, selects the specific variant of the
operation in the op field.
2. I- Format
Op Rs Rt Constant address
6 bits 5 bits 5 bits 16 bits
 Used by the immediate and data transfer instructions.

Today’s computers are built on two key principles:

1. Instructions are represented as numbers.
2. Programs are stored in memory to be read or written, just like data (Figure 3.5).
REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

Fig. 3.5 Stored-program concept

3.4.2 INSTRUCTION SET ARCHITECTURE OF A CPU

Instruction and Instruction set
The words of a computer’s language are called instructions, and its vocabulary is called an instruction Set.
Instruction format
The layout of the instruction is called the instruction format.
MIPS
MIPS (originally an acronym for Microprocessor without Interlocked Pipeline Stages) is a reduced
instruction set computer (RISC) instruction set (ISA) developed by MIPS technologies. A measurement of
Program execution speed based on the number of millions of instructions. MIPS is computed as the
instruction count divided by the product of the execution time and 106
𝐼𝑛𝑠𝑡𝑟𝑢𝑐𝑡𝑖𝑜𝑛𝑐𝑜𝑢𝑛𝑡
𝑀𝐼𝑃𝑆 =
𝐸𝑥𝑒𝑐𝑢𝑡𝑖𝑜𝑛𝑡𝑖𝑚𝑒 × 106

The relationship between MIPS, Clock rate and CPI:

By Substituting Execution time:
𝐼𝑛𝑠𝑡𝑟𝑐𝑢𝑡𝑖𝑜𝑛𝑐𝑜𝑢𝑛𝑡 𝐶𝑙𝑜𝑐𝑘𝑟𝑎𝑡𝑒
𝑀𝐼𝑃𝑆 = =
𝐼𝑛𝑐𝑠𝑡𝑢𝑐𝑡𝑖𝑜𝑛𝑐𝑜𝑢𝑛𝑡 × 𝐶𝑃𝐼 𝐶𝑃𝐼 × 106
𝐶𝑙𝑜𝑐𝑘𝑟𝑎𝑡𝑒

Three popular instruction set

1. ARMv7 is similar to MIPS. More than 9 billion chips with ARM processors were manufactured in
2011, making it the most popular instruction set in the world.
2. The second example is the Intel x86, which powers both the PC and the cloud of the PostPC Era.
3. The third example is ARMv8, which extends the address size of the ARMv7 from 32 bits to 64 bits.
Ironically, as we shall see, this 2013 instruction set is closer to MIPS than it is to ARMv7.
An instruction set is a group of commands for a CPU in machine language. The term can refer to all possible
REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

instructions for a CPU or a subset of instructions to enhance its performance in certain situations.
The instruction set provides commands to the processor, to tell it what it needs to do. The instruction set
consists of addressing modes, instructions, native data types, registers, memory, interrupt and exception
handling, and external I/O.
Examples of instruction set are
ADD- Add two numbers together.
COMPARE- Compare numbers.
IN- Input information from a device, e.g., keyboard.
JUMP- Jump to designated RAM address.
JUMP IF- Conditional statement that jumps to a designated RAM address.
LOAD- Load information from RAM to the CPU.
OUT- Output information to device, e.g., monitor.
STORE- Store information to RAM
CPU Organization
i) Single Accumulator
 Result usually goes to the Accumulator
 Accumulator has to be saved to memory quite often
ii) General Register
 Registers hold operands thus reduce memory traffic
 Register bookkeeping
iii) Stack
 Operands and result are always in the stack
Basic Instruction Types
There are five types of instruction formats in a computer that are commonly used, namely:
1. Three-address instruction format.
2. Two-address instruction format.
3. one-address instruction format.
4. Zero-address instruction format.
5. One-and-half address instruction format.
Number of operands
Instruction sets may be categorized by the maximum number of operands explicitly specified in
instructions.
0- operand (zero-address machines), so called stack machines: All arithmetic operations take place using
the top one or two positions on the stack: push a, push b, add, pop c
1- operand (one-address machines), so called accumulator machines, include early computers and many
small microcontrollers: most instructions specify a single right operand (that is, constant, a register, or a
memory location), with the implicit accumulator as the left operand (and the destination if there is one):
load a, add b, store c.
2- operand- many CISC and RISC machines fall under this category:
CISC - move A to C; then add B to C.
RISC - Requiring explicit memory loads, the instructions would be: load a, reg1; load b, reg2; add reg1,
reg2; store reg2, c.
3- operand- It allows better reuse of data:
REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

CISC - It becomes either a single instruction: add a, b, c

CISC - Machines limited to two memory operands per instruction, move a, reg1; add reg1, b, c;
RISC - arithmetic instructions use registers only, so explicit 2-operand load/store instructions are
needed: load a, reg1; load b, reg2; add reg1+reg2->reg3; store reg3, c;
Complex instruction set computing (CISC)
CISC is a CPU design where single instructions can execute several low level operations (such as a load
from memory, an arithmetic operation, and a memory store) or capable of multi-step operations or
addressing modes within single instructions.
Reduced Instruction Set Computers (RISC)
It is a microprocessor that is designed to perform a smaller number of types of computer instruction so that
it can operate at a higher speed.
Two key characteristics of RISC instruction sets are:
1. Each instruction fits in a single word.
2. A load/store architecture is used, in which
 Memory operands are accessed only using Load and Store instructions.
 All operands involved in arithmetic or logic operation must either be in processor registers, or one
of the operands may be given explicitly within the instruction word.
At the start of execution of a program, all instructions and data used in the program are stored in the memory
of a computer. Processor registers do not contain valid operands at that time. If operands are expected to
be in processor registers before they can be used by an instruction, then it is necessary to first bring these
operands into the registers. This task is done by Load instructions which copy the contents of a memory
location into a processor register. Load instructions are of the form
Load destination, source
(Or)
Load processor_register, memory_location
Let us now consider a typical arithmetic operation. The operation of adding two numbers is a fundamental
capability in any computer. The statement
C=A+B
In high-level language program instructs the computer to add the current values of the two variables called
A and B, and to assign the sum to a third variable, C. When the program containing this statement is
compiled, the three variables, A, B, and C, are assigned to distinct locations in the memory. For simplicity,
Refer to the addresses of these locations as A, B, and C respectively. The contents of these locations
represent the values of the three variables. Hence, the above high-level language statement requires the
action to take place in the computer.
C ← [A] + [B]
To carry out this action, the contents of memory locations A and B are fetched from the memory and
transferred into the processor where their sum is computed. This result is then sent back to the memory and
stored in location C.
The required action can be accomplished by a sequence of simple machine instructions. Choose to use
registers R2, R3, and R4 to perform the task with four instructions:
Load R2, A
Load R3, B
Add R4, R2, R3
REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

Store R4, C
Add is a three-operand, or a three-address, instruction of the form
Add destination, source1, source2
The Store instruction is of the form
Store source, destination
where the source is a processor register and the destination is a memory location. Observe that in the Store
instruction the source and destination are specified in the reverse order from the Load instruction; this is a
commonly used convention.
The desired addition by using only two registers, R2 and R3, if one of the source registers is also used as
the destination for the result. In this case the addition would be performed as
Add R3, R2, R3 and the last instruction would become
Store R3, C
Advantages
Speed- RISC processors often achieve 2 to 4 times the performance of CISC processors using comparable
semiconductor technology and the same clock rates.
Simpler hardware- Because the instruction set of a RISC processor is so simple. It uses up much less chip
space and simple hardware requirements.
Shorter design cycle- Since RISC processors are simpler than corresponding CISC processors, they can
be designed more quickly, and can complete their work in 1 clock cycle

3.4.3 INSTRUCTION EXECUTION CYCLE

An instruction cycle, also known as fetch-decode-execute cycle is the basic operational process of a
computer (Figure 3.6). This process is repeated continuously by CPU from boot up to shut down of
computer.
Following are the steps that occur during an instruction cycle:
1. Fetch the Instruction
The instruction is fetched from memory address that is stored in PC (Program Counter) and stored in the
instruction register IR. At the end of the fetch operation, PC is incremented by 1 and it then points to the
next instruction to be executed.
2. Decode the Instruction
The instruction in the IR is executed by the decoder.
3. Read the Effective Address
If the instruction has an indirect address, the effective address is read from the memory. Otherwise operands
are directly read in case of immediate operand instruction.
4. Execute the Instruction
The Control Unit passes the information in the form of control signals to the functional unit of CPU. The
result generated is stored in main memory or sent to an output device.
The cycle is then repeated by fetching the next instruction. Thus in this way the instruction cycle is repeated
continuously.
REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

Fig.3.6 Instruction execution cycle

Instruction Cycle Code (ICC)
Assumed a new 2-bit register called Instruction Cycle Code (ICC). The ICC designates the state of the
processor in terms of which portion of the cycle it is in:-
00 : Fetch Cycle
01 : Indirect Cycle
10 : Execute Cycle
11 : Interrupt Cycle
At the end of the each cycle, the ICC is set appropriately. The above flowchart of Instruction Cycle
describes the complete sequence of micro-operations, depending only on the instruction sequence and the
interrupt pattern (this is a simplified example).
The operation of the processor is described as the performance of a sequence of micro-operation.
Different Instruction Cycles:
1. Fetch Cycle
At the beginning of the fetch cycle, the address of the next instruction to be executed is in the Program
Counter (PC).
REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

Step 1: The address in the program counter is moved to the memory address register (MAR), as this is the
only register which is connected to address lines of the system bus.

Step 2: The address in MAR is placed on the address bus, now the control unit issues a READ command
on the control bus, and the result appears on the data bus and is then copied into the memory buffer register
(MBR). Program counter is incremented by one, to get ready for the next instruction. (These two actions

can be performed simultaneously to save time)

Step 3: The content of the MBR is moved to the instruction register (IR).

Thus, a simple Fetch Cycle consists of three steps and four micro-operations. Symbolically, write this
sequence of events as follows:
t1:MARPC
t2:MBRMEMORY
PC (PC) + 1
t3: IR (MBR)
Here’I’’ is the instruction length. The notation (t1, t2, t3) represents successive time units. Assume that a
clock is available for timing purposes and it emits regularly spaced clock pulses. Each clock pulse defines
a time unit. Thus, all time units are of equal duration. Each micro- operation can be performed within the
time of a single time unit.
First time unit: Move the contents of the PC to MAR.
Second time unit: Move contents of memory location specified by MAR to MBR. Increment
content of PC by I.
Third time unit: Move contents of MBR to IR.
Note: Second and third micro-operations both take place during the second time unit.
REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

2. Indirect Cycles
Once an instruction is fetched, the next step is to fetch source operands. Source Operand is being fetched
by indirect addressing (it can be fetched by any addressing mode, here it’s done by indirect addressing).
Register-based operands need not be fetched. Once the opcode is executed, a similar process may be needed
to store the result in the main memory. Following micro-operations takes place:-
t1:MARIR (ADDRESS)
t2:MBRMEMORY
t3:IR (ADDRESS)(MBR(ADDRESS))
Step 1: The address field of the instruction is transferred to the MAR. This is used to fetch the address of
the operand.
Step 2: The address field of the IR is updated from the MBR.(So that it now contains a direct addressing
rather than indirect addressing)
Step 3: The IR is now in the state, as if indirect addressing has not been occurred.
Note: Now IR is ready for the execute cycle, but it skips that cycle for a moment to consider the Interrupt
Cycle.
3. Execute Cycle
The other three cycles (Fetch, Indirect and Interrupt) are simple and predictable. Each of them requires
simple, small and fixed sequence of micro-operation. In each case same micro-operation are repeated each
time around.
Execute Cycle is different from them. Like, for a machine with N different opcodes there are N different
sequence of micro-operations that can occur.
Let’s take a hypothetical example:-
Consider an add instruction:
ADD R, X
Here, this instruction adds the content of location X to register R. Corresponding micro-operation will be:
t1:MARIR (ADDRESS)
t2:MBR MEMORY
t3: R (R) + (MBR)
Begin with the IR containing the ADD instruction.
Step 1: The address portion of IR is loaded into the MAR.
Step 2: The address field of the IR is updated from the MBR, so the reference memory location is read.
Step 3: Now, the contents of R and MBR are added by the ALU.
Let’s take a complex example:-
ISZ X
Here, the content of location X is incremented by 1. If the result is 0, the next instruction will be skipped.
Corresponding sequence of micro-operation will be:
t1:MARIR (ADDRESS)
t2:MBR MEMORY
t3: MBR (MBR) + 1
t4:MEMORY (MBR) If
(MBR) = 0) then (PC  9PC) + 1)
Here, the PC is incremented if (MBR) = 0. This test (is MBR equal to zero or not) and action (PC is
incremented by 1) can be implemented as one micro-operation.
REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

Note: This test and action micro-operation can be performed during the same time unit during which the
updated value MBR is stored back to memory.
4. The Interrupt Cycle
At the completion of the Execute Cycle, a test is made to determine whether any enabled interrupt has
occurred or not. If an enabled interrupt has occurred then Interrupt Cycle occurs. The nature of this cycle
varies greatly from one machine to another.
Let’s take a sequence of micro-operation:
t1:MAR (PC)
t2:MBR SAVE_ADDRESS
PCROUTINE_ADDRESS
t3:MEMORY (MBR)
Step 1: Contents of the PC is transferred to the MBR, so that they can be saved for return.
Step 2: MAR is loaded with the address at which the contents of the PC are to be saved. PC is loaded with
the address of the start of the interrupt-processing routine.
Step 3: MBR, containing the old value of PC, is stored in memory.
Note: In step 2, two actions are implemented as one micro-operation. However, most processor provide
multiple types of interrupts, it may take one or more micro-operation to obtain the save_address and the
routine_address before they are transferred to the MAR and PC respectively.

3.5 ADDRESSING MODES

Addressing modes are the ways of specifying an operand or a memory address.
1. Register Addressing
2. Immediate Addressing
3. PC-Relative Addressing
4. Base Addressing
5. Pseudo-Direct Addressing
1. Register Addressing
 Register Addressing is a source or destination operand is specified as content of one of the registers
$0-$31.
 Register Addressing is considered the simplest addressing mode.
 This is because both operands are in a register (Figure 3.7). Which allow instructions to be executed
much faster in comparison with other addressing modes because they does not involves with
memory access.
 The number of registers is limited since only a few bits are reserved to select a register.
 Register Addressing is a form of direct addressing, this is because of only interested in the number
in the register, rather than using that number as a memory address.

Example of Register Addressing:

add $s1 , $s2 , $s3 also means that $s1 ←$s2 + $s3
where; $s1 = rd
$s2 = rs
$s3 = rt
REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

Fig.3.7 Register Addressing

2. Immediate Addressing
 Immediate Addressing is a numeric value embedded in the instruction in the actual operand.
 In immediate addressing, the operand is a constant within the encoded instruction (Figure 3.8).
 Immediate addressing has the advantage of not requiring an extra memory access to fetch the
operand, hence will be executed faster.
 However, the size of operand is limited to 16 bits.
 The jump instruction format also falls under immediate addressing, where the destination is held in
the instruction.
Example of Immediate Addressing:
addi $t1 , $zero , 1 means $t1 ← 0 + 7
(add immediate , uses the I-type format)
where; $t1 = rd
$zero = r1
1 = immediate value

Fig. 3.8 Immediate Addressing

3. PC-Relative Addressing
 PC-Relative Addressing also known as Program Counter Addressing is a data or instruction
memory location is specified as an offset relative to the incremented PC.
 PC-relative addressing is usually used in conditional branches. PC refers to special purpose register,
Program Counter that stores the address of next instruction to be fetched.
 In PC-relative addressing, the offset value can be an immediate value or an interpreted label value.
 The effective address is the sum of the Program Counter and offset value in the instruction. The
effective address determines the branch target.
 PC-relative addressing implements position-independent codes. Only a small offset is adequate for
shorter loops.
 Branch instructions can only move 32768 above or below the program counter because the offset
is a 16-bit two’s complement number.
Example of PC-Relative Addressing:
The operand address = PC + an offset Implements position-independent codes. A small offset is
adequate for short loops.
REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

Example: beqz $t0, strEnd

where; $t0 = rs
100 = offset
Thus; if ($t1 == 0) goto PC + 4 + (4*2)
In this instruction, beqz is a conditional instruction that branches to label in the code if the content of $t0
is equal to zero. If the current address for branch instruction in execution is 0x4000000C, the effective
address will be 40000018.
4. Base Addressing
 Base Addressing is a data or instruction memory location which is specified as a signed offset from
a register.
 Base addressing is also known as indirect addressing, where a register act as a pointer to an operand
located at the memory location whose address is in the register.
 The register is called base that may point to a structure or some other collection of data and
immediate value is loaded at a constant offset from the beginning of the structure. The offset
specifies how far the location of the operand data from the memory location pointed by the base.
 The address of the operand is the sum of the offset value and the base value (rs). However, the size
of operand is limited to 16 bits because each MIPS instruction fits into a word.
 The offset value is a signed number which is represented in a two's complement format. Therefore,
offset value can also be a negative value.
Here's an example for Base Addressing:
Instruction: lw $t1, 4 ($t2)
Where; $t1 = rs
$t2 = base (memory address)
4 = offset value
Thus; $t1 = Memory [$t2 +4]
In the example above, $t2 pointed to the base of a memory structure. The instruction the load register $t1
with the contents of the memory location four words onward from the location pointed by register $t2.
5. Pseudo-Direct Addressing
 Pseudo-Direct addressing is specifically used for J-type instructions, j and jal. The instruction
format is 6 bits of opcode and 26 bits for the immediate value (target) (Figure 3.9).
 In Pseudo-Direct addressing, the effective address is calculated by taking the upper 4 bits of the
Program Counter (PC), concatenated to the 26 bit immediate value, and the lower two bits are 00.
 Therefore, the new effective address will always be a word-aligned and never have a target address
of a jump instruction with the two bits anything other than 0 0 and creates a complete 32-bit address.
 Since the upper 4 bits of the PC are used, this constrains the jump target to anywhere within the
current 256 MB block of code (1/16 of the total 4 GB address space). To jump anywhere within the
4 GB space, the R-type instructions jr and jalr are used, where the complete 32 - bit target address
is specified in a register.

Fig. 3.9 Pseudo-Direct Addressing

REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

3.6 PERFORMANCE
 Performance means the measure of accuracy, efficiency and speed of executing program instructions
by computer.
 For best performance, it is necessary to design the compiler, the machine instruction set, and the
hardware in a coordinated way.
 Processor circuits are controlled by a timing signal called clock. The processor divides the action to be
performed in basic steps, such that each step can be completed in one clock cycle.
 Basic Performance Equation is given by:- T=((NXS)/R) , Where N= actual no. of instruction
executions , S= avg no. of basic step needed to execute one machine instruction , R- clock rate
(cycles/sec)
 In order to achieve high performance, the T value should reduce which can be done by reducing N and
S, or by increasing R.
 A Substantial improvement can also be done by overlapping the execution of successive instructions.
This concept is known as pipelining.

3.6.1 METRICS FOR PERFORMANCE MEASUREMENT

Computer performance is the amount of work accomplished by a computer system. The word
performance in computer performance means ―How well is the computer doing the work it is supposed to
do?‖. It basically depends on response time, throughput and execution time of a computer system.
Response time is the time from start to completion of a task. This also includes:
 Operating system overhead.
 Waiting for I/O and other processes.
 Accessing disk and memory.
 Time spent executing on the CPU or execution time.
Throughput is the total amount of work done in a given time.
CPU execution time is the total time a CPU spends computing on a given task. It also excludes time for
I/O or running other programs. This is also referred to as simply CPU time.
Performance is determined by execution time as performance is inversely proportional to execution time.
Performance = (1 / Execution time)
And,
(Performance of A / Performance of B) = (Execution Time of B / Execution Time of A)
If given that Processor A is faster than processor B, that means execution time of A is less than that of
execution time of B. Therefore, performance of A is greater than that of performance of B.
Example- Machine A runs a program in 100 seconds, Machine B runs the same program in 125 seconds.
(Performance of A / Performance of B) = (Execution Time of B / Execution Time of A)
= 125 / 100 = 1.25
That means machine A is 1.25 times faster than Machine B.
And, the time to execute a given program can be computed as:
Execution time = CPU clock cycles x clock cycle time
Since clock cycle time and clock rate are reciprocals, so,
Execution time = CPU clock cycles / clock rate
The number of CPU clock cycles can be determined by,
CPU clock cycles = (No. of instructions / Program) x (Clock cycles / Instruction)
REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

= Instruction Count x CPI

Which gives,
Execution time = Instruction Count x CPI x clock cycle time
= Instruction Count x CPI / clock rate
The units for CPU Execution time are:
How to Improve Performance?

To improve performance can either:

 Decrease the CPI (clock cycles per instruction) by using new Hardware.
 Decrease the clock time or Increase clock rate by reducing propagation delays or by use pipelining.
 Decrease the number of required cycles or improve ISA or Compiler.

3.7 DATA REPRESENTATION

 The basic form of information handled by a computer are instructions and data. The data can be in the form
of numbers or non-numerical data.
 The data in the number form can be further classified as fixed point and floating point.
Basic information types

3.7.1 SIGNED NUMBERS

Signed numbers contain sign flag, this representation distinguishes positive and negative numbers.
This technique contains both sign bit and magnitude of a number. For example, in representation of
negative decimal number, need to put negative symbol in front of given decimal number.
Approaches of signed numbers
a) Sign magnitude representation
b) One’s complement representation
c) Two’s complement representation
a) Sign-magnitude representation
 In computers both positive and negative numbers are represented with only binary digits.
B7 B6 B5 B4 B3 B2 B1 B0
MSB LSB

Sign Magnitude
REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

 Here, MSB represents sign of the number. If MSB is 1, the number is negative and if MSB is 0,
number is positive.
 Remaining bits represent magnitude of the number.
Example:
+6 = 0 0 0 0 0 1 1 0
-14 = 1 0 0 0 1 1 0 0
b) One’s complement representation
 The 1’s complement of a binary number is the number that results when we change all one’s to
zeros and the zeros to one’s (NOT operation).
Example: Find 1’s complement of (11010100)2
11010100

1’s complement 00101011

Answer is: (0 0 1 0 1 0 1 1)2
c) Two’s complement representation
 Add 1 to the 1’s complement.
 2’s complement = 1’s complement +1.
 Used to represent negative numbers.
Example: Find 2’s complement of (11000100)2
1 1 0 0 0 1 0 0
(1) (1) Carries
1’s complement 0 0 1 1 1 0 1 1
Now Add 1 (+) 1
0 0 1 1 1 1 0 0
Answer is: (0 0 1 1 1 1 0 0)2
3.7.2 FIXED POINT REPRESENTATION
This representation has fixed number of bits for integer part and for fractional part. For example, if
given fixed-point representation is [Link], then it store minimum value is 0000.0001 and maximum
value is 9999.9999. There are three parts of a fixed-point number representation: the sign field, integer
field, and fractional field.

Represent these numbers using:

(k-1)
 Signed representation: range from -(2 -1) to (2(k-1)-1), for k bits.
(k-1)
 1’s complement representation: range from -(2 -1) to (2(k-1)-1), for k bits.
 2’s complementation representation: range from -(2(k-1)) to (2(k-1)-1), for k bits.
2’s complementation representation is preferred in computer system because of unambiguous property and
easier for arithmetic operations.
REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

Example: Assume number is using 32-bit format which reserve 1 bit for the sign, 15 bits for the
integer part and 16 bits for the fractional part.
Then, -43.625 is represented as following:

Where, 0 is used to represent + and 1 is used to represent. 000000000101011 is 15 bit binary value for
decimal 43 and 1010000000000000 is 16 bit binary value for fractional 0.625.
The advantage of using a fixed-point representation is performance and disadvantage is relatively limited
range of values that they can represent. So, it is usually inadequate for numerical analysis as it does not
allow enough numbers and accuracy. A number whose representation exceeds 32 bits would have to be
stored inexactly.

These are above smallest positive number and largest positive number which can be store in 32-bit
representation as given above format. Therefore, the smallest positive number is 2-16 ≈ 0.000015
approximate and the largest positive number is (215-1)+(1-2-16)=215(1-2-16) =32768, and gap between these
numbers is 2-16. We can move the radix point either left or right with the help of only integer field is 1.
3.7.3 FLOATING POINT REPRESENTATION
 A designer of a floating-point representation must find a compromise between the size of the
fraction and the size of the exponent, because a fixed word size means we must take a bit from
one to add a bit to the other.
 Fraction is the value, generally between 0 and1, placed in the fraction field. The fraction is also
called the mantissa.
 Exponent is the numerical representation system of floating-point arithmetic, the value that is
placed in the exponent field.
 Increasing the size of the fraction enhances the precision of the fraction, while increasing the size
of the exponent increases the range of numbers that can be represented.
 Floating point numbers are usually a multiple of the size of a word.
 Floating representation has three fields
i) Sign ii) Significant digits iii) Exponent
Example:
1 1 1 1 0 1. 1 0 0 0 1 1 0 1. 1 1 1 0 1 1 0 0 1 1 0 × 25

Significant digits Scaling factor

Normalized form
REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

Sign = 0; Mantissa = 1 1 1 0 1 1 0 0 1 1 0; Exponent = 5

The representation of a MIPS floating-point number is shown below,

Where S is the sign of the floating-point number (1 meaning negative),

Exponent is the value of the 8-bit exponent field (including the sign of the exponent),
Fraction is the 23-bit number.
In general, floating-point numbers are of the form
(-1)S x F x 2E
F involves the value in the fraction field and E involves the value in the exponent field;
 These sizes of exponent and fraction give MIPS computer arithmetic an extraordinary range.
 Thus cause the overflow interrupts in floating point arithmetic as well as in integer arithmetic.
Overflow (Floating point)
 Overflow is a situation in which a positive exponent becomes too large to fit in the exponent field.
 Over means the exponent is too large to be represented in the exponent field.
Underflow (Floating point)
 Underflow is a Situation in which a negative exponent becomes too large to fit in the exponent
field.
 Underflow occurs when the negative exponent is too large to fit in the exponent field.
IEEE standard for floating point number
The standards for representing floating point numbers in 32-bits and 64-bits have developed by IEEE
Single Precision
The 32-bits standard representation is called a single precision representation because it occupies a single
32-bit word. The 32-bits are divided into three fields
(Field 1) Sign 1 bit
(Field 2) Exponent 8 bits
(Field 3) Mantissa 23 bits
Instead of the signed exponent E, the value actually stored in the exponent field is
Eʹ = E (scaling Factor) + bias

32 Bits
31 30 23 22 0
S Eʹ M

Sign of number: 8-bit signed exponent in 23-bit

0 signifies + excess -127 representations Mantissa fraction
1 signifies -
Value representation = ± 1.M × 2Eʹ-127
REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

Double Precision

64 Bits
63 62 52 51 0
S Eʹ M

Sign 11-bit excess-1023 exponent 52-bit

Mantissa fraction
Value representation = ± 1.M × 2Eʹ-1023
Example: Represent (1259.125)10 in single precision and double precision formats
Solution:
Step 1: Convert decimal number in binary format
Integer part:
78 4
16 1 2 5 9 16 78
112 64
0 139 14=E
128
011=B

=4EBH=1 00 1110 1011

4 E B
Fractional part
0. 1 2 5 × 2 = 0. 2 5 = 0
0. 2 5 × 2 = 0. 5 = 0
0. 5 × 2 = 1. 0 = 1
0. 1 2 5 = 0. 0 0 1
Binary number = 1 0 0 1 1 1 0 1 0 1 1. 0 0 1
Step 2: Normalize the number
1 0 0 1 1 1 0 1 0 1 1. 0 0 1 = 1. 0 0 1 1 1 0 1 0 1 1 0 0 1 × 210
Single Precision
Sign (s) = 0
Exponent (E) = 1 0
Mantissa (M) = 0 0 1 1 1 0 1 0 1 1 0 0 1
Bias for single precision format is 127
Eʹ = E + 127
= 10 + 127
= (137)10 = (1 0 0 0 1 0 0 1)2
Single precision is
0 10001001 0 0 1 1 1 0 1 0 1 1 0 0 1……..0

Sign Exponent Mantissa

REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

Double Precision
Bias for double precision format is 1023
Eʹ = E + 1023
= 10 + 1023
= (1033)10
= (1 0 0 0 0 0 0 1 0 0 1)2
Double precision is
0 10000001001 0 0 1 1 1 0 1 0 1 1 0 0 1……0

Sign Exponent Mantissa

3.7.4 CHARACTER REPRESENTATION
 The most common encoding scheme for characters is ASCII (American Standard Code for
Information Interchange).
 Alphanumeric characters, operators, punctuation symbols, and control characters are represented
by 7-bit codes.
 It is convenient to use an 8-bit byte to represent and store a character.
 The code occupies the low-order seven bits. The high-order bit is usually set to 0.
 The codes for the alphabetic and numeric characters are in increasing sequential order when
interpreted as unsigned binary numbers. This facilitates sorting operations on alphabetic and
numeric data.
 The low-order four bits of the ASCII codes for the decimal digits 0 to 9 are the first ten values of
the binary number system. This 4-bit encoding is referred to as the binary-coded decimal (BCD)
code.
Table 3.2 7-bit ASCII code
REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

3.8 COMPUTER ARITHMETIC

3.8.1 ADDITION AND SUBTRACTION
Digits are added bit by bit from right to left, with carries passed to the next digit to the left,
just as you would do by hand. Subtraction uses addition: the appropriate operand is simply negated before
being added.
Binary Addition and Subtraction:
Let’s try adding 6ten to 7ten in binary and then subtracting 6ten from 7ten in binary.

The carries are shown in parentheses, with the arrows showing how they are passed.
Binary addition, showing carries from right to left:
The rightmost bit adds 1 to 0, resulting in the sum of this bit being 1 and the carry out from this bit being
0. Hence, the operation for the second digit to the right is 0 + 1+ 1. This generates a 0 for this sum bit and
a carry out of 1. The third digit is the sum of 1 + 1 + 1, resulting in a carry out of 1 and a sum bit of 1. The
fourth bit is 1 +0 + 0, yielding a 1 sum and no carry.

Addition using the two’s complement representation of -6:

When adding operands with different signs, overflow cannot occur. The reason is the sum must be no larger
than one of the operands. For example, -10+ 4=-6. Since the operands fit in 32 bits and the sum is no larger
than an operand, the sum must fit in 32 bits as well. Therefore, no overflow can occur when adding positive
and negative operands.
During subtract, but it’s just the opposite principle: when the signs of the operands are the same, overflow
cannot occur. To see this, remember that c - a = c+ (-a) because we subtract by negating the second operand
and then add. Therefore, when we subtract operands of the same sign we end up by adding operands of
different signs.
REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

Adding or subtracting two 32-bit numbers can yield a result that needs 33 bits to be fully expressed.
The lack of a 33rd bit means that when overflow occurs, the sign bit is set with the value of the result
instead of the proper sign of the result. Since we need just one extra bit, only the sign bit can be wrong.
Hence, overflow occurs when adding two positive numbers and the sum is negative, or vice versa. This
false sum means a carry out occurred into the sign bit.
Overflow occurs in subtraction when we subtract a negative number from a positive number and get a
negative result, or when we subtract a positive number from a negative number and get a positive result.
Such a ridiculous result means a borrow occurred from the sign bit. Figure shows the combination of
operations, operands, and results that indicate an overflow.
Table 3.3 Overflow conditions for addition and subtraction

Unsigned integers are commonly used for memory addresses where overflows are ignored. The computer
designer must therefore provide a way to ignore overflow in some cases and to recognize it in others. The
MIPS solution is to have two kinds of arithmetic instructions to recognize the two choices:
 Add (add), add immediate (addi), and subtract (sub) cause exceptions on overflow.
 Add unsigned (addu), add immediate unsigned (addiu), and subtract unsigned (subu) do not cause
exceptions on overflow.
The computer designer must decide how to handle arithmetic overflows. Although some languages like C
and Java ignore integer overflow, languages like Ada and FORTRAN require that the program be notified.
The programmer or the programming environment must then decide what to do when overflow occurs.
MIPS detects overflow with an exception, also called an interrupt on many computers. An exception or
interrupt is essentially an unscheduled procedure call. The address of the instruction that overflowed is
saved in a register, and the computer jumps to a predefined address to invoke the appropriate routine for
that exception. The interrupted address is saved so that in some situations the program can continue after
corrective code is executed.
MIPS include a register called the exception program counter (EPC) to contain the address of the
instruction that caused the exception. The instruction move from system control (mfc0) is used to copy EPC
into a general-purpose register so that MIPS software has the option of returning to the offending
instruction via a jump register instruction.

3.8.2 RIPPLE CARRY ADDER

 A ripple carry adder is a digital circuit that produces the arithmetic sum of two binary numbers.
 It can be constructed with full adders connected in cascaded with the carry output from each full
adder connected to the carry input of the next full adder in the chain.
 The interconnection of four full adder (FA) circuits to provide a 4-bit ripple carry adder.
REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

 In 4-bit full adder the input is from the right side (Figure 3.10)because the first cell traditionally
represents the least significant bit (LSB)

Fig.3.10 4- bit Ripple Carry Adder

 Bits a0 and b0 in 4-bit full adder represent the least significant bits of the numbers to be added.
 The sum output is represented by the bits S0—S3.

Fig.3.11 Binary addition/subtraction logic circuit.

If an n-bit ripple-carry adder is used in the addition/subtraction circuit of Figure 3.11, it may have too much
delay in developing its outputs, s0 through sn−1 and cn. Whether or not the delay incurred is acceptable can
be decided only in the context of the speed of other processor components and the data transfer times of
registers and cache memories. The delay through a network of logic gates depends on the integrated circuit
electronic technology used in fabricating the network and on the number of gates in the paths from inputs
to outputs.
The delay through any combinational circuit constructed from gates in a particular technology is
determined by adding up the number of logic-gate delays along the longest signal propagation path through
the circuit. In the case of the n-bit ripple-carry adder, the longest path is from inputs x0, y0, and c0 at the
LSB position to outputs cn and sn−1 at the most-significant-bit (MSB) position.
REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

Fig.3.12 Logic for a single stage

Fig.3.13 An n-bit ripple-carry adder

Fig.3.14 Cascade of k n-bit adders

Using the implementation indicated in Figure 3.12, cn−1 is available in 2(n−1) gate delays, and Sn−1 is
correct one XOR gate delay later. The final carry-out, Cn, is available after 2n gate delays. Therefore, if a
ripple-carry adder is used to implement the addition/subtraction unit shown in Figure 3.11, all sum bits are
REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

available in 2n gate delays, including the delay through the XOR gates on the Y input. Using the
implementation Cn ⊕ Cn−1 for overflow, this indicator is available after 2n + 2 gate delays. Two approaches
can be taken to reduce delay in adders. The first approach is to use the fastest possible electronic
technology. The second approach is to use a logic gate network called a carry-lookahead network.

3.8.3 CARRY LOOK-AHEAD ADDER

 The addition of two binary numbers in parallel implies that all the bits of the augend (A) and added (B)
are available for computation at the same time. For any combinational circuit, the signal must propagate
through the gates has required sometime delay, this is known as propagation delay.
 Propagation delay time in an adder is the time it takes the carry to propagate through the full adder.
Also the number of gate levels for the carry propagation can be found from the adder circuit. The carry
propagation time is an important attribute of the adder, because it limits the speed with which two numbers
are added.
Example
In parallel the carry output of each full adder stage is connected to the carry input of the next higher order
stage. Therefore, the sum and carry outputs of any stage cannot be produced until the input carry occurs,
this leads a time delay in the addition process. This delay is known as carry propagation delay which can
be explained by following consideration.
Consider Augend, A = 0 1 0 1 and added, B = 0 0 1 1

Here the addition LSB = 1 + 1 produces a carry into the next bit. When the carry is added to the second bit
position, then only the addition takes place. Similarly to the third and fourth-bit position. This leads to
delay the next process; this delay time is known as carry propagation delay time.
To eliminate these delay time, one method of speeding up this process by eliminating inter stage carry
delay is called carry look ahead adder or fast adder. The carry look ahead adder is based on the principle
of looking at the lower order bits of the augend and addend to see if a higher order carry is to be generated.
It uses two functions
(i) Carry generate, Gi
(ii) Carry propagate, Pi
REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

Fig.3.15 Full adder with P and G

In this two binary variables carry propagate and a carry generate are defined as
Pi = Ai ⊕ Bi Carry propagate
Gi = Ai Bi Carry generate
The output sum and carry can respectively be expressed as
Si = Pi ⊕ Ci
Ci+1 = Gi + Pi Ci
Carry generate Gi produces a carry of 1 when both Ai and Bi are regardless of the input carry Ci. The
Boolean functions of the carry outputs of each stage can now be written as
C0 = input carry
C1 = G0 + P0 C0
C2 = G1 + P1 C1 = G1 + P1 G0 + P1 P0 G0
C3 = G2 + P2 C2 = G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 C0
The three Boolean functions C1, C2 and C3 are implemented in the carry look generator shown in the
following figure 3.16.

Fig.3.16 Logic diagram of carry look ahead generator

REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

In this, this circuit can add in less time because C3 does not have to wait for C2 and C1 to propagate and
also C3 is propagated at the same time as C1 and C2. This will gain in speed of operation is achieved at the
expense of additional complexity.
The construction of carry look ahead adder using carry look ahead generator is shown in figure 3.17.

Fig.3.17 4-bit carry look ahead adder

Each sum output requires two exclusive OR gates. The output of the first exclusive OR gates generates Pi
and AND gate generates Gi. The carries are propagated through the carry look ahead generator and applied
to the second exclusive OR gate. All output carries are generated after a delay through two levels of gates.
Thus outputs S1 through S3 have equal propagation delay.

3.8.4 MULTIPLICATION
The multiplication is a complex operation than addition and subtraction.
Multiplying 1000ten by 1001ten:
REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

The first operand is called the multiplicand and the second the multiplier. The final result is called the
product. Take the digits of the multiplier one at a time from right to left, multiplying the multiplicand by
the single digit of the multiplier, and shifting the intermediate product one digit to the left of the earlier
intermediate products.
The first observation is that the number of digits in the product is considerably larger than the number in
either the multiplicand or the multiplier. In fact, if we ignore the sign bits, the length of the multiplication
of an n-bit multiplicand and an m-bit multiplier is a product that is n + m bits long. That is, n + m bits are
required to represent all possible products. Hence, like add, multiply must cope with overflow because we
frequently want a 32-bit product as the result of multiplying two 32-bit numbers.
With only two choices, each step of the multiplication is simple:
 Just place a copy of the multiplicand (1 X multiplicand) in the proper place if the multiplier digit is
a 1, or
 Place 0 (0 X multiplicand) in the proper place if the digit is 0.

Fig.3.18 First version of the multiplication hardware

The Multiplicand register, ALU, and Product register are all 64 bits wide, with only the Multiplier register
containing 32 bits. The 32-bit multiplicand starts in the right half of the Multiplicand register and is shifted
left 1 bit on each step. The multiplier is shifted in the opposite direction at each step. The algorithm starts
with the product initialized to 0. Control decides when to shift the Multiplicand and Multiplier registers
and when to write new values into the Product register (Figure 3.18).
Sequential Version of the Multiplication Algorithm and Hardware
Let’s assume that the multiplier is in the 32-bit Multiplier register and that the 64-bit Product register is
initialized to 0. We will need to move the multiplicand left one digit each step, as it may be added to the
intermediate products. Over 32 steps, a 32-bit multiplicand would move 32 bits to the left. Hence, we need
a 64-bit Multiplicand register, initialized with the 32-bit multiplicand in the right half and zero in the left
half. This register is then shifted left 1 bit each step to align the multiplicand with the sum being
accumulated in the 64-bit Product register.
REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

Fig.3.19 First multiplication algorithm

The least significant bit of the multiplier (Multiplier0) determines whether the multiplicand is added
to the Product register. The left shift in step 2 has the effect of moving the intermediate operands to the
left. The shift right in step 3 gives us the next bit of the multiplier to examine in the following iteration.
These three steps are repeated 32 times to obtain the product (Figure 3.19).
This algorithm and hardware are easily refined to take 1 clock cycle per step. The speed-up comes from
performing the operations in parallel: the multiplier and multiplicand are shifted while the multiplicand is
added to the product if the multiplier bit is a 1. The hardware just has to ensure that it tests the right bit of
the multiplier and gets the preshifted version of the multiplicand. The hardware is usually further optimized
to halve the width of the adder and registers by noticing where there are unused portions of registers and
adders.
REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

Fig.3.20 Refined version of the multiplication hardware

The Multiplicand register, ALU, and Multiplier register are all 32 bits wide, with only the Product register
left at 64 bits. Now the product is shifted right. The separate Multiplier register also disappeared. The
multiplier is placed instead in the right half of the Product register (Figure 3.20).

[Link] BOOTH MULTIPLIER

Booth's algorithm is a multiplication algorithm that multiplies two signed binary numbers in two's
complement notation. Booth used desk calculators that were faster at shifting than adding and created the
algorithm to increase their speed. Booth's algorithm is of interest in the study of computer architecture.
Booth's algorithm performs fewer additions and subtractions than the normal multiplication algorithm.
 In existing technique, when we add negative multiplicand, we must extend the sign bit value of the
multiplicand to the left and product will extend.
 It does not treat both positive and negative uniformly.
 Booth’s algorithm is a powerful algorithm for signed number multiplicands which generates a 2n-
bit product and treats both positive and negative uniformly.
 Reduce the number of operations by using this algorithm.
Booth’s algorithm hardware implementation (Figure 3.21)
 It consists of n-bit adder, shift, add subtract control logic and four register A, B, Q and Q-1.
 Multiplier and multiplicand are loaded into register Q and B
 The sequence counter (SC) is set to a number n equal to the number of bits in the multiplier
 The n-bit adder performs addition of two inputs.
 The shift control logic is generating a control signals.
REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

Fig.3.21 Hardware to implement booth multiplication

Example: (5) × (-4)

[Link] CARRY SAVE MULTIPLIER

 In carry save adders (CSA) can be used to add several numbers with carry propagation only in the
last stage.
 The partial products can be generated in parallel using n2 AND gates.
REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

 The n partial products can then be added using a CSA tree (Figure 3.22).

Fig.3.22 4 × 4 Carry save multiplier

Example: 1 0 1 1 × 1 1 0 1

1011
× 1101
1011 A
00000 B
101100 C
1011000 D
1001111 Resultant

Step 1: Add A and B (A+ B)

1 0 1 1 A
(+) 0 0 0 0 0 B

0 1 0 1 1 S1
0 0 0 0 0 C1
Step 2: Add C and D (C+ D)
1 0 1 1 0 0 C
(+) 1 0 1 1 0 0 0 D

1 1 1 0 1 0 0 S2
0 0 1 0 0 0 0 C2
REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

Step 3: Find S3 and C3 (Add S1, C1 and S2)

0 1 0 1 1 S1
0 0 0 0 0 C1
(+) 1 1 1 0 1 0 0 S2

1 1 1 1 1 1 1 S3
0 0 0 0 0 0 0 C3

Step 4: Find S4 and C4 (Add S3, C3 and C2)

1 1 1 1 1 1 1 S3
0 0 0 0 0 0 0 C3
(+) 0 0 1 0 0 0 0 C2

1 1 0 1 1 1 1 S4
0 1 0 0 0 0 0 C4

Step 5: Add S4 and C4 (S4 + C4 Result)

(1)
1 1 0 1 1 1 1 S4
(+) 0 1 0 0 0 0 0 C4

1 0 0 0 1 1 1 1 Result

Answer is 1 0 0 0 1 1 1 1

3.8.5 DIVISION
The example is dividing 1,001,010ten by 1000ten:

Divide’s two operands, called the dividend and divisor, and the result, called the quotient, are accompanied
by a second result, called the remainder. Here is another way to express the relationship between the
components:
Dividend = Quotient X Divisor + Remainder
where the remainder is smaller than the divisor.
REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

Dividend - A number being divided.

Divisor - A number that the dividend is divided by.
Quotient - The primary result of a division; a number that when multiplied by the divisor and added to the
remainder produces the dividend.
Remainder - The secondary result of a division; a number that when added to the product of the quotient
and the divisor produces the dividend.
It’s easy to figure out how many times the divisor goes into the portion of the dividend: it’s either 0 times
or 1 time. Binary numbers contain only 0 or 1, so binary division is restricted to these two choices, thereby
simplifying binary division.
Division Algorithm are
(i) Restoring Division
(ii) Non- Restoring Division
[Link] RESTORING TECHNIQUE
Restoring division operates on fixed-point fractional numbers and depends on the following assumptions
D < N,
0 < N,
D < 1.
For binary representation, the restoring division is simply a process of quotient digit selection from the set
{0,1}.It restores the partial remainder to a positive condition before beginning the next quotient digit
iteration.
Hardware Implementation

Fig.3.23 Hardware to implement division

Hardware Implementation consists of n+1 bit binary adder, shift, add and subtract control logic and
register A, B, and Q.
REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

Divisor and Dividend are loaded into register B, Q and register A is set to zero initially (Figure 3.23).
Steps:
1. Shift A and Q Left ones binary position
2. Subtract divisor from A and store result in A (i.e) A A-B
3. If the sign bit of A is 1, set Q0 to 0 and add divisor back to A. Otherwise set Q0 to 1
4. Repeat steps 1, 2 and 3 n times.
Advantage
 Full width comparisons required to deduce the new quotient digit.
Limitation
 Slower- requires time because of restoration in each cycle
Example: Divide (10)10 by (3)10 using the restoring division algorithm
Solution:
Assume the Registers:
Register A=00000
Dividend Q = 1010
Divisor B= 0011(Append 0 to MSB of B while add/sub with accumulator A)

Steps A Register Q Register

Initially 00000 1010
0 1 0 First Cycle
Shift 00001

A=A-B 11110 0 1 0 0

Restore A= A+B 00001

1 0 0
Shift 00010
Second Cycle
A=A-B 1 1111 1 0 0 0

Restore A= A+B 00010

0 0 0
Shift 00101 Third Cycle

A=A-B 0 0010 0 0 0 1

Shift 00100
0 0 1
A=A-B 00001
Fourth Cycle
0 0 1 1
Remainder

Quotient
REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

[Link] NON-RESTORING TECHNIQUE

Steps
1. If the sign of A is 0, shift A and Q left one bit position and subtract divisor from A. otherwise shift A
and Q left and add divisor to A. If the sign of A is 0 then Set Q0 to 1otherwise, set Q0 to 0.
2. Repeat steps 1 and 2 for n times.
3. If the sign of A is 1. Add divisor to A.

Example: Divide (10)10 by (3)10 using the non-restoring division algorithm

Assume the Registers
Register A=00000
Dividend Q =1010
Divisor B= 0011 (Append 0 to MSB of B while add/sub with accumulator A)

Steps A Register Q Register

Initially 00000 1010
0 1 0
Shift 00001
First Cycle

A=A-B 11110 0 1 0 0

1 0 0
Shift 11100
Second Cycle
1 0 0 0
A=A+B 11111

0 0 0
Shift 11111
Third Cycle
A=A+B 00010 0 0 0 1

Shift 00100 0 0 1

A=A-B 00001 Fourth Cycle

0 0 1 1

Remainder Quotient
REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

Restoring vs Non-restoring division algorithm

Table 3.3 comparison between restoring and non-restoring division algorithm
Restoring Non- Restoring
 Needs restoring of register A if the  Does not need restoring.
result of subtraction is negative.
 In each cycle, content of register A is  In each cycle content of register A is first
first shifted left and then divisor is shifted left and then divisor is added or
subtracted from it. subtracted within the content of register A
depending on the sign of A.
 Does not need restoring of remainder.  Need restoring of remainder is negative.
 Slower Algorithm  Faster algorithm.

3.9 FLOATING POINT ARITHMETIC

The basic operations for floating-point arithmetic. For addition and subtraction, it is necessary to
ensure that both operands have the same exponent value. This may require shifting the radix point on one
of the operands to achieve alignment. Multiplication and division are more straightforward. A floating-
point operation may produce one of these conditions:
Exponent overflow: A positive exponent exceeds the maximum possible exponent value. In some systems,
this may be designated as +∞ or - ∞.
Exponent underflow: A negative exponent is less than the minimum possible exponent value (e.g., - 200
is less than -127). This means that the number is too small to be represented, and it may be reported as 0.
Table 3.4 Floating-Point Numbers and Arithmetic Operations

Examples:
X = 0.3 * 102 = 30
Y = 0.2 * 103 = 200
X + Y = (0.3 * 102-3 + 0.2) * 103 = 0.23 * 103 = 230
X - Y = (0.3 * 102-3 - 0.2) * 103 = ( - 0.17) * 103 = -170
X * Y = (0.3 * 0.2) * 102+3 = 0.06 * 105 = 6000
X , Y = (0.3 , 0.2) * 102-3 = 1.5 * 10-1 = 0.15

3.9.1 ADDITION AND SUBTRACTION

In floating-point arithmetic, addition and subtraction are more complex than multiplication and
division. This is because of the need for alignment. There are four basic phases of the algorithm for addition
and subtraction:
1. Check for zeros.
2. Align the significands.
REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

3. Add or subtract the significands.

4. Normalize the result.
A typical flowchart is shown in Figure.3.24. A step-by-step narrative highlights the main functions required
for floating-point addition and subtraction. For the addition or subtraction operation, the two operands must
be transferred to registers that will be used by the ALU. If the floating-point format includes an implicit
significand bit, that bit must be made explicit for the operation.
Phase 1-Zero check: Because addition and subtraction are identical except for a sign change, the process
begins by changing the sign of the subtrahend if it is a subtract operation. Next, if either operand is 0, the
other is reported as the result.
Phase 2-Significand alignment: The next phase is to manipulate the numbers so that the two exponents
are equal.
Alignment may be achieved by shifting either the smaller number to the right (increasing its exponent) or
shifting the larger number to the left. Because either operation may result in the loss of digits, it is the
smaller number that is shifted; any digits that are lost are therefore of relatively small significance. The
alignment is achieved by repeatedly shifting the magnitude portion of the significand right 1 digit and
incrementing the exponent until the two exponents are equal. (Note that if the implied base is 16, a shift of
1 digit is a shift of 4 bits.) If this process results in a 0 value for the significand, then the other number is
reported as the result. Thus, if two numbers have exponents that differ significantly, the lesser number is
lost.

Fig. 3.24 Floating-Point Addition and Subtraction (Z X ±Y)

REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

Phase 3-Addition: Next, the two significands are added together, taking into account their signs. Because
the signs may differ, the result may be 0. There is also the possibility of significand overflow by 1 digit. If
so, the significand of the result is shifted right and the exponent is incremented. An exponent overflow
could occur as a result; this would be reported and the operation halted.
Phase 4-Normalization: The final phase normalizes the result. Normalization consists of shifting
significand digits left until the most significant digit (bit, or 4 bits for base-16 exponent) is nonzero. Each
shift causes a decrement of the exponent and thus could cause an exponent underflow. Finally, the result
must be rounded off and then reported.

3.9.2 MULTIPLICATION AND DIVISION

Floating-point multiplication and division are much simpler processes than addition and
subtraction. In multiplication, first, if either operand is 0, 0 is reported as the result.
The next step is to add the exponents. If the exponents are stored in biased form, the exponent sum would
have doubled the bias. Thus, the bias value must be subtracted from the sum. The result could be either an
exponent overflow or underflow, which would be reported, ending the algorithm.

Fig. 3.25 Floating-Point Multiplication (Z X ± Y)

If the exponent of the product is within the proper range, the next step is to multiply the significands, taking
into account their signs. The multiplication is performed in the same way as for integers. In this case, we
are dealing with a sign magnitude representation, but the details are similar to those for twos complement
representation.
REGULATION: IFETCE R2023 ACADEMIC YEAR: 2025-2026

The product will be double the length of the multiplier and multiplicand. The extra bits will be lost during
rounding. After the product is calculated, the result is then normalized and rounded, as was done for
addition and subtraction (Figure 3.25). Note that normalization could result in exponent underflow.
In division, the first step is testing for 0. If the divisor is 0, an error report is issued, or the result is set to
infinity, depending on the implementation. A dividend of 0 results in 0. Next, the divisor exponent is
subtracted from the dividend exponent. This removes the bias, which must be added back in. Tests are then
made for exponent underflow or overflow. The next step is to divide the significands. This is followed with
the usual normalization and rounding (Figure 3.26).

Fig.3.26 Floating-Point Division (Z X/Y)