Complete Electronics Formula & Reference Guide

PART 1: DC CIRCUIT ANALYSIS

Topic 1: Ohm's Law & Power Calculations

Basic Formulas:

Ohm's Law: V = IR, R = V/I, I = V/R

Power: P = VI = I²R = V²/R (Watts)

Energy: E = Pt (Joules, where t is time in seconds)

Power loss in wire: P_loss = I²R_wire

Components Used:

Resistors: Fixed, variable, thermistor, photoresistor (LDR)

Power supplies: DC source, battery, regulated power supply

Applications:

LED current limiting: I = (V_supply - V_LED)/R

Heater power: P = V²/R

Fuse selection based on current capacity

Topic 2: Series & Parallel Resistance

Series Circuits:

Total Resistance: R_T = R ₁ + R₂ + R₃ + ... + Rₙ

ₓ
Voltage Division: V_x = V_T × (R /R_T)

Current everywhere: I = I ₁ = I₂ = I₃ (same)

Total Voltage: V_T = V ₁ + V ₂ + V₃

Parallel Circuits:
 Two resistors: R_T = (R ₁ × R₂)/(R₁ + R₂)

n resistors: 1/R_T = 1/R ₁ + 1/R₂ + ... + 1/Rₙ

Current Division: I_x = I_T × (R_T/R ) ₓ

Voltage (same across all): V = V ₁ = V₂ = V₃

Total Current: I_T = I ₁ + I₂ + I₃

Voltage Divider (Series):

V_out = V_in × (R /(R ₂ ₁ + R₂))

Current Divider (Parallel):

I_x = I_T × (R_other/R_x)

Topic 3: Kirchhoff's Laws

Kirchhoff's Voltage Law (KVL):

Sum of voltages around closed loop = 0: ΣV = 0

V_source = V_R ₁ + V_R₂ + ...

Kirchhoff's Current Law (KCL):

Sum of currents entering node = sum leaving: ΣI_in = ΣI_out

At junction: I ₁ = I₂ + I₃

Steps for Circuit Analysis:

1. Assign current directions in each branch

2. Apply KCL at each node (n-1 equations for n nodes)

3. Apply KVL for each loop

4. Solve simultaneous equations

Topic 4: Thévenin's & Norton's Theorem

Thévenin's Theorem:
 V_th = Open circuit voltage between terminals

R_th = Equivalent resistance (sources deactivated)

Thévenin circuit: V_th in series with R_th

Norton's Theorem:

I_n = Short circuit current = V_th/R_th

R_n = R_th

Norton circuit: I_n in parallel with R_n

Conversions:

V_th = I_n × R_th

I_n = V_th/R_th

Topic 5: Maximum Power Transfer

Maximum Power Theorem:

Maximum power to load when R_L = R_th

P_max = V_th²/(4R_th)

Efficiency:

η = R_L/(R_th + R_L) × 100%

At max power (R_L = R_th): η = 50%

PART 2: AC CIRCUIT ANALYSIS

Topic 6: Phasor Analysis & Impedance

AC Signal Representation:

v(t) = V_m sin(ωt + φ)

RMS Value: V_rms = V_m/√2

 Peak-to-Peak: V_pp = 2V_m

Angular Frequency: ω = 2πf

Phasor Form:

V = V_rms∠φ

Rectangular: V = a + jb

|V| = √(a² + b²), θ = arctan(b/a)

Impedance (Z):

Resistor: Z_R = R∠0°

Inductor: Z_L = jωL∠90°, X_L = ωL = 2πfL

Capacitor: Z_C = -j/(ωC)∠-90°, X_C = 1/(ωC)

RLC: Z = R + j(X_L - X_C), |Z| = √(R² + (X_L - X_C)²)

Phase: φ = arctan((X_L - X_C)/R)

Topic 7: RLC Circuit Resonance

Series RLC Resonance:

Resonant Frequency: f_r = 1/(2π√LC) Hz

At resonance: X_L = X_C, φ = 0°, Z = R

Current (maximum): I_max = V/R

Voltage across R: V_R = V (full supply)

Quality Factor (Q):

Q = ω_r L/R = 1/(ω_r RC) = (1/R)√(L/C)

Q = f_r/BW

High Q = sharp resonance, Low Q = broad resonance

Bandwidth:

BW = f_r/Q

Half-power points: |Z| = R√2

 ₁ ₂ = f_r/2 × (√(1 + 1/Q²) ± 1/Q)
Frequencies: f , f

Voltage Magnification:

Voltage multiplier = Q

V_L at resonance = Q × V_source

Topic 8: AC Power Calculations

Power Types:

Real Power: P = VI cos(φ) Watts

Reactive Power: Q = VI sin(φ) VAR

Apparent Power: S = VI VA

Relation: S² = P² + Q²

Power Factor:

PF = cos(φ) = P/S

Leading (capacitive): φ < 0°

Lagging (inductive): φ > 0°

Phase Angle:

cos(φ) = R/Z

tan(φ) = (X_L - X_C)/R

Energy:

E = Pt = S × t × cos(φ) Wh

Topic 9: Voltage & Current in AC Circuits

AC Values:

Peak: V_m, I_m

RMS: V_rms = V_m/√2

 Average: V_avg = (2/π)V_m ≈ 0.637V_m

Peak-to-peak: V_pp = 2V_m

Form & Crest Factors (for sine wave):

Form Factor: FF = V_rms/ V_avg ≈ 1.11

Crest Factor: CF = V_peak/ V_rms = √2 ≈ 1.414

Phase Relationships:

Resistor: V and I in phase (φ = 0°)

Inductor: V leads I by 90°

Capacitor: V lags I by 90°

Phase Difference:

φ = φ_v - φ_i

Time delay: t = φ/ω = φ/(2πf)

Topic 10: Frequency Response & Filters

Gain (dB):

Voltage Gain: G_dB = 20 log ₁₀(V_out/ V_in)

Power Gain: G_dB = 10 log ₁₀(P_out/P_in)

Cutoff Frequency:

f_c = 1/(2πRC)

At -3dB point: |A|_-3dB = A_max/√2

Low-Pass Filter (RC):

f_c = 1/(2πRC)

Roll-off: -20 dB/decade above f_c

Phase at f_c: -45°

High-Pass Filter (RC):

f_c = 1/(2πRC)

Roll-off: -20 dB/decade below f_c

Phase at f_c: +45°

Band-Pass Filter (RLC):

Center frequency: f_c = 1/(2π√LC)

Bandwidth: BW = f_r/Q

Filter Roll-off:

First-order: -20 dB/decade

Second-order: -40 dB/decade

nth-order: -20n dB/decade

PART 3: DIGITAL LOGIC DESIGN

Topic 11: Boolean Algebra & Logic Gates

Basic Operations:

AND (·): 1 only if all inputs = 1

OR (+): 1 if any input = 1

NOT ('): Complement (0→1, 1→0)

XOR (⊕): 1 if inputs differ

XNOR (⊙): 1 if inputs same

Boolean Laws:

Commutative: A+B = B+A, AB = BA

Associative: (A+B)+C = A+(B+C)

Distributive: A(B+C) = AB+AC

Identity: A+0 = A, A·1 = A

Null: A+1 = 1, A·0 = 0

 Complement: A+A' = 1, A·A' = 0

De Morgan's Laws:

(A+B)' = A'·B'

(A·B)' = A'+B'

Universal Gates:

NAND gate: Can implement ANY logic

NOR gate: Can implement ANY logic

Topic 12: Combinational Logic Circuits

Minterms & Maxterms:

Minterm: Product of all variables (1 for that combination)

Maxterm: Sum of all variables (0 for that combination)

For n variables: 2^n minterms/maxterms

Sum of Products (SOP):

Y = A'BC + AB'C + ABC

AND gates → OR gate

Product of Sums (POS):

Y = (A+B+C)(A+B'+C)

OR gates → AND gate

Karnaugh Map (K-Map):

2-var: 2×2 grid (4 cells)

3-var: 2×4 grid (8 cells)

4-var: 4×4 grid (16 cells)

Group 2^n adjacent 1s (for SOP) or 0s (for POS)

Write variable names that don't change in each group

Decoder:

n inputs → 2^n outputs

Only one output = 1 at a time

Application: Address decoding, 7-segment display

Encoder:

2^n inputs → n outputs

Shows which input is active

Priority encoder: Multiple inputs → highest priority

Multiplexer (MUX):

2^n data inputs → 1 output

n select lines choose which input passes through

₀ ₁
2-to-1: Y = I ·S' + I ·S

₀ ₁ ₀ ₁ ₁ ₀ + I₂·S₁S₀' + I₃·S₁S₀
4-to-1: Y = I ·S 'S ' + I ·S 'S

Demultiplexer (DEMUX):

1 input → 2^n outputs

n select lines choose which output gets the input

Others remain 0 (or float)

Topic 13: Number Systems & Conversions

Base Conversions:

Decimal → Binary: Divide by 2, collect remainders

Binary → Decimal: Sum of (digit × 2^position)

Binary ↔ Octal: Group in 3s

Binary ↔ Hex: Group in 4s

Signed Numbers:
 Sign-Magnitude: MSB = sign bit, rest = magnitude

One's Complement: Negative = invert all bits

Two's Complement: Negative = invert bits + 1

Two's Complement:

Range for n-bit: -2^(n-1) to +(2^(n-1)-1)

Used for subtraction: A - B = A + (-B)

Gray Code:

Binary → Gray: G[i] = B[i] XOR B[i+1]

Only one bit changes between consecutive values

BCD (Binary Coded Decimal):

Each decimal digit → 4-bit binary

0 = 0000, 1 = 0001, ..., 9 = 1001

Topic 14: Decoder, Encoder, Multiplexer, Demultiplexer (Detailed)

Decoder Truth Table (2-to-4):

Input D3 D2 D1 D0

AB=00 0 0 0 1

AB=01 0 0 1 0

AB=10 0 1 0 0

AB=11 1 0 0 0

Encoder Truth Table (4-to-2):

 D3 D2 D1 D0 B A

0 0 0 1 0 0

0 0 1 0 0 1

0 1 0 0 1 0

1 0 0 0 1 1

MUX/DEMUX Equations:

₀ ₁ ₀ ₁ ₁ ₀ + I₂S₁S₀' + I₃S₁S₀
MUX-4-to-1: Y = I S 'S ' + I S 'S

DEMUX-1-to-4: Y ₀ = IS₁'S₀', Y₁ = IS₁'S₀, Y₂ = IS₁S₀', Y₃ = IS₁S₀

Topic 15: Flip-Flops & Sequential Logic

SR Flip-Flop (Set-Reset):

S=1, R=0 → Q=1 (Set)

S=0, R=1 → Q=0 (Reset)

S=0, R=0 → Q holds previous state

S=1, R=1 → Invalid/undefined

JK Flip-Flop:

J=0, K=0 → Hold state

J=1, K=0 → Q=1 (Set)

J=0, K=1 → Q=0 (Reset)

J=1, K=1 → Toggle (Q → Q')

D Flip-Flop (Data):

D=0 → Q=0

D=1 → Q=1

Captures data on clock edge

Q = D on each clock pulse

T Flip-Flop (Toggle):

T=0 → Hold state

T=1 → Toggle (Q → Q')

Frequency divider: Output freq = Input freq / 2

Frequency Division:

n flip-flops → f_out = f_in / 2^n

Divide by 2: 1 flip-flop

Divide by 4: 2 flip-flops

Timing Parameters:

Setup time: t_s (data must be stable before clock)

Hold time: t_h (data must stay stable after clock)

Propagation delay: t_p (time for output to change)

Clock-to-output: t_co

PART 4: ELECTRONIC DEVICES

Topic 16: Diode Characteristics

Diode Ideal Behavior:

Forward bias (V_f > 0): Acts like closed switch (R ≈ 0)

Reverse bias (V_r < 0): Acts like open switch (R ≈ ∞)

Forward voltage drop (Si): ~0.7V, (Ge): ~0.3V

Diode Equation (Shockley):

I = I_s(e^(V_d/(nV_t)) - 1)

I_s = saturation current

n = ideality factor (~1-2)

V_t = thermal voltage = kT/q ≈ 26mV at 25°C

Practical Diode Model:

Forward bias: V_d ≈ 0.7V (silicon), 0.3V (germanium)

Reverse bias: I_r ≈ I_s (very small, ~nA)

Reverse breakdown: V_br (breakdown voltage)

Zener Diode:

Operates in reverse bias

V_z = constant (zener voltage)

Used for voltage regulation

Zener regulation: V_out = V_z (approximately constant)

Rectifier Diode:

Half-wave rectification: Average voltage = V_m/π

Full-wave rectification: Average voltage = 2V_m/π

Ripple frequency: f_ripple = f for half-wave, 2f for full-wave

Capacitor Filter:

Reduces ripple voltage

V_ripple = I_load·T/(2C) = I_load/(2·f·C)

Larger C → smaller ripple

Photodiode:

Current proportional to light intensity

I_photo = I_d + I_light

Used in: Light sensors, optical communication

Topic 17: Transistor (BJT) Biasing & Operation

BJT Basics:

NPN: Electrons flow from emitter to collector

 PNP: Holes flow from emitter to collector

I_c = β·I_b (current amplification)

I_e = I_c + I_b (emitter current)

Transistor Relations:

Current gain (β): β = I_c/I_b (typically 50-500)

Alpha (α): α = I_c/I_e, α + β = 1 → α = β/(β+1)

I_c = α·I_e = β·I_b

Transistor Regions:

Cutoff: V_be < 0.7V (Si), both junctions reverse biased, I_c ≈ 0

Active: V_be ≈ 0.7V (Si), base reverse biased, I_c = β·I_b

Saturation: V_be ≈ 0.7V, both junctions forward biased, I_c ≈ I_sat

Common Emitter (CE) Configuration:

Input: Base current (I_b)

Output: Collector current (I_c)

Voltage gain: A_v = -g_m·R_c (negative = phase reversal)

Input resistance: r_be = V_t/I_b (usually 1-100kΩ)

Output resistance: r_ce = (very high)

Common Collector (Emitter Follower):

Input: Base

Output: Emitter

Voltage gain: A_v ≈ 1 (unity gain, no inversion)

High input impedance, low output impedance

Used for: Impedance matching, buffering

Common Base:

Input: Emitter

Output: Collector
 Current gain ≈ 1, high voltage gain

Very low input impedance

Biasing Methods:

Fixed base bias: I_b = (V_cc - V_be)/R_b

Voltage divider bias: Stable, temperature compensated

Emitter bias: Most stable

Collector feedback bias

Topic 18: MOSFET Characteristics

MOSFET Basics:

N-channel (NMOS): Electrons are majority carriers

P-channel (PMOS): Holes are majority carriers

V_t = Threshold voltage (turn-on voltage)

MOSFET Operation:

Cutoff Region:

V_gs < V_t: Gate voltage below threshold

I_d ≈ 0 (no channel formed)

Acts like open switch

Linear/Triode Region:

V_gs > V_t and V_ds < (V_gs - V_t)

Channel acts like variable resistor

I_d = (μ·C_ox/2)·(W/L)·[2(V_gs - V_t)V_ds - V_ds²]

R_ds(on) = 1/{(μ·C_ox/2)·(W/L)·(V_gs - V_t)}

Saturation Region:

V_gs > V_t and V_ds ≥ (V_gs - V_t)

Pinch-off occurs: channel narrows at drain

 I_d = (μ·C_ox/2)·(W/L)·(V_gs - V_t)²·(1 + λV_ds)

λ = channel length modulation factor (ideally 0)

Transconductance:

g_m = ∂I_d/∂V_gs

In saturation: g_m = 2·μ·C_ox·(W/L)·(V_gs - V_t)

In linear: g_m = μ·C_ox·(W/L)·V_ds

MOSFET Parameters:

μ = carrier mobility (μ_n for NMOS ~600 cm²/ Vs, μ_p ~200 for PMOS)

C_ox = oxide capacitance per unit area

W/L = width-to-length ratio (device size)

V_t = threshold voltage (0.4-0.8V typically)

MOSFET as Switch:

On state: V_gs >> V_t, R_ds(on) ≈ minimal

Off state: V_gs < V_t, I_d ≈ 0

Power dissipation: P = I_d²·R_ds(on)

Topic 19: PN Junction & Semiconductor Physics

Built-in Potential:

V_bi = (kT/q)·ln(N_d·N_a/n_i²)

V_bi ≈ 0.6-0.7V for silicon at 25°C

k = Boltzmann constant, T = temperature, q = electron charge

n_i = intrinsic carrier concentration

Depletion Width:

₀
W = √[2ε ε_r(V_bi + V_R)/(q·N)]

N = (N_d·N_a)/(N_d + N_a) (reduced doping)

 Grows with reverse bias voltage

Decreases with doping concentration

Depletion Capacitance:

₀ ₀
C_j = ε ε_r·A/W = A·√[q/(2ε ε_r)]·√[N/(V_bi + V_R)]

C_j ∝ 1/√V_R

Used in varactor diodes

Diffusion Current:

I_diff = q·D·n_i²·A/(N_d·L_p + N_a·L_n)

D = diffusion coefficient

L_p, L_n = diffusion lengths

Drift Current:

I_drift = -q·μ·n·E·A

μ = mobility, E = electric field

In reverse bias: I_drift = I_s (saturation current)

Minority Carrier Concentration:

p_n = n_i²/N_d (hole concentration in n-region)

n_p = n_i²/N_a (electron concentration in p-region)

Leakage Current:

I_leak = I_s·(e^(V_d/(nV_t)) - 1)

Depends exponentially on temperature

Doubles every ~6°C (for silicon)

Topic 20: Transistor Gain & Parameters

DC Gain:

β_dc = I_c/I_b (static/DC current gain)

 Typical: 50-500 for BJT

Varies with I_c, V_ce, temperature

AC Gain (Small Signal):

g_m = ∂I_c/∂V_be (transconductance)

g_m ≈ I_c/(V_t) = I_c/26mV at 25°C

r_be = V_t/I_b = β/g_m (base-emitter resistance)

Common Emitter Gain:

Voltage gain: A_v = -g_m·R_c ≈ -(I_c/ V_t)·R_c

Current gain: A_i = β

Power gain: A_p = A_v·A_i

Output Resistance:

CE: r_o ≈ r_ce (Early effect) = V_a/I_c

V_a = Early voltage (50-200V)

Input/Output Impedance:

Z_in = r_be + (β+1)·r_e (where r_e = emitter resistance)

Z_out ≈ R_c||r_ce

PART 5: DIGITAL & ANALOG ELECTRONICS

Topic 21: Amplifier Configurations & Gain

Voltage Gain:

A_v = V_out/ V_in (voltage ratio)

A_v(dB) = 20·log ₁₀|A_v|

Example: A_v = 10 → A_v(dB) = 20 dB

Current Gain:

A_i = I_out/I_in (current ratio)

 A_i(dB) = 20·log ₁₀|A_i|

Power Gain:

A_p = P_out/P_in = A_v·A_i

A_p(dB) = 10·log ₁₀(P_out/P_in)

Decibel Conversions:

20 dB = 10× voltage/current

40 dB = 100× voltage/current

10 dB = 3.16×, 30 dB = 31.6×

-3 dB = 0.707× (half power)

Input Impedance:

Z_in = V_in/I_in

High Z_in preferred for voltage amplifier (less loading)

Used in multimeters, oscilloscopes

Output Impedance:

Z_out = V_out(no load)/I_out(short)

Low Z_out preferred (better voltage regulation)

High Z_out acceptable for current amplifier

Common Emitter:

Voltage gain: A_v = -g_m·R_c = -R_c/r_e

High current gain β

Moderate input/output impedance

180° phase shift

Common Collector (Emitter Follower):

A_v ≈ 1 (voltage follower)

High input impedance

 Low output impedance

0° phase shift (in-phase)

Topic 22: Feedback in Amplifiers

Feedback Factor:

β = V_feedback/ V_output (always positive for stable feedback)

Loop gain: A_loop = A·β

Closed-loop gain: A_f = A/(1 + β·A) = A/(1 + A_loop)

Closed-Loop Gain:

For large loop gain (β·A >> 1): A_f ≈ 1/β

Gain becomes independent of open-loop gain A

Feedback Effects:

Reduces gain by factor (1 + A_loop)

Increases bandwidth by factor (1 + A_loop)

Reduces distortion and noise

Stabilizes gain against component variations

Input Impedance with Feedback:

Z_in(feedback) = Z_in(open-loop)·(1 + A_loop)

Increases for voltage feedback at input

Decreases for current feedback at input

Output Impedance with Feedback:

Z_out(feedback) = Z_out(open-loop)/(1 + A_loop)

Series feedback reduces output impedance

Shunt feedback increases output impedance

Types of Feedback:
 Series-Shunt: Samples voltage, feeds back in series (reduces gain, increases Z_in, decreases

Z_out)

Shunt-Series: Samples current, feeds back in series

Series-Series: Samples voltage, feeds back in series

Shunt-Shunt: Samples current, feeds back in parallel

Loop Gain Stability:

Phase margin: angle between -180° and actual phase at unity gain

Gain margin: gain reduction before instability

45° phase margin ≈ 1.4× gain margin

Topic 23: Operational Amplifier (Op-Amp) Circuits

Ideal Op-Amp Assumptions:

Gain A → ∞ (very large, ~100,000-1,000,000)

Input impedance → ∞ (very high)

Output impedance → 0 (very low)

Bandwidth → ∞

No offset voltage or bias current

Virtual Short Circuit:

For negative feedback: V_+ ≈ V_-

No current flows between inputs

Op-Amp Power Supply:

Single supply: 0 to +V (referenced to ground)

Dual supply: -V to +V (symmetric)

Saturation voltages: V_out,max ≈ V_cc - 1V

Non-Inverting Amplifier:

G = 1 + (R_f/R_in)
 V_out = V_in·(1 + R_f/R_in)

High input impedance: Z_in ≈ ∞

Very low output impedance

Gain always > 1

Example: G = 1 + 1M/1k = 1001

Inverting Amplifier:

G = -(R_f/R_in)

V_out = -V_in·(R_f/R_in)

Input impedance: Z_in = R_in

Can have gain < 1

180° phase inversion

Example: G = -1M/1k = -1000

Summing Amplifier (Inverting Summer):

V_out = -(R_f/R_1·V_1 + R_f/R_2·V_2 + R_f/R_3·V_3)

Weighted summing with inversion

Used in: Audio mixers, D/A converters

Integrator:

V_out = -(1/RC)·∫V_in dt

Slope = -V_in/RC (V/s)

Output ramps up/down based on input

Used in: Ramp generators, function generators

Differentiator:

V_out = -RC·(dV_in/dt)

Output proportional to rate of change

Noisy at high frequencies

Used in: Edge detection, oscillators

Voltage Comparator:

When V_+ > V_-: