Mutah University
Faculty of Engineering
Computer Engineering Department
Error Detection Techniques
Professor Mokhled Tarawneh
March 27, 2026
Even Parity Examples
Example 1
• Data: 1011001 (4 ones → even)
• Parity bit: 0 (keeps total ones even)
• Transmitted codeword: 1011001 0
• Error: Bit 3 flips → 1001001 0
• Receiver counts ones: 1001001 has 3 ones, plus parity 0 → total 3 (odd) → error
detected.
Example 2
• Data: 1100100 (3 ones → odd)
• Parity bit: 1 (makes total ones even: 3+1=4)
• Transmitted codeword: 1100100 1
• Error: Bit 5 flips → 1110100 1
• Receiver counts ones: 1110100 has 4 ones, plus parity 1 → total 5 (odd) → error
detected.
Example 3
• Data: 0001110 (3 ones → odd)
• Parity bit: 1 (total ones become 4)
• Transmitted codeword: 0001110 1
• Error: Bit 7 flips → 0001100 1
• Receiver counts ones: 0001100 has 2 ones, plus parity 1 → total 3 (odd) → error
detected.
Odd Parity Examples
Example 1
• Data: 1011001 (4 ones → even)
• Parity bit: 1 (makes total ones odd: 4+1=5)
• Transmitted codeword: 1011001 1
• Error: Bit 4 flips → 1010001 1
• Receiver counts ones: 1010001 has 3 ones, plus parity 1 → total 4 (even) → error
detected.
1
Example 2
• Data: 1100100 (3 ones → odd)
• Parity bit: 0 (keeps total ones odd)
• Transmitted codeword: 1100100 0
• Error: Bit 2 flips → 1000100 0
• Receiver counts ones: 1000100 has 2 ones, plus parity 0 → total 2 (even) → error
detected.
Example 3
• Data: 0001110 (3 ones → odd)
• Parity bit: 0 (total ones remain odd)
• Transmitted codeword: 0001110 0
• Error: Bit 6 flips → 0001010 0
• Receiver counts ones: 0001010 has 2 ones, plus parity 0 → total 2 (even) → error
detected.
Checksum
Example 1: Two Subunits
Sender Site:
10101010 subunit 1
11001100 subunit 2
----------------
1 01110110 sum (carry out)
01110110 add carry → 01110111 (1s complement sum)
10001000 checksum (complement of sum)
Data transmitted to Receiver is:
10101010 11001100 10001000
Receiver Site:
Adds all three 8-bit words (including checksum) using 1s complement:
10101010
11001100
10001000
--------
1 11111110 sum
11111110 add carry → 11111111
Complement = 00000000 → valid (no error detected).
2
Example 2: Four Subunits
Sender Site:
10110011 subunit 1
01101100 subunit 2
11001010 subunit 3
10101001 subunit 4
First add subunit 1 and 2:
10110011 + 01101100 = 1 00011111 → add carry → 00100000
Add subunit 3:
00100000 + 11001010 = 11101010 (no carry)
Add subunit 4:
11101010 + 10101001 = 1 10010011 → add carry → 10010100 (1s complement sum)
Checksum = complement of 10010100 = 01101011
Data transmitted to Receiver is:
10110011 01101100 11001010 10101001 01101011
Receiver Site:
Adds all five 8-bit words (including checksum) using 1s complement.
If no errors, the final result will be 11111111 and its complement 00000000.
Example 3: Three Subunits (XOR Checksum)
This example uses XOR instead of 1s complement sum to illustrate another common
checksum type.
Sender Site:
11001100 subunit 1
10101010 subunit 2
11110000 subunit 3
XOR of subunit 1 and 2:
11001100 10101010 = 01100110
XOR with subunit 3:
01100110 11110000 = 10010110 (XOR sum)
Checksum = same as XOR sum (no complement needed) = 10010110
Data transmitted to Receiver is:
11001100 10101010 11110000 10010110
Receiver Site:
XORs all four bytes (including checksum).
If no errors, the result is 00000000.
CRC (Cyclic Redundancy Check)
Example 1: CRC-3 with Generator 1011
Generator polynomial: x3 + x + 1 → binary 1011 (degree 3).
Data to transmit: 11010011 (8 bits).
Sender site:
3
1. Append 3 zero bits (degree of generator) to data: 11010011000.
2. Divide by generator 1011 using modulo-2 division (XOR):
11001010 (quotient, not used)
1011 ) 11010011000
1011
----
1100
1011
----
1111
1011
----
1001
1011
----
0101
0000
----
1010
1011
----
001 ← remainder (3 bits)
Remainder = 001.
Transmitted codeword = original data + remainder = 11010011 001.
Receiver site:
Receives 11010011001 (assuming no errors). Divide by 1011:
11001010
1011 ) 11010011001
1011
----
1100
1011
----
1111
1011
----
1001
1011
----
0101
0000
----
1010
1011
----
4
0011
1011
----
000 ← remainder zero → no error detected
Remainder = 000 → valid.
Example 2: CRC-4 with Generator 10011
Generator polynomial: x4 + x + 1 → binary 10011 (degree 4).
Data to transmit: 10101100 (8 bits).
Sender site:
1. Append 4 zeros: 101011000000.
2. Divide by 10011. Using the shift-register algorithm (bit-by-bit):
Let the remainder be updated as each bit is processed. The final remainder is 0011.
Transmitted codeword = 10101100 0011.
Receiver site:
Receives 101011000011. Applying the same algorithm yields remainder 0000 → valid.
Example 3: CRC-8 with Generator 100000111
Generator polynomial: x8 + x2 + x + 1 → binary 100000111 (degree 8).
Data to transmit: 11110000 (8 bits).
Sender site:
1. Append 8 zeros: 1111000000000000 (16 bits).
2. Divide by 100000111. The computed remainder is 10010101.
Transmitted codeword = 11110000 10010101.
Receiver site:
Receives 1111000010010101. Dividing by 100000111 yields remainder 00000000 if no
errors.
Summary of CRC Examples
Example Generator (binary) Data Transmitted Codeword
1 1011 11010011 11010011001
2 10011 10101100 101011000011
3 100000111 11110000 1111000010010101
Table 1: CRC examples summary
In each case, the receiver divides the received codeword by the generator. If the
remainder is zero, the data is assumed error-free; a non-zero remainder indicates an
error.