®

80C88

Data Sheet February 22, 2008 FN2949.4

CMOS 8-/16-Bit Microprocessor Features

The Intersil 80C88 high performance 8-/16-bit CMOS CPU is • Compatible with NMOS 8088
manufactured using a self-aligned silicon gate CMOS
• Direct Software Compatibility with 80C86, 8086, 8088
process (Scaled SAJI IV). Two modes of operation,
MINimum for small systems and MAXimum for larger • 8-Bit Data Bus Interface; 16-Bit Internal Architecture
applications such as multiprocessing, allow user • Completely Static CMOS Design
configuration to achieve the highest performance level.
- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5MHz (80C88)
Full TTL compatibility (with the exception of CLOCK) and - DC . . . . . . . . . . . . . . . . . . . . . . . . . . . .8MHz (80C88-2)
industry-standard operation allow use of existing NMOS
• Low Power Operation
8088 hardware and Intersil CMOS peripherals.
- ICCSB. . . . . . . . . . . . . . . . . . . . . . . . . 500µA Maximum
Complete software compatibility with the 80C86, 8086, and - ICCOP . . . . . . . . . . . . . . . . . . . . . 10mA/MHz Maximum
8088 microprocessors allows use of existing software in new
• 1 Megabyte of Direct Memory Addressing Capability
designs.
• 24 Operand Addressing Modes
• Bit, Byte, Word, and Block Move Operations
• 8-Bit and 16-Bit Signed/Unsigned Arithmetic
• Bus-Hold Circuitry Eliminates Pull-up Resistors
• Wide Operating Temperature Ranges
- C80C88 . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
- I80C88 . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
- M80C88 . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
• Pb-Free Available (RoHS Compliant)

Ordering Information
TEMPERATURE
PART NUMBER PART PART NUMBER PART RANGE
(5MHz) MARKING (8MHz) MARKING (°C) PACKAGE PKG. DWG. #

CP80C88 CP80C88 CP80C88-2 CP80C88-2 0 to +70 40 LD PDIP E40.6

IP80C88 IP80C88 IP80C88-2 IP80C88-2 -40 to +85 40 LD PDIP E40.6

MD80C88/B MD80C88/B -55 to +125 40 LD CERDIP F40.6

CP80C88Z CP80C88Z 0 to +70 40 LD PDIP* E40.6

(Note) (Pb-Free)

NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J
STD-020.

1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Harris Corporation 1997, Copyright Intersil Americas Inc. 2004, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
 80C88

Pinouts
80C88
(40 LD PDIP, 40 LD CERIDP)
TOP VIEW
MIN MAX
MODE MODE
GND 1 40 VCC
A14 2 39 A15
A13 3 38 A16/S3
A12 4 37 A17/S4
A11 5 36 A18/S5
A10 6 35 A19/S6
A9 7 34 SS0 (HIGH)
A8 8 33 MN/MX
AD7 9 32 RD
AD6 10 31 HOLD (RQ/GT0)
AD5 11 30 HLDA (RQ/GT1)
AD4 12 29 WR (LOCK)
AD3 13 28 IO/M (S2)
AD2 14 27 DT/R (S1)
AD1 15 26 DEN (S0)
AD0 16 25 ALE (QS0)
NMI 17 24 INTA (QS1)
INTR 18 23 TEST
CLK 19 22 READY
GND 20 21 RESET

2 FN2949.4
February 22, 2008
 80C88

Functional Diagram
EXECUTION UNIT BUS INTERFACE UNIT
REGISTER FILE RELOCATION
REGISTER FILE
DATA POINTER SEGMENT REGISTERS
AND AND
INDEX REGS INSTRUCTION POINTER
(8 WORDS) (5 WORDS)

SSO/HIGH
16-BIT ALU
4 A19/S6. . . A16/S3
FLAGS
BUS 8 AD7-AD0
INTERFACE
UNIT 8 A8-A15

3 INTA, RD, WR

4 DT/R, DEN, ALE, IO/M

4-BYTE
INSTRUCTION
QUEUE

TEST
INTR LOCK
NMI
CONTROL AND TIMING 2 QS0, QS1
RQ/GT0, 1 2
HOLD 3 S2, S1, S0
HLDA

3
CLK RESET READY MN/MX GND
VCC

MEMORY INTERFACE

C-BUS

INSTRUCTION
STREAM BYTE
B-BUS QUEUE
ES
BUS CS
INTERFACE SS
UNIT DS
IP
EXECUTION UNIT
CONTROL SYSTEM
A-BUS

AH AL
BH BL ARITHMETIC/
LOGIC UNIT
CH CL
EXECUTION DH DL
UNIT
SP
BP
SI
DI FLAGS

3 FN2949.4
February 22, 2008
 80C88
Pin Description
The following pin function descriptions are for 80C88 systems in either minimum or maximum mode. The “local bus” in these
descriptions is the direct multiplexed bus interface connection to the 80C88 (without regard to additional bus buffers).

PIN
SYMBOL NUMBER TYPE DESCRIPTION

MAXIMUM OR MINIMUM MODE. THE “LOCAL BUS” IN THESE DESCRIPTIONS IS THE DIRECT MULTIPLEXEDBUS INTERFACE
CONNECTION TO THE 80C88 (WITHOUT REGARD TO ADDITIONAL BUS BUFFERS).

AD7 thru 9 thru 16 I/O ADDRESS DATA BUS: These lines constitute the time multiplexed memory/IO address (T1) and data
AD0 (T2,T3,Tw and T4) bus. These lines are active HIGH and are held at high impedance to the last valid level
during interrupt acknowledge and local bus “hold acknowledge” or “grant sequence”

A15, 39, 2 thru 8 O ADDRESS BUS: These lines provide address bits 8 through 15 for the entire bus cycle (T1-T4). These
A14 thru A8 lines do not have to be latched by ALE to remain valid. A15-A8 are active HIGH and are held at high
impedance to the last valid logic level during interrupt acknowledge and local bus “hold acknowledge” or
“grant sequence”.

A19/S6, 35 O ADDRESS/STATUS: During T1, these are the four most

A18/S5, 36 O significant address lines for memory operations. During I/O S4 S3 CHARACTERISTICS
A17/S4, 37 O operations, these lines are LOW. During memory and I/O 0 0 Alternate Data
A16/S3 38 O operations, status information is available on these lines during
T2, T3, TW and T4. S6 is always LOW. The status of the 0 1 Stack
interrupt enable flag bit (S5) is updated at the beginning of each
1 0 Code or None
clock cycle. S4 and S3 are encoded as shown.
This information indicates which segment register is presently 1 1 Data
being used for data accessing.
These lines are held at high impedance to the last valid logic
level during local bus “hold acknowledge” or “grant Sequence”.

RD 32 O READ: Read strobe indicates that the processor is performing a memory or I/O read cycle, depending on
the state of the IO/M pin or S2. This signal is used to read devices which reside on the 80C88 local bus.
RD is active LOW during T2, T3, Tw of any read cycle, and is guaranteed to remain HIGH in T2 until the
80C88 local bus has floated.
This line is held at a high impedance logic one state during “hold acknowledge” or “grant sequence”.

READY 22 I READY: is the acknowledgment from the address memory or I/O device that it will complete the data
transfer. The RDY signal from memory or I/O is synchronized by the 82C84A clock generator to from
READY. This signal is active HIGH. The 80C88 READY input is not synchronized. Correct operation is not
guaranteed if the set up and hold times are not met.

INTR 18 I INTERRUPT REQUEST: is a level triggered input which is sampled during the last clock cycle of each
instruction to determine if the processor should enter into an interrupt acknowledge operation. A subroutine
is vectored to via an interrupt vector lookup table located in system memory. It can be internally masked by
software resetting the interrupt enable bit. INTR is internally synchronized. This signal is active HIGH.

TEST 23 I TEST: input is examined by the “wait for test” instruction. If the TEST input is LOW, execution continues,
otherwise the processor waits in an “idle” state. This input is synchronized internally during each clock cycle
on the leading edge of CLK.

NMI 17 I NONMASKABLE INTERRUPT: is an edge triggered input which causes a type 2 interrupt. A subroutine is
vectored to via an interrupt vector lookup table located in system memory. NMI is not maskable internally
by software. A transition from a LOW to HIGH initiates the interrupt at the end of the current instruction.
This input is internally synchronized.

RESET 21 I RESET: cases the processor to immediately terminate its present activity. The signal must transition LOW
to HIGH and remain active HIGH for at least four clock cycles. It restarts execution, as described in the
instruction set description, when RESET returns LOW. RESET is internally synchronized.

CLK 19 I CLOCK: provides the basic timing for the processor and bus controller. It is asymmetric with a 33% duty
cycle to provide optimized internal timing.

VCC 40 VCC: is the +5V power supply pin. A 0.1µF capacitor between pins 20 and 40 recommended for
decoupling.

GND 1, 20 GND: are the ground pins (both pins must be connected to system ground). A 0.1µF capacitor between
pins 1 and 20 is recommended for decoupling.

MN/MX 33 I MINIMUM/MAXIMUM: indicates the mode in which the processor is to operate. The two modes are
discussed in the following sections.

4 FN2949.4
February 22, 2008
 80C88

Pin Description
The following pin function descriptions are for 80C88 system in minimum mode (i.e., MN/MX = VCC). Only the pin functions which
are unique to the minimum mode are described; all other pin functions are as described above.
PIN
SYMBOL NUMBER TYPE DESCRIPTION

MINIMUM MODE SYSTEM (i.e., MN/MX = VCC)

IO/M 28 O STATUS LINE: is an inverted maximum mode S2. It is used to distinguish a memory access from an I/O
access. IO/M becomes valid in the T4 preceding a bus cycle and remains valid until the final T4 of the cycle
(I/O = HIGH, M = LOW). IO/M is held to a high impedance logic one during local bus “hold acknowledge”.

WR 29 O Write: strobe indicates that the processor is performing a write memory or write I/O cycle, depending on
the state of the IO/M signal. WR is active for T2, T3, and Tw of any write cycle. It is active LOW, and is held
to high impedance logic one during local bus “hold acknowledge”.

INTA 24 O INTA: is used as a read strobe for interrupt acknowledge cycles. It is active LOW during T2, T3 and Tw of
each interrupt acknowledge cycle. Note that INTA is never floated.

ALE 25 O ADDRESS LATCH ENABLE: is provided by the processor to latch the address into the 82C82/82C83
address latch. It is a HIGH pulse active during clock low of T1 of any bus cycle. Note that ALE is never
floated.

DT/R 27 O DATA TRANSMIT/RECEIVE: is needed in a minimum system that desires to use an 82C86/82C87 data
bus transceiver. It is used to control the direction of data flow through the transceiver. Logically, DT/R is
equivalent to S1 in the maximum mode, and its timing is the same as for IO/M (T = HIGH, R = LOW). This
signal is held to a high impedance logic one during local bus “hold acknowledge”.

DEN 26 O DATA ENABLE: is provided as an output enable for the 82C86/82C87 in a minimum system which uses
the transceiver. DEN is active LOW during each memory and I/O access, and for INTA cycles. For a read
or INTA cycle, it is active from the middle of T2 until the middle of T4, while for a write cycle, it is active from
the beginning of T2 until the middle of T4. DEN is held to high impedance logic one during local bus “hold
acknowledge”.

HOLD, 31 I HOLD: indicates that another master is requesting a local bus “hold”. To be acknowledged, HOLD must be
HLDA 30 O active HIGH. The processor receiving the “hold” request will issue HLDA (HIGH) as an acknowledgment,
in the middle of a T4 or T1 clock cycle. Simultaneous with the issuance of HLDA the processor will float the
local bus and control lines. After HOLD is detected as being LOW, the processor lowers HLDA, and when
the processor needs to run another cycle, it will again drive the local bus and control lines.
Hold is not an asynchronous input. External synchronization should be provided if the system cannot
otherwise guarantee the set up time.

SS0 34 O STATUS LINE: is logically equivalent to S0 in

the maximum mode. The combination of SS0, IO/M DT/R SS0 CHARACTERISTICS
IO/M and DT/R allows the system to completely 1 0 0 Interrupt Acknowledge
decode the current bus cycle status. SS0 is held
to high impedance logic one during local bus 1 0 1 Read I/O Port
“hold acknowledge”.
1 1 0 Write I/O Port

1 1 1 Halt

0 0 0 Code Access

0 0 1 Read Memory

0 1 0 Write Memory

0 1 1 Passive

5 FN2949.4
February 22, 2008
 80C88

Pin Description (Continued)

The following pin function descriptions are for 80C88 system in maximum mode (i.e., MN/MX = GND). Only the pin functions which
are unique to the maximum mode are described; all other pin functions are as described above.
PIN
SYMBOL NUMBER TYPE DESCRIPTION

MAXIMUM MODE SYSTEM (i.e., MN/MX = GND).

S0 26 O STATUS: is active during clock high of T4, T1 and T2,

S2 S1 S0 CHARACTERISTICS
S1 27 O and is returned to the passive state (1, 1, 1) during T3 or
S2 28 O during Tw when READY is HIGH. This status is used by 0 0 0 Interrupt Acknowledge
the 82C88 bus controller to generate all memory and I/O
0 0 1 Read I/O Port
access control signals. Any change by S2, S1 or S0
during T4 is used to indicate the beginning of a bus 0 1 0 Write I/O Port
cycle, and the return to the passive state in T3 or Tw is 0 1 1 Halt
used to indicate the end of a bus cycle.
These signals are held at a high impedance logic one 1 0 0 Code Access
state during “grant sequence”. 1 0 1 Read Memory
1 1 0 Write Memory
1 1 1 Passive

RQ/GT0, 31 I/O REQUEST/GRANT: pins are used by other local bus masters to force the processor to release the local
RQ/GT1 30 bus at the end of the processor’s current bus cycle. Each pin is bidirectional with RQ/GT0 having higher
priority than RQ/GT1. RQ/GT has internal bus-hold high circuitry and, if unused, may be left unconnected.
The request/grant sequence is as follows (see RQ/GT Timing Sequence):
1. A pulse of one CLK wide from another local bus master indicates a local bus request (“hold”) to the
80C88 (pulse 1).
2. During a T4 or T1 clock cycle, a pulse one clock wide from the 80C88 to the requesting master (pulse
2), indicates that the 80C88 has allowed the local bus to float and that it will enter the “grant sequence”
state at the next CLK. The CPUs bus interface unit is disconnected logically from the local bus during
“grant sequence”.
3. A pulse one CLK wide from the requesting master indicates to the 80C88 (pulse 3) that the “hold”
request is about to end and that the 80C88 can reclaim the local bus at the next CLK. The CPU then
enters T4 (or T1 if no bus cycles pending).
Each master-master exchange of the local bus is a sequence of three pulses. There must be one idle CLK
cycle after bus exchange. Pulses are active LOW.
If the request is made while the CPU is performing a memory cycle, it will release the local bus during T4
of the cycle when all the following conjugations are met:
1. Request occurs on or before T2.
2. Current cycle is not the low bit of a word.
3. Current cycle is not the first acknowledge of an interrupt acknowledge sequence.
4. A locked instruction is not currently executing.
If the local bus is idle when the request is made the two possible events will follow:
1. Local bus will be released during the next clock.
2. A memory cycle will start within 3 clocks. Now the four rules for a currently active memory cycle apply
with condition number 1 already satisfied.

LOCK 29 O LOCK: indicates that other system bus masters are not to gain control of the system bus while LOCK is
active (LOW). The LOCK signal is activated by the “LOCK” prefix instruction and remains active until the
completion of the next instruction. This signal is active LOW, and is held at a high impedance logic one
state during “grant sequence”. In Max Mode, LOCK is automatically generated during T2 of the first INTA
cycle and removed during T2 of the second INTA cycle.

6 FN2949.4
February 22, 2008
 80C88

Pin Description (Continued)

The following pin function descriptions are for 80C88 system in maximum mode (i.e., MN/MX = GND). Only the pin functions which
are unique to the maximum mode are described; all other pin functions are as described above.
PIN
SYMBOL NUMBER TYPE DESCRIPTION

MAXIMUM MODE SYSTEM (i.e., MN/MX = GND).

QS1, QS0 24, 25 O QUEUE STATUS: provide status to allow external

tracking of the internal 80C88 instruction queue. QS1 QS0 CHARACTERISTICS
The queue status is valid during the CLK cycle after 0 0 No Operation
which the queue operation is performed. Note that the
queue status never goes to a high impedance statue 0 1 First Byte of Opcode from
(floated). Queue
1 0 Empty the Queue
1 1 Subsequent Byte from
Queue

34 O Pin 34 is always a logic one in the maximum mode and is held at a high impedance logic one during a “grant
sequence”.

Functional Description this unit serves to increase processor performance through

improved bus bandwidth utilization. Up to 4-bytes of the
Static Operation instruction stream can be queued while waiting for decoding
All 80C88 circuitry is static in design. Internal registers, and execution.
counters and latches are static and require not refresh as
The instruction stream queuing mechanism allows the BIU to
with dynamic circuit design. This eliminates the minimum
keep the memory utilized very efficiently. Whenever there is
operating frequency restriction placed on other
space for at least 1-byte in the queue, the BIU will attempt a
microprocessors. The CMOS 80C88 can operate from DC to
byte fetch memory cycle. This greatly reduces “dead time”:
the specified upper frequency limit. The processor clock may
on the memory bus. The queue acts as a First-In-First-Out
be stopped in either state (high/low) and held there
(FIFO) buffer, from which the EU extracts instruction bytes
indefinitely. This type of operation is especially useful for
as required. If the queue is empty (following a branch
system debug or power critical applications.
instruction, for example), the first byte into the queue
The 80C88 can be single stepped using only the CPU clock. immediately becomes available to the EU.
This state can be maintained as long as is necessary. Single
The execution unit receives pre-fetched instructions from the
step clock operation allows simple interface circuitry to
BIU queue and provides unrelocated operand addresses to
provide critical information for start-up.
the BIU. Memory operands are passed through the BIU for
Static design also allows very low frequency operation (as processing by the EU, which passes results to the BIU for
low as DC). In a power critical situation, this can provide storage.
extremely low power operation since 80C88 power
dissipation is directly related to operation frequency. As the Memory Organization
system frequency is reduced, so is the operating power until, The processor provides a 20-bit address to memory which
at a DC input frequency, the power requirement is the 80C88 locates the byte being referenced. The memory is organized
standby current. as a linear array of up to 1 million bytes, addressed as
00000(H) to FFFFF(H). The memory is logically divided into
Internal Architecture code, data, extra, and stack segments of up to 64-bytes
The internal functions of the 80C88 processor are partitioned each, with each segment falling on 16-byte boundaries. (See
logically into two processing units. The first is the Bus Figure 1).
Interface Unit (BIU) and the second is the Execution Unit
(EU) as shown in the CPU block diagram.

These units can interact directly but for the most part
perform as separate asynchronous operational processors.
The bus interface unit provides the functions related to
instruction fetching and queuing, operand fetch and store,
and address relocation. This unit also provides the basic bus
control. The overlap of instruction pre-fetching provided by

7 FN2949.4
February 22, 2008
 80C88

Certain locations in memory are reserved for specific CPU

.

7 0
FFFFFH operations. (See Figure 2). Locations from addresses
FFFF0H through FFFFFH are reserved for operations
including a jump to initial system initialization routine.
64K-BIT CODE SEGMENT
Following RESET, the CPU will always begin execution at
location FFFF0H where the jump must be located. Locations
XXXXOH
00000H through 003FFH are reserved for interrupt
operations. Each of the 256 possible interrupt service
STACK SEGMENT routines is accessed through its own pair of 16-bit pointers -
+ OFFSET
segment address pointer and offset address pointer. The
first pointer, used as the offset address, is loaded into the IP,
SEGMENT and the second pointer, which designates the base address,
REGISTER FILE
DATA SEGMENT is loaded into the CS. At this point program control is
CS LSB
WORD
SS BYTE transferred to the interrupt routine. The pointer elements are
DS MSB assumed to have been stored at their respective places in
ES
reserved memory prior to the occurrence of interrupts.

EXTRA SEGMENT
Minimum and Maximum Modes
The requirements for supporting minimum and maximum
00000H
80C88 systems are sufficiently different that they cannot be
FIGURE 1. MEMORY ORGANIZATION done efficiently with 40 uniquely defined pins. Consequently,
All memory references are made relative to base addresses the 80C88 is equipped with a strap pin (MN/MX) which
contained in high speed segment registers. The segment defines the system configuration. The definition of a certain
types were chosen based on the addressing needs of subset of the pins changes, dependent on the condition of
programs. The segment register to be selected is the strap pin. When the MN/MX pin is strapped to GND, the
automatically chosen according to specific rules as shown in 80C88 defines pins 24 through 31 and 34 in maximum
Table1. All information in one segment type share the same mode. When the MN/MX pins is strapped to VCC, the 80C88
logical attributes (e.g., code or data). By structuring memory generates bus control signals itself on pins 24 through 31
into relocatable areas of similar characteristics and by and 34.
automatically selecting segment registers, programs are
The minimum mode 80C88 can be used with either a
shorter, faster, and more structured.
muliplexed or demultiplexed bus. This architecture provides
TABLE 1. the 80C88 processing power in a highly integrated form.
MEMORY SEGMENT
The demultiplexed mode requires one latch (for 64k address
REFERENCE REGISTER SEGMENT
NEED USED SELECTION RULE ability) or two latches (for a full megabyte of addressing). An
82C86 or 82C87 transceiver can also be used if data bus
Instructions CODE (CS) Automatic with all instruction
buffering is required. (See Figure 3). The 80C88 provides
prefetch.
DEN and DT/R to control the transceiver, and ALE to latch
Stack STACK (SS) All stack pushes and pops. the addresses. This configuration of the minimum mode
Memory references relative to
provides the standard demultiplexed bus structure with
BP base register except data
references. heavy bus buffering and relaxed bus timing requirements.

Local Data DATA (DS) Data references when: relative The maximum mode employs the 82C88 bus controller (See
to stack, destination of string Figure 4). The 82C88 decode status lines S0, S1 and S2,
operation, or explicitly and provides the system with all bus control signals. Moving
overridden.
the bus control to the 82C88 provides better source and sink
External Data EXTRA (ES) Destination of string current capability to the control lines, and frees the 80C88
(Global) operations: Explicitly selected pins for extended large system features. Hardware lock,
using a segment override.
queue status, and two request/grant interfaces are provided
by the 80C88 in maximum mode. These features allow
Word (16-bit) operands can be located on even or odd
coprocessors in local bus and remote bus configurations.
address boundaries. For address and data operands, the
least significant byte of the word is stored in the lower valued
address location and the most significant byte in the next
higher address location.

The BIU will automatically execute two fetch or write cycles

for 16-bit operands.

8 FN2949.4
February 22, 2008
 80C88

FFFFFH RESET BOOTSTRAP

FFFF0H PROGRAM JUMP

3FFH TYPE 255 POINTER

3FCH (AVAILABLE)

AVAILABLE
INTERRUPT
POINTERS TYPE 33 POINTER
(224) (AVAILABLE)
084H
TYPE 32 POINTER
080H (AVAILABLE)
TYPE 31 POINTER
07FH (AVAILABLE)
RESERVED
INTERRUPT
POINTERS
(27)
TYPE 5 POINTER
014H (RESERVED)
TYPE 4 POINTER
010H OVERFLOW
TYPE 3 POINTER
00CH 1 BYTE INT INSTRUCTION
DEDICATED TYPE 2 POINTER
INTERRUPT NON MASKABLE
POINTERS 008H
(5) TYPE 1 POINTER
004H SINGLE STEP
TYPE 0 POINTER CS BASE ADDRESS
000H DIVIDE ERROR IP OFFSET

16-BITS

FIGURE 2. RESERVED MEMORY LOCATIONS

Bus Operation During T1 of any bus cycle, the ALE (Address latch enable)
The 80C88 address/data bus is broken into three parts: the signal is emitted (by either the processor or the 82C88 bus
lower eight address/data bits (AD0-AD7), the middle eight controller, depending on the MN/MX strap). At the trailing
address bits (A8-A15), and the upper four address bits (A16- edge of this pulse, a valid address and certain status
A19). The address/data bits and the highest four address information for the cycle may be latched.
bits are time multiplexed. This technique provides the most Status bits S0, S1, and S2 are used by the bus controller, in
efficient use of pins on the processor, permitting the use of maximum mode, to identify the type of bus transaction
standard 40 lead package. The middle eight address bits are according to Table 2.
not multiplexed, i.e., they remain valid throughout each bus
cycle. In addition, the bus can be demultiplexed at the Status bits S3 through S6 are multiplexed with high order
processor with a single address latch if a standard, non address bits and are therefore valid during T2 through T4.
multiplexed bus is desired for the system. S3 and S4 indicate which segment register was used to this
bus cycle in forming the address according to Table 3.
Each processor bus cycle consists of at least four CLK
cycles. These are referred to as T1, T2, T3 and T4. (See S5 is a reflection of the PSW interrupt enable bit. S6 is
Figure 5). The address is emitted from the processor during always equal to 0.
T1 and data transfer occurs on the bus during T3 and T4. T2
is used primarily for changing the direction of the bus during
read operations. In the event that a “Not Ready” indication is
given by the addressed device, “wait” states (TW) are
inserted between T3 and T4. Each inserted “wait” state is of
the same duration as a CLK cycle. Periods can occur
between 80C88 driven bus cycles. These are referred to as
“idle” states (TI), or inactive CLK cycles. The processor uses
these cycles for internal housekeeping.

9 FN2949.4
February 22, 2008
 80C88

VCC

MN/MX VCC
82C84A/85
CLK IO/M
RES READY RD
RESET WR
RDY

CLOCK
GND GENERATOR INTA
80C88 DT/R
CPU
DEN

1 ALE STB
GND GND OE
C1 AD0-AD7 ADDR/DATA
VCC A8-A19 82C82 ADDRESS
20 LATCH
GND (1, 2 OR 3)
C2
40
VCC
T
C1 = C2 = 0.1μF INTR
OE
82C86 DATA
TRANSCEIVER

EN OE CS RDWR
82C59A
INTERRUPT HM-65162 HS-6616 82CXX
CONTROL CMOS PROM CMOS PROM PERIPHERALS
INT
IR0-7

FIGURE 3. DEMULTIPLEXED BUS CONFIGURATION

VCC

MN/MX GND CLK MRDC

82C84A/85
CLK S0 S0 MWTC
READY S1 82C88 AMWC NC
RES S1
RESET S2 IORC
RDY S2
DEN IOWC
DT/R AIOWC NC
GND ALE INTA
80C88
CPU

1 STB
GND GND OE
C1 AD0-AD7 ADDR/DATA
VCC 82C82 ADDRESS
20 A8-A19
LATCH
GND (1, 2 OR 3)
C2
40
VCC
T
C1 = C2 = 0.1μF INT
OE
82C86 DATA
TRANSCEIVER

OE CS RDWR
82C59A
INTERRUPT HM-65162 HS-6616 82CXX
CONTROL CMOS PROM CMOS PROM PERIPHERALS

IR0-7

FIGURE 4. FULLY BUFFERED SYSTEM USING BUS CONTROLLER

10 FN2949.4
February 22, 2008
 80C88

(4 + NWAIT) = TCY (4 + NWAIT) = TCY

T1 T2 T3 TWAIT T4 T1 T2 T3 TWAIT T4

CLK

GOES INACTIVE IN THE STATE

JUST PRIOR TO T4
ALE

S2-S0

ADDR
STATUS A19-A16 S6-S3 A19-A16 S6-S3

ADDR A15-A8 A15-A8

ADDR DATA BUS RESERVED D15-D0

A7-A0 A7-A0 DATA OUT (D7-D0)
FOR DATA IN VALID

RD, INTA

READY READY

READY

WAIT WAIT

DT/R

DEN

MEMORY ACCESS TIME

WP

FIGURE 5. BASIC SYSTEM TIMING

TABLE 2.
TABLE 3.
S2 S1 S0 CHARACTERISTICS
S4 S3 CHARACTERISTICS
0 0 0 Interrupt Acknowledge
0 0 Alternate Data (Extra Segment)
0 0 1 Read I/O
0 1 Stack
0 1 0 Write I/O
1 0 Code or None
0 1 1 Halt
1 1 Data
1 0 0 Instruction Fetch

1 0 1 Read Data from Memory

I/O Addressing
1 1 0 Write Data to Memory In the 80C88, I/O operations can address up to a maximum
1 1 1 Passive (No Bus Cycle) of 64k I/O registers. The I/O address appears in the same
format as the memory address on bus lines A15-A0. The
address lines A19-A16 are zero in I/O operations. The
variable I/O instructions, which use register DX as a pointer,
have full address capability, while the direct I/O instructions
directly address one or two of the 256 I/O byte locations in
page 0 of the I/O address space. I/O ports are addressed in
the same manner as memory locations.

11 FN2949.4
February 22, 2008
 80C88

Designers familiar with the 8085 or upgrading an 8085 appropriate element to the new interrupt service program
design should note that the 8085 addresses I/O with an 8-bit location.
address on both halves of the 16-bit address bus. The
80C88 uses a full 16-bit address on its lower 16 address BOND EXTERNAL
PAD PIN
lines.
OUTPUT
DRIVER
External Interface
INPUT
Processor Reset and Initialization BUFFER
INPUT
Processor initialization or start up is accomplished with PROTECTION
CIRCUITRY
activation (HIGH) of the RESET pin. The 80C88 RESET is
required to be HIGH for greater than four clock cycles. The FIGURE 6A. BUS HOLD CIRCUITRY PINS 2-16 AND 35-39
80C88 will terminate operations on the high-going edge of
RESET and will remain dormant as long as RESET is HIGH.
The low-going transition of RESET triggers an internal reset BOND EXTERNAL
PAD PIN
sequence for approximately 7 clock cycles. After this interval VCC P
OUTPUT
the 80C88 operates normally, beginning with the instruction DRIVER
in absolute location FFFFOH (see Figure 2). The RESET
input is internally synchronized to the processor clock. At INPUT
BUFFER
initialization, the HIGH to LOW transition of RESET must INPUT
PROTECTION
occur no sooner than 50μs after power up, to allow complete CIRCUITRY
initialization of the 80C88.
FIGURE 6B. BUS HOLD CIRCUITRY PINS 26-32 AND 34
NMI will not be recognized if asserted prior to the second FIGURE 6.
CLK cycle following the end of RESET.

Bus Hold Circuitry Non-Maskable Interrupt (NMI)

To avoid high current conditions caused by floating inputs to The processor provides a single non-maskable interrupt
CMOS devices and to eliminate the need for pull-up/down (NMI) pin which has higher priority than the maskable
resistors, “bus-hold” circuitry has been used on 80C88 pins interrupt request (INTR) pin. A typical use would be to
2-16, 26-32 and 34-39 (see Figure 6A and 6B). These activate a power failure routine. The NMI is edge-triggered
circuits maintain a valid logic state if no driving source is on a LOW to High transition. The activation of this pin
present (i.e., an unconnected pin or a driving source which causes a type 2 interrupt.
goes to a high impedance state).
NMI is required to have a duration in the HIGH state of
To override the “bus hold” circuits, an external driver must be greater than two clock cycles, but is not required to be
capable of supplying 400μA minimum sink or source current synchronized to the clock. An high going transition of NMI is
at valid input voltage levels. Since this “bus hold” circuitry is latched on-chip and will be serviced at the end of the current
active and not a “resistive” type element, the associated instruction or between whole moves (2-bytes in the case of
power supply current is negligible. Power dissipation is word moves) of a block type instruction. Worst case
significantly reduced when compared to the use of passive response to NMI would be for multiply, divide, and variable
pull-up resistors. shift instructions. There is no specification on the occurrence
Interrupt Operations of the low-going edge; it may occur before, during, or after
the servicing of NMI. Another high-going edge triggers
Interrupt operations fall into two classes: software or
another response if it occurs after the start of the NMI
hardware initiated. The software initiated interrupts and
procedure.
software aspects of hardware interrupts are specified in the
instruction set description. Hardware interrupts can be The signal must be free of logical spikes in general and be
classified as nonmusical or maskable. free of bounces on the low-going edge to avoid triggering
extraneous responses.
Interrupts result in a transfer of control to a new program
location. A 256 element table containing address pointers to Maskable Interrupt (INTR)
the interrupt service program locations resides in absolute The 80C88 provides a singe interrupt request input (INTR)
locations 0 through 3FFH (see Figure 2), which are reserved which can be masked internally by software with the
for this purpose. Each element in the table is 4-bytes in size resetting of the interrupt enable (IF) flag bit. The interrupt
and corresponds to an interrupt “type”. An interrupting request signal is level triggered. It is internally synchronized
device supplies an 8-bit type number, during the interrupt during each clock cycle on the high-going edge of CLK.
acknowledge sequence, which is used to vector through the

12 FN2949.4
February 22, 2008
 80C88

To be responded to, INTR must be present (HIGH) during An interrupt request or RESET will force the 80C88 out of
the clock period preceding the end of the current instruction the HALT state.
or the end of a whole move for a block type instruction. INTR
Read/Modify/Write (Semaphore) Operations Via
may be removed anytime after the falling edge of the first
LOCK
INTA signal. During interrupt response sequence, further
interrupts are disabled. The enable bit is reset as part of the The LOCK status information is provided by the processor
response to any interrupt (INTR, NMI, software interrupt, or when consecutive bus cycles are required during the
single step). The FLAGS register, which is automatically execution of an instruction. This allows the processor to
pushed onto the stack, reflects the state of the processor perform read/modify/write operations on memory (via the
prior to the interrupt. The enable bit will be zero until the old “exchange register with memory” instruction), without
FLAGS register is restored, unless specifically set by an another system bus master receiving intervening memory
instruction. cycles. This is useful in multiprocessor system
configurations to accomplish “test and set lock” operations.
During the response sequence (see Figure 7), the processor The LOCK signal is activated (LOW) in the clock cycle
executes two successive (back-to-back) interrupt following decoding of the LOCK prefix instruction. It is
acknowledge cycles. The 80C88 emits to LOCK signal deactivated at the end of the last bus cycle of the instruction
(maximum mode only) from T2 of the first bus cycle until T2 following the LOCK prefix. While LOCK is active, a request
of the second. A local bus “hold” request will not be honored on a RQ/GT pin will be recorded, and then honored at the
until the end of the second bus cycle. In the second bus end of the LOCK.
cycle, a byte is fetched from the external interrupt system
(e.g., 82C59A PIC) which identifies the source (type) of the External Synchronization Via TEST
interrupt. This byte is multiplied by four and used as a As an alternative to interrupts, the 80C88 provides a single
pointer into the interrupt vector lookup table. software-testable input pin (TEST). This input is utilized by
executing a WAIT instruction. The single WAIT instruction is
An INTR signal left HIGH will be continually responded to
repeatedly executed until the TEST input goes active (LOW).
within the limitations of the enable bit and sample period.
The execution of WAIT does not consume bus cycles once
INTR may be removed anytime after the falling edge of the
the queue is full.
first INTA signal. The interrupt return instruction includes a
flags pop which returns the status of the original interrupt If a local bus request occurs during WAIT execution, the
enable bit when it restores the flags. 80C88 three-states all output drivers while inputs and I/O
pins are held at valid logic levels by internal bus-hold
circuits. If interrupts are enabled, the 80C88 will recognize
T1 T2 T3 T4 T1 T2 T3 T4 interrupts and process them when it regains control of the
ALE bus.

Basic System Timing

LOCK In minimum mode, the MN/MX pin is strapped to VCC and
the processor emits bus control signals (RD, WR, IO/M, etc.)
directly. In maximum mode, the MN/MX pin is strapped to
INTA
GND and the processor emits coded status information
which the 82C88 bus controller uses to generate
AD0- TYPE
AD7 VECTOR
MULTIBUS™ compatible bus control signals.

System Timing - Minimum System

FIGURE 7. INTERRUPT ACKNOWLEDGE SEQUENCE
The read cycle begins in T1 with the assertion of the address
Halt latch enable (ALE) signal (see Figure 5). The trailing (low
When a software HALT instruction is executed, the going) edge of this signal is used to latch the address
processor indicates that it is entering the HALT state in one information, which is valid on the address data bus (ADO-
of two ways, depending upon which mode is strapped. In AD7) at this time, into the 82C82/82C83 latch. Address lines
minimum mode, the processor issues ALE, delayed by one A8 through A15 do not need to be latched because they
clock cycle, to allow the system to latch the halt status. Halt remain valid throughout the bus cycle. From T1 to T4 the
status is available on IO/M, DT/R, and SS0. In maximum IO/M signal indicates a memory or I/O operation. At T2 the
mode, the processor issues appropriate HALT status on S2, address is removed from the address data bus and the bus
S1 and S0, and the 82C88 bus controller issues one ALE. is held at the last valid logic state by internal bus-hold
The 80C88 will not leave the HALT state when a local bus devices. The read control signal is also asserted at T2. The
hold is entered while in HALT. In this case, the processor read (RD) signal causes the addressed device to enable its
reissues the HALT indicator at the end of the local bus hold. data bus drivers to the local bus. Some time later, valid data

13 FN2949.4
February 22, 2008
 80C88

will be available on the bus and the addressed device will disabled when reading from the master 82C59A during the
drive the READY line HIGH. When the processor returns the interrupt acknowledge sequence and software “poll”.
read signal to a HIGH level, the addressed device will again
The 80C88 Compared to the 80C86
three-state its bus drivers. If a transceiver (82C86/82C87) is
required to buffer the local bus, signals DT/R and DEN are The 80C88 CPU is a 8-bit processor designed around the
provided by the 80C88. 8086 internal structure. Most internal functions of the 80C88
are identical to the equivalent 80C86 functions. The 80C88
A write cycle also begins with the assertion of ALE and the handles the external bus the same way the 80C86 does with
emission of the address. The IO/M signal is again asserted the distinction of handling only 8-bits at a time. Sixteen-bit
to indicate a memory or I/O write operation. In T2, operands are fetched or written in two consecutive bus
immediately following the address emission, the processor cycles. Both processors will appear identical to the software
emits the data to be written into the addressed location. This engineer, with the exception of execution time. The internal
data remains valid until at least the middle of T4. During T2, register structure is identical and all instructions have the
T3, and Tw, the processor asserts the write control signal. same end result. Internally, there are three differences
The write (WR) signal becomes active at the beginning of between the 80C88 and the 80C86. All changes are related
T2, as opposed to the read, which is delayed somewhat into to the 8-bit bus interface.
T2 to provide time for output drivers to become inactive.
• The queue length is 4-bytes in the 80C88, whereas the
The basic difference between the interrupt acknowledge 80C86 queue contains 6-bytes, or three words. The queue
cycle and a read cycle is that the interrupt acknowledge was shortened to prevent overuse of the bus by the BIU
(INTA) signal is asserted in place of the read (RD) signal and when prefetching instructions. This was required because
the address bus is held at the last valid logic state by internal of the additional time necessary to fetch instructions 8-bits
bus-hold devices (see Figure 6. In the second of two at a time.
successive INTA cycles, a byte of information is read from • To further optimize the queue, the prefetching algorithm
the data bus, as supplied by the interrupt system logic (i.e., was changed. The 80C88 BIU will fetch a new instruction
82C59A priority interrupt controller). This byte identifies the to load into the queue each time there is a 1-byte space
source (type) of the interrupt. It is multiplied by four and used available in the queue. The 80C86 waits until a 2-byte
as a pointer into the interrupt vector lookup table, as space is available.
described earlier. The internal execution time of the instruction set is affected
Bus Timing - Medium Complexity Systems by the 8-bit interface. All 16-bit fetches and writes from/to
memory take an additional four clock cycles. The CPU is
For medium complexity systems, the MN/MX pin is
also limited by the speed of instruction fetches. This latter
connected to GND and the 82C88 bus controller is added to
problem only occurs when a series of simple operations
the system, as well as an 82C82/82C83 latch for latching the
occur. When the more sophisticated instructions of the
system address, and an 82C86/82C87 transceiver to allow
80C88 are being used, the queue has time to fill the
for bus loading greater than the 80C88 is capable of
execution proceeds as fast as the execution unit will allow.
handling (see Figure 8). Signals ALE, DEN, and DT/R are
generated by the 82C88 instead of the processor in this The 80C88 and 80C86 are completely software compatible
configuration, although their timing remains relatively the by virtue of their identical execution units. Software that is
same. The 80C88 status outputs (S2, S1 and S0) provide system dependent may not be completely transferable, but
type of cycle information and become 82C88 inputs. This software that is not system dependent will operate equally as
bus cycle information specifies read (code, data or I/O), write well on an 80C88 or an 80C86.
(data or I/O), interrupt acknowledge, or software halt. The
The hardware interface of the 80C88 contains the major
82C88 thus issues control signals specifying memory read
differences between the two CPUs. The pin assignments are
or write, I/O read or write, or interrupt acknowledge. The
nearly identical, however, with the following functional
82C88 provides two types of write strobes, normal and
changes:
advanced, to be applied as required. The normal write
strobes have data valid at the leading edge of write. The • A8-A15: These pins are only address outputs on the
advanced write strobes have the same timing as read 80C88. These address lines are latched internally and
strobes, and hence, data is not valid at the leading edge of remain valid throughout a bus cycle in a manner similar to
write. The 82C86/82C87 transceiver receives the usual T the 8085 upper address lines.
and OE inputs from the 82C88 DT/R and DEN outputs. • BHE has no meaning on the 80C88 and has been
The pointer into the interrupt vector table, which is passed eliminated.
during the second INTA cycle, can derive from an 82C59A • SS0 provides the S0 status information in the minimum
located on either the local bus or the system bus. If the mode. This output occurs on pin 34 in minimum mode
master 82C59A priority interrupt controller is positioned on
the local bus, the 82C86/82C87 transceiver must be

14 FN2949.4
February 22, 2008
 80C88

only. DT/R, IO/M and SS0 provide the complete bus status
in minimum mode.
• IO/M has been inverted to be compatible with the 8085
bus structure.
• ALE is delayed by one clock cycle in the minimum mode
when entering HALT, to allow the status to be latched with
ALE.

T1 T2 T3 T4

CLK

QS1, QS0

80C88
S2, S1, S0

A19/S6 - A16/S3 A19 - A16 S6 - S3

ALE

80C88 RDY 82C84

READY 80C88

AD7 - AD0 DATA OUT A7-A0 DATA IN

80C88 A15 - A8 A15 - A8

RD

DT/R

80C88 MRDC

DEN

FIGURE 8. MEDIUM COMPLEXITY SYSTEM TIMING

15 FN2949.4
February 22, 2008
 80C88

Absolute Maximum Ratings Thermal Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Thermal Resistance (Typical) . . . . . . . . . . . . . . . . . . . . . .θJA (oC/W)
Input, Output or I/O Voltage . . . . . . . . . . . GND - 0.5V to VCC + 0.5V PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 CERDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Maximum Junction Temperature
Operating Conditions Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C
Plastic Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Storage Temperature Range . . . . . . . . . . . . . . . . . -65°C to +150°C
M80C88-2 Only . . . . . . . . . . . . . . . . . . . . . . . . . +4.75V to +5.25V Pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . . . see link below
Operating Temperature Range
[Link]
C80C88/-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
*Pb-free PDIPs can be used for through hole wave solder processing
I80C88/-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C only. They are not intended for use in Reflow solder processing applica-
M80C88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
tions.

Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9750 Gates

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.

Electrical Specifications VCC = 5.0V, ±10%; TA = 0°C to +70°C (C80C88, C80C88-2)

VCC = 5.0V, ±10%; TA = -40°C to +85°C (l80C88, I80C88-2)
VCC = 5.0V, ±10%; TA = -55°C to +125°C (M80C88)
SYMBOL PARAMETER TEST CONDITION MIN MAX UNITS
VlH Logical One Input Voltage C80C88, I80C88 (Note 4) 2.0 - V
M80C88 (Note 4) 2.2 V
VIL Logical Zero Input Voltage - 0.8 V
VIHC CLK Logical One Input Voltage VCC - 0.8 - V
VILC CLK Logical Zero Input Voltage - 0.8 V
VOH Output High Voltage lOH = -2.5mA 3.0 - V
lOH = -100µA VCC - 0.4 V
VOL Output Low Voltage lOL = +2.5mA - 0.4 V
II Input Leakage Current VIN = 0V or VCC -1.0 1.0 µA
Pins 17 thru 19, 21 thru 23 and 33
lBHH Input Current-Bus Hold High VIN = - 3.0V (Note 1) -40 -400 µA
lBHL Input Current-Bus Hold Low VIN = - 0.8V (Note 2) 40 400 µA
IO Output Leakage Current VOUT = 0V (Note 5) - -10.0 µA
ICCSB Standby Power Supply Current VCC = 5.5V (Note 3) - 500 µA
ICCOP Operating Power Supply Current FREQ = Max, VIN = VCC or GND, - 10 mA/MHz
Outputs Open
NOTES:
1. lBHH should be measured after raising VIN to VCC and then lowering to 3.0V on the following pins 2 thru16, 26 thru 32, 34 thru 39.
2. IBHL should be measured after lowering VIN to GND and then raising to 0.8V on the following pins: 2 thru16, 35 thru 39.
3. lCCSB tested during clock high time after HALT instruction executed. VIN = VCC or GND, VCC = 5.5V, Outputs unloaded.
4. MN/MX is a strap option and should be held to VCC or GND.
5. IO should be measured by putting the pin in a high impedance state and then driving VOUT to GND on the following pins: 26-29 and 32.

Capacitance TA = +25°C
SYMBOL PARAMETER TEST CONDITIONS TYPICAL UNITS

CIN Input Capacitance FREQ = 1MHz. All measurements are referenced to device GND 25 pF
COUT Output Capacitance FREQ = 1MHz. All measurements are referenced to device GND 25 pF

CI/O I/O Capacitance FREQ = 1MHz. All measurements are referenced to device GND 25 pF

16 FN2949.4
February 22, 2008
 80C88

AC Electrical Specifications VCC = 5.0V ±10%; TA = 0°C to +70°C (C80C88, C80C88-2)

VCC = 5.0V ±10%; TA = -40°C to +85°C (I80C88, I80C88-2)
VCC = 5.0V ±10%; TA = -55° to +125°C (M80C88)

80C88 80C88-2
TEST
SYMBOL PARAMETER CONDITIONS MIN MAX MIN MAX UNITS

MINIMUM COMPLEXITY SYSTEM

Timing Requirements

(1) TCLCL CLK Cycle Period 200 - 125 - ns

(2) TCLCH CLK Low Time 118 - 68 - ns

(3) TCHCL CLK High Time 69 - 44 - ns

(4) TCH1CH2 CLK Rise Time From 1.0V to 3.5V - 10 - 10 ns

(5) TCL2CL1 CLK FaIl Time From 3.5V to 1.0V - 10 - 10 ns

(6) TDVCL Data In Setup Time 30 - 20 - ns

(7) TCLDX1 Data In Hold Time 10 - 10 - ns

(8) TR1VCL RDY Setup Time into 82C84A 35 - 35 - ns

(Notes 6,7)
(9) TCLR1X RDY Hold Time into 82C84A 0 - 0 - ns
(Notes 6,7)

(10) TRYHCH READY Setup Time into 80C88 118 - 68 - ns

(11) TCHRYX READY Hold Time into 80C88 30 - 20 - ns

(12) TRYLCL READY Inactive to CLK (Note 8) -8 - -8 - ns

(13) THVCH HOLD Setup Time 35 - 20 - ns

(14) TINVCH lNTR, NMI, TEST Setup Time 30 - 15 - ns

(Note 7)

(15) TILIH Input Rise Time (Except CLK) From 0.8V to 2.0V - 15 - 15 ns

(16) TIHIL Input FaIl Time (Except CLK) From 2.0V to 0.8V - 15 - 15 ns

Timing Responses

(17) TCLAV Address Valid Delay CL = 100pF 10 110 10 60 ns

(18) TCLAX Address Hold Time CL = 100pF 10 - 10 - ns

(19) TCLAZ Address Float Delay CL = 100pF TCLAX 80 TCLAX 50 ns

(20) TCHSZ Status Float Delay CL = 100pF - 80 - 50 ns

(21) TCHSV Status Active Delay CL = 100pF 10 110 10 60 ns

(22) TLHLL ALE Width CL = 100pF TCLCH-20 - TCLCH-10 - ns

(23) TCLLH ALE Active Delay CL = 100pF - 80 - 50 ns

(24) TCHLL ALE Inactive Delay CL = 100pF - 85 - 55 ns

(25) TLLAX Address Hold Time to ALE CL = 100pF TCHCL-10 - TCHCL-10 - ns

Inactive

(26) TCLDV Data Valid Delay CL = 100pF 10 110 10 60 ns

(27) TCLDX2 Data Hold Time CL = 100pF 10 - 10 - ns

(28) TWHDX Data Hold Time After WR CL = 100pF TCLCL-30 - TCLCL-30 - ns

(29) TCVCTV Control Active Delay 1 CL = 100pF 10 110 10 70 ns

(30) TCHCTV Control Active Delay 2 CL = 100pF 10 110 10 60 ns

(31) TCVCTX Control Inactive Delay CL = 100pF 10 110 10 70 ns

(32) TAZRL Address Float to READ Active CL = 100pF 0 - 0 - ns

17 FN2949.4
February 22, 2008
 80C88

AC Electrical Specifications VCC = 5.0V ±10%; TA = 0°C to +70°C (C80C88, C80C88-2)

VCC = 5.0V ±10%; TA = -40°C to +85°C (I80C88, I80C88-2)
VCC = 5.0V ±10%; TA = -55° to +125°C (M80C88) (Continued)

80C88 80C88-2
TEST
SYMBOL PARAMETER CONDITIONS MIN MAX MIN MAX UNITS

(33) TCLRL RD Active Delay CL = 100pF 10 165 10 100 ns

(34) TCLRH RD Inactive Delay CL = 100pF 10 150 10 80 ns

(35) TRHAV RD Inactive to Next Address CL = 100pF TCLCL-45 - TCLCL-40 - ns

Active

(36) TCLHAV HLDA Valid Delay CL = 100pF 10 160 10 100 ns

(37) TRLRH RD Width CL = 100pF 2TCLCL-75 - 2TCLCL-50 - ns

(38) TWLWH WR Width CL = 100pF 2TCLCL-60 - 2TCLCL-40 - ns

(39) TAVAL Address Valid to ALE Low CL = 100pF TCLCH-60 - TCLCH-40 - ns

(40) TOLOH Output Rise Time From 0.8V to 2.0V - 15 - 15 ns

(41) TOHOL Output Fall Time From 2.0V to 0.8V - 15 - 15 ns

NOTES:
6. Signal at 82C84A shown for reference only.
7. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.
8. Applies only to T2 state (8ns into T3).

18 FN2949.4
February 22, 2008
 80C88

Waveforms
T1 T2 T3 T4
(5) TW
(1)
TCLCL TCL2CL1
TCH1CH2
CLK (82C84A OUTPUT) (4)
(3) (2)
TCHCL TCLCH TCHCTV
(30) TCHCTV (30)
IO/M, SSO

(17)
TCLAV
A15-A8 A15-A8 (FLOAT DURING INTA)

(17) (26) TCLDV (17)

TCLAV (18) TCLAX TCLAV

A19/S6-A16/S3 A19-A16 S6-S3

(23) TCLLH TLHLL

(22) TLLAX
(25)
ALE
(24)
TCHLL TR1VCL (8)
RDY (82C84A INPUT) VIH
TAVAL
SEE NOTE 9, 10 (39)
VIL
TCLR1X (9)
(12)
TRYLCL

(11)
READY (80C88 INPUT)
TCHRYX

(10)
TRYHCH (7)
(19) (16) TCLDX1
TCLAZ TDVCL

AD7-AD0 AD7-AD0 DATA IN

(32) TAZRL (34) TCLRH TRHAV (35)

RD
READ CYCLE (30) (30)
TRLRH TCHCTV
(WR, INTA = VOH) TCHCTV TCLRL (37)
(33)
DT/R

(29) TCVCTV TCVCTX

(31)
DEN

FIGURE 9. BUS TIMING - MINIMUM MODE SYSTEM

NOTES:
9. RDY is sampled near the end of T2, T3, TW to determine if TW machine states are to be inserted.
10. Signals at 82C84A are shown for reference only.

19 FN2949.4
February 22, 2008
 80C88

Waveforms (Continued)

T1 T2 T3 TW T4
(4) (5)
TCH1CH2 TCL2CL1

CLK (82C84A OUTPUT) TW

(26)
(17) (27)
TCLDV TCLDX2
TCLAV TCLAX (18)

AD7-AD0 AD7-AD0 DATA OUT

TWHDX (28)
TCVCTV (29) (31) TCVCTX
WRITE CYCLE DEN

(29) TCVCTV (38)

TWLWH
WR

TCVCTX (31)
(19)
TCLAZ TDVCL (6)
TCLDX1 (7)

AD7-AD0 POINTER
TCHCTV (30)
TCHCTV
(30)
DT/R
INTA CYCLE
(NOTE 11) (29) TCVCTV
RD, WR = VOH
INTA

TCVCTX
(29) TCVCTV
(31)

DEN

SOFTWARE
HALT -
AD7-AD0 INVALID ADDRESS SOFTWARE HALT
DEN, RD,
WR, INTA = VOH TCLAV
(17) TCHLL
(24)

ALE

TCHCTV TCLLH TCVCTX

(30) (23) (31)
IO/M
DT/R
SSO

FIGURE 10. BUS TIMING - MINIMUM MODE SYSTEM (Continued)

NOTES:
1. Two INTA cycles run back-to-back. The 80C88 local ADDR/DATA bus is floating during both INTA cycles. Control signals are shown for the
second INTA cycle.
2. Signals at 82C84A are shown for reference only.

20 FN2949.4
February 22, 2008
 80C88

AC Electrical Specifications VCC = 5.0V±10%; TA = 0°C to +70°C (C80C88, C80C88-2)

VCC = 5.0V±10%; TA = -40°C to +85°C (I80C88, I80C88-2)
VCC = 5.0V±10%; TA = -55°C to +125°C (M80C88)
MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER)
80C88 80C88-2

SYMBOL PARAMETER TEST CONDITIONS MIN MAX MIN MAX UNITS

TIMING REQUIREMENTS

(1) TCLCL CLK Cycle Period 200 - 125 - ns

(2) TCLCH CLK Low Time 118 - 68 - ns

(3) TCHCL CLK High Time 69 - 44 - ns

(4) TCH1CH2 CLK Rise Time From 1.0V to 3.5V - 10 - 10 ns

(5) TCL2CL1 CLK Fall Time From 3.5V to 1.0V - 10 - 10 ns

(6) TDVCL Data in Setup Time 30 - 20 - ns

(7) TCLDX1 Data In Hold Time 10 - 10 - ns

(8) TR1VCL RDY Setup Time into 82C84 35 - 35 - ns

(Notes 13,14)
(9) TCLR1X RDY Hold Time into 82C84 0 - 0 - ns
(Notes 13,14)

(10) TRYHCH READY Setup Time into 80C88 118 - 68 - ns

(11) TCHRYX READY Hold Time into 80C88 30 - 20 - ns

(12) TRYLCL READY Inactive to CLK (Note15) -8 - -8 - ns

(13) TlNVCH Setup Time for Recognition 30 - 15 - ns

(lNTR, NMl, TEST) (Note 14)

(14) TGVCH RQ/GT Setup Time 30 - 15 - ns

(15) TCHGX RQ Hold Time into 80C88 (Note 16) 40 TCHCL + 30 TCHCL + ns
10 10

(16) TILlH Input Rise Time (Except CLK) From 0.8V to 2.0V - 15 - 15 ns

(17) TIHIL Input Fall Time (Except CLK) From 2.0V to 0.8V - 15 - 15 ns

TIMING RESPONSES
(18) TCLML Command Active Delay (Note13) 5 35 5 35 ns

(19) TCLMH Command Inactive (Note 13) 5 35 5 35 ns

(20) TRYHSH READY Active to Status Passive - 110 - 65 ns

(Notes 15, 17)

(21) TCHSV Status Active Delay 10 110 10 60 ns

(22) TCLSH Status Inactive Delay (Note 17) 10 130 10 70 ns

(23) TCLAV Address Valid Delay 10 110 10 60 ns

CL = 100pF
(24) TCLAX Address Hold Time for all 80C88 outputs in 10 - 10 - ns
addition to internal
(25) TCLAZ Address Float Delay loads. TCLAX 80 TCLAX 50 ns

(26) TCHSZ Status Float Delay - 80 - 50 ns

(27) TSVLH Status Valid to ALE High (Note 13) - 20 - 20 ns

(28) TSVMCH Status Valid to MCE High (Note 13) - 30 - 30 ns

(29) TCLLH CLK Low to ALE Valid (Note 13) - 20 - 20 ns

(30) TCLMCH CLK Low to MCE High (Note 13) - 25 - 25 ns

(31) TCHLL ALE Inactive Delay (Note 13) 4 18 4 18 ns

21 FN2949.4
February 22, 2008
 80C88

AC Electrical Specifications VCC = 5.0V±10%; TA = 0°C to +70°C (C80C88, C80C88-2)

VCC = 5.0V±10%; TA = -40°C to +85°C (I80C88, I80C88-2)
VCC = 5.0V±10%; TA = -55°C to +125°C (M80C88)
MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER) (Continued)

80C88 80C88-2

SYMBOL PARAMETER TEST CONDITIONS MIN MAX MIN MAX UNITS

(32) TCLMCL MCE Inactive Delay (Note 13) - 15 - 15 ns

(33) TCLDV Data Valid Delay 10 110 10 60 ns

(34) TCLDX2 Data Hold Time 10 - 10 - ns

(35) TCVNV Control Active Delay (Note 13) 5 45 5 45 ns

(36) TCVNX Control Inactive Delay (Note 13) 10 45 10 45 ns

(37) TAZRL Address Float to Read Active 0 - 0 - ns

(38) TCLRL RD Active Delay 10 165 10 100 ns

(39) TCLRH RD Inactive Delay CL = 100pF 10 150 10 80 ns

for all 80C88 outputs in
(40) TRHAV RD Inactive to Next Address Active addition to internal TCLCL - TCLCL - ns
loads. - 45 - 40

(41) TCHDTL Direction Control Active Delay - 50 - 50 ns

(Note 13)

(42) TCHDTH Direction Control Inactive Delay - 30 - 30 ns

(Note 1)

(43) TCLGL GT Active Delay 0 85 0 50 ns

(44) TCLGH GT Inactive Delay 0 85 0 50 ns

(45) TRLRH RD Width 2TCLCL - 2TCLCL - ns
- 75 - 50

(46) TOLOH Output Rise Time From 0.8V to 2.0V - 15 - 15 ns

(47) TOHOL Output Fall Time From 2.0V to 0.8V - 15 - 15 ns

NOTES:
3. Signal at 82C84A or 82C88 shown for reference only.
4. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.
5. Applies only to T2 state (8ns into T3).
6. The 80C88 actively pulls the RQ/GT pin to a logic one on the following clock low time.
7. Status lines return to their inactive (logic one) state after CLK goes low and READY goes high.

22 FN2949.4
February 22, 2008
 80C88

Waveforms
T1 T2 T3 T4
(4)
TCH1CH2
(1) (5)
TCLCL TCL2CL1 TW

CLK
(23)
TCLAV TCLCH
TCHCL (3)
(2)
QS0, QS1

(21) TCHSV (22) TCLSH

S2, S1, S0 (EXCEPT HALT) (SEE NOTE 20)

A15-A8 A15-A8

(23) TCLAV TCLDV (33)

(23)
TCLAX (24) TCLAV

A19/S6-A16/S3 A19-A16 S6-S3

TSVLH
(27) TCHLL (31)

ALE (82C88 OUTPUT) TCLLH

(29)

NOTES 18, 19 TR1VCL (8)

RDY (82C84 INPUT)

TCLR1X (9)
(12) TRYLCL

(11)
READY 80C86 INPUT) TCHRYX
(24) TRYHSH
(20)
TCLAX
(10)
TRYHCH (7)
(25) (6)
TCLAZ TCLDX1
READ CYCLE TCLAV (23) TDVCL

AD7-AD0 AD7-AD0 DATA IN

(37) TAZRL (39) TCLRH TRHAV (40)

RD
(42)
(41) TCHDTL TCHDTH
TRLRH
TCLRL (45)
DT/R (38)

TCLML (18) TCLMH (19)

82C88
OUTPUTS MRDC OR IORC
SEE NOTES 19, 21
(35) TCVNV

DEN

TCVNX (36)

FIGURE 11. BUS TIMING - MAXIMUM MODE (USING 82C88)

NOTES:
8. RDY is sampled near the end of T2, T3, TW to determine if TW machine states are to be inserted.
9. Signals at 82C84A or 82C88 are shown for reference only.
10. Status inactive in state just prior to T4.
11. The issuance of the 82C88 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA, and DEN) lags the active high
82C88 CEN.

23 FN2949.4
February 22, 2008
 80C88

Waveforms (Continued)

T1 T2 T3 TW T4

CLK

TCHSV (21)

S2, S1, S0 (EXCEPT HALT) (SEE NOTE 24)

TCLDV (33) (22) TCLDX2 (34)

WRITE CYCLE TCLAV (23) TCLSH
TCLAX (24)
AD7-AD0 DATA

TCVNV
(35) TCVNX (36)
DEN
TCLMH
(19)
82C88 (18) TCLML
OUTPUTS
AMWC OR AIOWC
SEE NOTES 22, 23
(18)TCLML TCLMH (19)

MWTC OR IOWC

INTA CYCLE
A15-A8 RESERVED FOR
(SEE NOTES 25, 26) CASCADE ADDR
(25) TCLAZ (6) TDVCL TCLDX1 (7)
AD7-AD0 POINTER

TCLMCL (32)
(28) TSVMCH
(41)
MCE/PDEN TCHDTL
(30) TCLMCH (42) TCHDTH
DT/R

82C88 OUTPUTS
SEE NOTES 22, 23, 25 (18) TCLML
INTA

TCVNV (19) TCLMH

(35)
DEN
TCVNX
SOFTWARE (36)
HALT - RD, MRDC, IORC, MWTC, AMWC, IOWC, AIOWC, INTA, S0, S1 = VOH

AD7-AD0
INVALID ADDRESS
A15-A8
TCLAV
(23)
S2, S1, S0

TCHSV TCLSH
(21) (22)

FIGURE 12. BUS TIMING - MAXIMUM MODE SYSTEM (USING 82C88) (Continued)
NOTES:
12. Signals at 82C84A or 82C86 are shown for reference only.
13. The issuance of the 82C88 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA and DEN) lags the active high
82C88 CEN.
14. Status inactive in state just prior to T4.
15. Cascade address is valid between first and second INTA cycles.
16. Two INTA cycles run back-to-back. The 80C88 local ADDR/DATA bus is floating during both INTA cycles. Control for pointer address is shown
for second INTA cycle.

24 FN2949.4
February 22, 2008
 80C88

Waveforms (Continued)

ANY > 0-CLK

CLK CYCLES
CYCLE

CLK

TCLGH (44) TGVCH (14) TCLGH (44)

(1) TCLGL
TCLCL TCHGX (15) (43) PULSE 2
80C88 GT
RQ/GT
PULSE 1 PULSE 3
COPROCESSOR COPROCESSOR
PREVIOUS GRANT RQ TCLAZ (25) RELEASE

AD7-AD0 80C88 COPROCESSOR

TCHSV (21)
TCHSZ (26) (SEE NOTE)
RD, LOCK
A19/S6-A16/S3
S2, S1, S0

FIGURE 13. REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY)

NOTE: The coprocessor may not drive the busses outside the region shown without risking contention.

≥ 1CL 1 OR 2
CYCLE CYCLES

CLK

THVCH (13) THVCH (13)

(SEE NOTE)
HOLD

TCLHAV (36) TCLHAV (36)

HLDA

TCLAZ (19)
A15-A8
80C88 COPROCESSOR 80C88
AD7-AD0
TCHSZ (20) TCHSV (21)
A19/S6-A16/S3

RD, WR, I/O/M, DT/R, DEN, SSO

FIGURE 14. HOLD/HOLD ACKNOWLEDGE TIMING (MINIMUM MODE ONLY)

NOTE: Setup requirements for asynchronous signals only to guarantee recognition at next CLK.

CLK ANY CLK CYCLE

ANY CLK CYCLE

(13) CLK
NMI TINVCH (SEE NOTE) TCLAV TCLAV
(23) (23)
INTR SIGNAL

TEST LOCK

FIGURE 15. ASYNCHRONOUS SIGNAL RECOGNITION FIGURE 16. BUS LOCK SIGNAL TIMING (MAXIMUM MODE
NOTE: Setup requirements for asynchronous signals only to ONLY)
guarantee recognition at next CLK.

25 FN2949.4
February 22, 2008
 80C88

Waveforms (Continued)

≥ 50µS

VCC

CLK

(7) TCLDX1
(6) TDVCL

RESET

≥ 4 CLK CYCLE

FIGURE 17. RESET TIMING

AC Test Circuit AC Testing Input, Output Waveform

OUTPUT FROM TEST INPUT OUTPUT
DEVICE UNDER TEST POINT VIH + 20% VIH
CL (NOTE) VOH
1.5V 1.5V
VOL
VIL - 50% VIL

NOTE: Includes stay and jig capacitance. 17. All input signals (other than CLK) must switch between VILMAX -50%
VIL and VIHMIN +20% VIH. CLK must switch between 0.4V and
VCC -0.4V. Input rise and fall times are driven at 1ns/V.

Burn-In Circuits
MD80C88 (CERDIP)
C
GND

GND 1 GND VCC 40 VCC

RIO RIO
GND 2 A14 A15 39 VCL
RIO RO
VCL 3 A13 A16 38 VCC/2
RIO RO
GND 4 A12 A17 37 VCC/2
RIO RO
GND 5 A11 A18 36 VCC/2
RIO RO
VCL 6 A10 A19 35 VCC/2
RIO RO
GND 7 A9 BHE 34 VCC/2
RIO
GND 8 A8 MX 33 GND
RIO RO
GND 9 AD7 RD 32 VIL
RIO RI
VCL 10 AD6 RQ0 31 VCL
RIO RO
VCL 11 AD5 RQ1 30 VCL
RIO RO
VCL 12 AD4 LOCK 29 VCC/2
RO
OPEN 13 AD3 S2 28 VCC/2
RO
OPEN 14 AD2 S1 27 VCC/2
RO
OPEN 15 AD1 S0 26 VCC/2
RO
OPEN 16 AD0 QS0 25 VCC/2
RO
GND 17 NMI QS2 24 VCC/2
GND 18 INTR TEST 23 GND
RC RI
F0 19 CLK READY 22 VCL
RI
GND 20 GND RESET 21 NODE A
FROM
PROGRAM
CARD

26 FN2949.4
February 22, 2008
 80C88

Burn-In Circuits (Continued)

NOTES: COMPONENTS:
1. VCC = 5.5V ±0.5V, GND = 0V. 1. RI = 10kΩ ±5%, 1/4W
2. Input voltage limits (except clock): 2. RO = 1.2kΩ ±5%, 1/4W
VIL (Maximum) = 0.4V
VIH (Minimum) = 2.6V, VIH (Clock) = VCC - 0.4V) minimum. 3. RIO = 2.7kΩ ±5%, 1/4W
3. VCC/2 is external supply set to 2.7V ±10%. 4. RC = 1kΩ ±5%, 1/4W
4. VCL is generated on program card (VCC - 0.65V). 5. C = 0.01μF (Minimum)
5. Pins 13 - 16 input sequenced instructions from internal hold
devices, (DIP Only).
6. F0 = 100kHz ±10%.
7. Node A = a 40μs pulse every 2.56ms.

27 FN2949.4
February 22, 2008
 80C88
Die Characteristics
METALLIZATION:
Type: Silicon - Aluminum
Thickness: 11KÅ ±2kÅ
GLASSIVATION:
Type: SiO2
Thickness: 8kÅ ±1kÅ
WORST CASE CURRENT DENSITY:
1.5 x 105 A/cm2

Metallization Mask Layout

80C88

A11 A12 A13 A14 GND VCC A15 A16/S3 A17/S4 A18/S5

A19/S6
A10

A9
SSO
MN/MX

A8
RD
AD7

HOLD
AD6

AD5

HLDA

AD4

AD3
WR

AD2 IO/M

AD1

DT/R

AD0

NMI INTR CLK GND RESET READY TEST INTA ALE DEN

28 FN2949.4
February 22, 2008
 80C88

Instruction Set Summary

INSTRUCTION CODE
MNEMONIC AND
DESCRIPTION 76543210 76543210 76543210 76543210

DATA TRANSFER
MOV = MOVE:
Register/Memory to/from 100010dw mod reg r/m
Register
Immediate to Regis- 1100011w mod 0 0 0 r/m data data if w 1
ter/Memory
Immediate to Register 1 0 1 1 w reg data data if w 1
Memory to Accumulator 1010000w addr-low addr-high
Accumulator to Memory 1010001w addr-low addr-high
Register/Memory to Seg- 10001110 mod 0 reg r/m
ment Register ††
Segment Register to Reg- 10001100 mod 0 reg r/m
ister/Memory
PUSH = Push:
Register/Memory 11111111 mod 1 1 0 r/m
Register 0 1 0 1 0 reg
Segment Register 0 0 0 reg 1 1 0
POP = Pop:
Register/Memory 10001111 mod 0 0 0 r/m
Register 0 1 0 1 1 reg
Segment Register 0 0 0 reg 1 1 1
XCHG = Exchange:
Register/Memory with 1000011w mod reg r/m
Register
Register with Accumula- 1 0 0 1 0 reg
tor
IN = Input from:
Fixed Port 1110010w port
Variable Port 1110110w
OUT = Output to:
Fixed Port 1110011w port
Variable Port 1110111w
XLAT = Translate Byte to 11010111
AL
LEA = Load EA to 10001101 mod reg r/m
Register2
LDS = Load Pointer to DS 11000101 mod reg r/m
LES = Load Pointer to ES 11000100 mod reg r/m
LAHF = Load AH with 10011111
Flags
SAHF = Store AH into 10011110
Flags
PUSHF = Push Flags 10011100
POPF = Pop Flags 10011101

29 FN2949.4
February 22, 2008
 80C88

Instruction Set Summary (Continued)

INSTRUCTION CODE
MNEMONIC AND
DESCRIPTION 76543210 76543210 76543210 76543210

ARITHMETIC
ADD = Add:
Register/Memory with 000000dw mod reg r/m
Register to Either
Immediate to Regis- 100000sw mod 0 0 0 r/m data data if s:w = 01
ter/Memory
Immediate to Accumula- 0000010w data data if w = 1
tor
ADC = Add with Carry:
Register/Memory with 000100dw mod reg r/m
Register to Either
Immediate to Regis- 100000sw mod 0 1 0 r/m data data if s:w = 01
ter/Memory
Immediate to Accumula- 0001010w data data if w = 1
tor
INC = Increment:
Register/Memory 1111111w mod 0 0 0 r/m
Register 0 1 0 0 0 reg
AAA = ASCll Adjust for 00110111
Add
DAA = Decimal Adjust for 00100111
Add
SUB = Subtract:
Register/Memory and 001010dw mod reg r/m
Register to Either
Immediate from Regis- 100000sw mod 1 0 1 r/m data data if s:w = 01
ter/Memory
Immediate from Accumu- 0010110w data data if w = 1
lator
SBB = Subtract with
Borrow
Register/Memory and 000110dw mod reg r/m
Register to Either
Immediate from Regis- 100000sw mod 0 1 1 r/m data data if s:w = 01
ter/Memory
Immediate from Accumu- 0001110w data data if w = 1
lator
DEC = Decrement:
Register/Memory 1111111w mod 0 0 1 r/m
Register 0 1 0 0 1 reg
NEG = Change Sign 1111011w mod 0 1 1 r/m
CMP = Compare:
Register/Memory and 001110dw mod reg r/m
Register
Immediate with Regis- 100000sw mod 1 1 1 r/m data data if s:w = 01
ter/Memory

30 FN2949.4
February 22, 2008
 80C88

Instruction Set Summary (Continued)

INSTRUCTION CODE
MNEMONIC AND
DESCRIPTION 76543210 76543210 76543210 76543210
Immediate with Accumu- 0011110w data data if w = 1
lator
AAS = ASCll Adjust for 00111111
Subtract
DAS = Decimal Adjust for 00101111
Subtract
MUL = Multiply (Un- 1111011w mod 1 0 0 r/m
signed)
IMUL = Integer Multiply 1111011w mod 1 0 1 r/m
(Signed)
AAM = ASCll Adjust for 11010100 00001010
Multiply
DlV = Divide (Unsigned) 1111011w mod 1 1 0 r/m
IDlV = Integer Divide 1111011w mod 1 1 1 r/m
(Signed)
AAD = ASClI Adjust for 11010101 00001010
Divide
CBW = Convert Byte to 10011000
Word
CWD = Convert Word to 10011001
Double Word

LOGIC
NOT = Invert 1111011w mod 0 1 0 r/m
SHL/SAL = Shift Logi- 110100vw mod 1 0 0 r/m
cal/Arithmetic Left
SHR = Shift Logical Right 110100vw mod 1 0 1 r/m
SAR = Shift Arithmetic 110100vw mod 1 1 1 r/m
Right
ROL = Rotate Left 110100vw mod 0 0 0 r/m
ROR = Rotate Right 110100vw mod 0 0 1 r/m
RCL = Rotate Through 110100vw mod 0 1 0 r/m
Carry Flag Left
RCR = Rotate Through 110100vw mod 0 1 1 r/m
Carry Right
AND = And:
Reg./Memory and Regis- 0010000dw mod reg r/m
ter to Either
Immediate to Regis- 1000000w mod 1 0 0 r/m data data if w = 1
ter/Memory
Immediate to Accumula- 0010010w data data if w = 1
tor
TEST = And Function to
Flags, No Result:
Register/Memory and 1000010w mod reg r/m
Register
Immediate Data and Reg- 1111011w mod 0 0 0 r/m data data if w = 1
ister/Memory

31 FN2949.4
February 22, 2008
 80C88

Instruction Set Summary (Continued)

INSTRUCTION CODE
MNEMONIC AND
DESCRIPTION 76543210 76543210 76543210 76543210
Immediate Data and Ac- 1010100w data data if w = 1
cumulator
OR = Or:
Register/Memory and 000010dw mod reg r/m
Register to Either
Immediate to Regis- 1000000w mod 1 0 1 r/m data data if w = 1
ter/Memory
Immediate to Accumula- 0000110w data data if w = 1
tor
XOR = Exclusive or:
Register/Memory and 001100dw mod reg r/m
Register to Either
Immediate to Regis- 1000000w mod 1 1 0 r/m data data if w = 1
ter/Memory
Immediate to Accumula- 0011010w data data if w = 1
tor
STRING MANIPULA-
TION
REP = Repeat 1111001z
MOVS = Move Byte/Word 1010010w
CMPS = Compare 1010011w
Byte/Word
SCAS = Scan Byte/Word 1010111w
LODS = Load Byte/Word 1010110w
to AL/AX
STOS = Stor Byte/Word 1010101w
from AL/A
CONTROL TRANSFER
CALL = Call:
Direct Within Segment 11101000 disp-low disp-high
Indirect Within Segment 11111111 mod 0 1 0 r/m
Direct Intersegment 10011010 offset-low offset-high
seg-low seg-high
Indirect Intersegment 11111111 mod 0 1 1 r/m

32 FN2949.4
February 22, 2008
 80C88

Instruction Set Summary (Continued)

INSTRUCTION CODE
MNEMONIC AND
DESCRIPTION 76543210 76543210 76543210 76543210

JMP = Unconditional
Jump:
Direct Within Segment 11101001 disp-low disp-high
Direct Within Segment- 11101011 disp
Short
Indirect Within Segment 11111111 mod 1 0 0 r/m
Direct Intersegment 11101010 offset-low offset-high
seg-low seg-high
Indirect Intersegment 11111111 mod 1 0 1 r/m
RET = Return from
CALL:
Within Segment 11000011
Within Seg Adding lmmed 11000010 data-low data-high
to SP
Intersegment 11001011

33 FN2949.4
February 22, 2008
 80C88

Instruction Set Summary (Continued)

INSTRUCTION CODE
MNEMONIC AND
DESCRIPTION 76543210 76543210 76543210 76543210
Intersegment Adding Im- 11001010 data-low data-high
mediate to SP
JE/JZ = Jump on 01110100 disp
Equal/Zero
JL/JNGE = Jump on 01111100 disp
Less/Not Greater or
Equal
JLE/JNG = Jump on Less 01111110 disp
or Equal/ Not Greater
JB/JNAE = Jump on Be- 01110010 disp
low/Not Above or Equal
JBE/JNA = Jump on Be- 01110110 disp
low or Equal/Not Above
JP/JPE = Jump on Pari- 01111010 disp
ty/Parity Even
JO = Jump on Overflow 01110000 disp
JS = Jump on Sign 01111000 disp
JNE/JNZ = Jump on Not 01110101 disp
Equal/Not Zero
JNL/JGE = Jump on Not 01111101 disp
Less/Greater or Equal
JNLE/JG = Jump on Not 01111111 disp
Less or Equal/Greater
JNB/JAE = Jump on Not 01110011 disp
Below/Above or Equal
JNBE/JA = Jump on Not 01110111 disp
Below or Equal/Above
JNP/JPO = Jump on Not 01111011 disp
Par/Par Odd
JNO = Jump on Not Over- 01110001 disp
flow
JNS = Jump on Not Sign 01111001 disp
LOOP = Loop CX Times 11100010 disp
LOOPZ/LOOPE = Loop 11100001 disp
While Zero/Equal
LOOPNZ/LOOPNE = 11100000 disp
Loop While Not Ze-
ro/Equal
JCXZ = Jump on CX Zero 11100011 disp
INT = Interrupt
Type Specified 11001101 type
Type 3 11001100
INTO = Interrupt on Over- 11001110
flow
IRET = Interrupt Return 11001111

PROCESSOR CONTROL

34 FN2949.4
February 22, 2008
 80C88

Instruction Set Summary (Continued)

INSTRUCTION CODE
MNEMONIC AND
DESCRIPTION 76543210 76543210 76543210 76543210
CLC = Clear Carry 11111000
CMC = Complement Car- 11110101
ry
STC = Set Carry 11111001
CLD = Clear Direction 11111100
STD = Set Direction 11111101
CLl = Clear Interrupt 11111010
ST = Set Interrupt 11111011
HLT = Halt 11110100
WAIT = Wait 10011011
ESC = Escape (to Exter- 11011xxx mod x x x r/m
nal Device)
LOCK = Bus Lock Prefix 11110000

35 FN2949.4
February 22, 2008
 80C88

Instruction Set Summary (Continued)

INSTRUCTION CODE
MNEMONIC AND
DESCRIPTION 76543210 76543210 76543210 76543210
NOTES: if s:w = 01 then 16-bits of immediate data form the operand.
AL = 8-bit accumulator if s:w = 11 then an immediate data byte is sign extended
AX = 16-bit accumulator to form the 16-bit operand.
CX = Count register if v = 0 then “count” = 1; if v = 1 then “count” in (CL)
DS= Data segment x = don't care
ES = Extra segment z is used for string primitives for comparison with ZF FLAG.
Above/below refers to un-
signed value. SEGMENT OVERRIDE PREFIX
Greater = more positive;
Less = less positive (more 001 reg 11 0
negative) signed values REG is assigned according to the following table:
if d = 1 then “to” reg; if d =
0 then “from” reg 16-BIT (w = 1) 8-BIT (w = 0) SEGMENT
if w = 1 then word instruc- 000 AX 000 AL 00 ES
tion; if w = 0 then byte
instruction 001 CX 001 CL 01 CS
if mod = 11 then r/m is 010 DX 010 DL 10 SS
treated as a REG field
if mod = 00 then DISP = 011 BX 011 BL 11 DS
0†, disp-low and disp-high 100 SP 100 AH
are absent
if mod = 01 then DISP = 101 BP 101 CH
disp-low sign-extended 110 SI 110 DH
16-bits, disp-high is ab-
sent 111 DI 111 BH
if mod = 10 then DISP = Instructions which reference the flag register file as a 16-bit object use the symbol
disp-high:disp-low FLAGS to represent the file:
if r/m = 000 then EA =
(BX) + (SI) + DISP FLAGS =
if r/m = 001 then EA = X:X:X:X:(OF):(DF):(IF):(TF):(SF):(ZF):X:(AF):X:(PF):X:(CF)
(BX) + (DI) + DISP
if r/m = 010 then EA = Mnemonics © Intel, 1978
(BP) + (SI) + DISP
if r/m = 011 then EA =
(BP) + (DI) + DISP
if r/m = 100 then EA = (SI)
+ DISP
if r/m = 101 then EA = (DI)
+ DISP
if r/m = 110 then EA =
(BP) + DISP †
if r/m = 111 then EA =
(BX) + DISP
DISP follows 2nd byte of
instruction (before data
if required)
† except if mod = 00 and
r/m = 110 then
EA = disp-high: disp-
low.
†† MOV CS, REG/MEM-
ORY not allowed.

36 FN2949.4
February 22, 2008
 80C88

Dual-In-Line Plastic Packages (PDIP)

E40.6 (JEDEC MS-011-AC ISSUE B)
N 40 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX INCHES MILLIMETERS
AREA 1 2 3 N/2
SYMBOL MIN MAX MIN MAX NOTES
-B-
A - 0.250 - 6.35 4
-A-
D E A1 0.015 - 0.39 - 4
BASE A2 0.125 0.195 3.18 4.95 -
PLANE A2
-C- A B 0.014 0.022 0.356 0.558 -
SEATING
PLANE L C
L
B1 0.030 0.070 0.77 1.77 8
D1 A1 eA C 0.008 0.015 0.204 0.381 -
D1
B1 e D 1.980 2.095 50.3 53.2 5
eC C
B
eB D1 0.005 - 0.13 - 5
0.010 (0.25) M C A B S
E 0.600 0.625 15.24 15.87 6
NOTES: E1 0.485 0.580 12.32 14.73 5
1. Controlling Dimensions: INCH. In case of conflict between English e 0.100 BSC 2.54 BSC -
and Metric dimensions, the inch dimensions control.
eA 0.600 BSC 15.24 BSC 6
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
eB - 0.700 - 17.78 7
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication No. 95. L 0.115 0.200 2.93 5.08 4
4. Dimensions A, A1 and L are measured with the package seated in N 40 40 9
JEDEC seating plane gauge GS-3.
Rev. 0 12/93
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be per-
pendicular to datum -C- .
7. eB and eC are measured at the lead tips with the leads uncon-
strained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dam-
bar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

37 FN2949.4
February 22, 2008
 80C88

Ceramic Dual-In-Line Frit Seal Packages (CERDIP)

c1 LEAD FINISH F40.6 MIL-STD-1835 GDIP1-T40 (D-5, CONFIGURATION A)
-A- -D- 40 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE

BASE INCHES MILLIMETERS

(c)
METAL
E SYMBOL MIN MAX MIN MAX NOTES
b1 A - 0.225 - 5.72 -
M M
-B- (b)
b 0.014 0.026 0.36 0.66 2

SECTION A-A
b1 0.014 0.023 0.36 0.58 3
bbb S C A-B S D S
b2 0.045 0.065 1.14 1.65 -
D
BASE b3 0.023 0.045 0.58 1.14 4
PLANE Q
-C- A c 0.008 0.018 0.20 0.46 2
SEATING
PLANE L c1 0.008 0.015 0.20 0.38 3
α
S1 D - 2.096 - 53.24 5
A A eA
b2 E 0.510 0.620 12.95 15.75 5
b e eA/2 c e 0.100 BSC 2.54 BSC -
ccc M C A-B S D S aaa M C A - B S D S eA 0.600 BSC 15.24 BSC -
eA/2 0.300 BSC 7.62 BSC -
NOTES:
1. Index area: A notch or a pin one identification mark shall be locat- L 0.125 0.200 3.18 5.08 -
ed adjacent to pin one and shall be located within the shaded Q 0.015 0.070 0.38 1.78 6
area shown. The manufacturer’s identification shall not be used
S1 0.005 - 0.13 - 7
as a pin one identification mark.
2. The maximum limits of lead dimensions b and c or M shall be α 90o 105o 90o 105o -
measured at the centroid of the finished lead surfaces, when aaa - 0.015 - 0.38 -
solder dip or tin plate lead finish is applied.
bbb - 0.030 - 0.76 -
3. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness. ccc - 0.010 - 0.25 -
4. Corner leads (1, N, N/2, and N/2+1) may be configured with a M - 0.0015 - 0.038 2, 3
partial lead paddle. For this configuration dimension b3 replaces N 40 40 8
dimension b2.
Rev. 0 4/94
5. This dimension allows for off-center lid, meniscus, and glass
overrun.
6. Dimension Q shall be measured from the seating plane to the
base plane.
7. Measure dimension S1 at all four corners.
8. N is the maximum number of terminal positions.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.

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38 FN2949.4
February 22, 2008