Design and Implementation of Voltage Control

Oscillator (VCO) using 180nm technology

Halesh M.R.1, [Link] 2, Rohini H3,

1 Electronics & Communication, [Link] College of Engg., & Tech,

Hubli,Karnataka India,
2 Electronics & Communication, K.L.E.C.E.T, Belgaum,Karnataka,India,
3 Electronics & Communication, [Link] College of Engg., & Tech,
Hubli,Karnataka India,
{Halesh M.R, Rohini H, haleshmr,rohini_sh}@[Link]
{[Link], kruparasane}@[Link]

Abstract. Voltage Control Oscillator (VCO) is an integral part of many electronic

applications like PLL, clock generation in microprocessors & carrier synthesis in cellular
telephones etc. Such applications require different topologies which gives robust high
performance. Consequently, VCO design in CMOS technology continues to pose interesting
challenges. This paper presents the design of Voltage Control Ring Oscillator with the
oscillation frequency up to 1 GHz. The circuit is implemented using Cadence tool in 0.18µm
CMOS technology (UMC180) with 1.8V supply. The designed VCO is generating a frequency
of 1.06GHz over a temperature range from -40oC to 125oC, & the linearity is achieved over a
range of frequency from 970MHz to 1.03GHz..
Keywords: VCO, PLL, DRC, LVS.

1 Introduction

The Phase Lock Loop (PLL) is a critical component in many high speed systems as it
provides the timing basis for the functions such as clock control, data recovery and
synchronization. The VCO is perhaps the integral element of the PLL. A CMOS VCO
can be built using ring structure, relaxation circuit or an LC resonant circuit. The LC
design has the best phase noise and frequency performance, but their tuning range is
relatively small. However adding high quality inductors to a CMOS process flow
increases the cost and complexity of the chip.
Ring oscillator, on the other hand can be built in any standard CMOS process and
may require less die area than LC design. This paper presents a design of ring
oscillator with a conventional architecture, which requires connecting an odd number
of inverters and feedback from the output of last stage to the input of the first stage.
The oscillation frequency is determined by the number of stages and the delay in each
stage which is very small for inverters. If the delay is voltage controllable, then a
VCO with variable-frequency output is obtained. The proposed ring oscillator is used
for the application of PLL as a communication circuit.
2 Design Implementation

A conventional VCO as shown in figure 1, is realized by N stages of inverters (N is

an odd number), with a control mechanism of the current passing through these
inverters. Usually inverter current mirror circuit is used to generate a current in each
delay stage.

Fig. 1. Conventional VCO

The frequency of oscillation can be found as

1
fosc = (1)
2 Nτ
Where τ is the delay of each stage.
The gain of the amplifier (inverter) from small signal model in figure 2 is given as
A = gm rds (2)

Fig. 2. SSM of an Inverter

Yalcin Alper Eken, and John P. Uyemura [1], compared the Differential architecture
with the LC resonator circuit (relaxation circuit) and the LC circuits are usually
implemented for a high frequency. In this paper an attempt has made to achieve high
frequency using CMOS circuit. Some of the characteristics like area and power is
improved in CMOS circuit compared to LC oscillator.
3 Feedback and Stability
Figure 3 represents the block schematic of a feedback amplifier system, with transfer
gain A and feedback network β [5], and a mixing circuit connected to form a closed
loop. The amplifier provides an output signal VO as consequence of external signal Vin
applied directly to amplifier input terminal.

Fig. 3. Feedback amplifier system Fig. 4. The locus of |1+Aβ|=1 is a circle

Of unit radius, with center -1+j0

The overall gain of the system is found to be

Af = A / (1+Aβ) (3)
If |1+Aβ| = 0(i.e., -Aβ = 1 ∟ 0.) this is called Barkhausen’s criterion for sustained
oscillation. An improved version of the Barkhausen criterion was given by Nyquist
for understanding the stability of amplifier using Loop gain[5]. If –Aβ›1 ∟ 0, the
amplifier becomes unstable, and the output sees a growing oscillation. The criteria for
positive or negative feedback may also be represented in the complex plane. From
Figure 4, we see that |1+Aβ|=1, represents a circle of unit radius, centered at (-1, 0).
Thus that portion of Aβ curve that falls outside the unit circle indicates negative
feedback, and the polar plot within the unit circle indicates positive feedback. For
oscillation, the polar plot should cross the critical point (-1, 0), and the frequency of
oscillation is the point where the curve crosses the negative real axis.
4 The Current Starved VCO
The current starved VCO is shown in Figure 5. Its operation is similar to the ring
oscillator [7]. MOSFETs M2 and M3 operate as an inverter, while MOSFETs Ml and
M5 operate as current sources. The MOSFETs M5 and M6 drain currents are the same
and are set by the input control voltage. The currents in M 5 and M6 are mirrored in
each inverter/current source stage. Consider the simplified schematic of one stage of
the VCO shown in Figure6, to derive the design equations. The total capacitance on
the drains of M2 and M3 is given by

Ctot = Cout + Cin (4)

=Cox’ (WpLp+WnLn) + 1.5Cox’ (WpLp+WnLn)

 =2.5 Cox’ (WpLp+WnLn).

Fig. 5. Current starved VCO

Fig. 6. Simplified view of single stage of current-starved VCO

The time takes to charge Ctot from zero to VSP with constant current ID5 is given by

t1 = Ctot (VSP/ID4) (5)

The time taken to discharge from VDD to VSP is given by

t2 = Ctot (VDD-VSP)/ID1 (6)

If we set ID5=ID1=ID (which is IDcentre when VinVCO =VDD/2) then the sum of t1 and t2 is
simply

t1 + t2 = (ctot * VDD) / ID (7)

The oscillation frequency of the current starved VCO for N (an odd number) of stages
is
fosc = 1 / N(t1 - t2)

fosc = ID / (N * Ctot * VDD) (8)

This is equal to
fosc = fcentre at VinVCO = VDD/2 and ID = Icenter (9)

5 Physical Design:
The process of translating the net-list into Silicon wafer requires an accurate map of
the circuit with details of device size, their layout and interconnections. The final
layout of VCO is shown in Fig 6, consuming 697 (μm) 2 of silicon areas.

Fig. 6. Implementation of VCO with its validation result

6 Results and Discussions

Transient Analysis:

The transient analysis of the circuit is depicted in figure 7a showing generated

frequency of 1.06 GHz in a typical corner. The delay between each stage is measured
to be 326ps, 306ps, and 304ps between V1 to V2, V2 to V3 and V3 back to V1
respectively, from the circuit shown in the Figure 5. So that the total delay is obtained
to be 936ps and so we get a frequency of 1.068GHz. This circuit was simulated for all
the process corners with 10% variation in power supply and the temperature variation
from -40o C to 125o C.
 Table 1. Comparison with different Architectures.
Architecture- Archi Architect Our paper
1(Ref-1) tecture-2 ure-3 (Ref-2)
(Ref-9)
Technology 180-nm CMOS 0.35µ 0.8µm High UMC180nm
Technology m - Voltage Technology with
2P3M- CMOS/DMOS 1.8V
COS Tech with 5V
Technolog
y
Frequency 3 – Stages 3 – 3 – Stages 3 – Stages
Range 5.16GHz - 5.93 Stages 13 Hz - 407 970 MHz - 1.03
GHz 1.25 GHz MHz GHz
-99.5 dBc/Hz at
Phase Noise 1-MHz offset from -
Measured a 5.79-GHz center 20dBc/Hz
frequency. at
100kHz. --- ----

Table 2. The pre-layout & post-layout simulation results.

Corners Supply Frequency Frequency range
voltage in range in GHz in GHz
Volts (prelayout) (Postlayout)
Typical 1.8 1.063 1.047
1.68 0.971 0.958
1.92 1.151 1.132
Slow 1.8 1.024 0.935
1.68 0.857 0.851
1.92 0.945 1.015
Fast 1.8 1.180 1.154

1.68 1.083 1.061

1.92 1.271 1.241
Slow nMOS & Fast 1.8 1.144 1.040
pMOS
(Snfp) 1.68 0.968 0.953
1.92 1.058 1.123
Fast nMOS & Slow 1.8 1.063 1.050
pMOS
(Fnsp) 1.68 0.970 0.959
1.92 1.152 1.136
 Fig. 7. Transient Analysis - variation of Fig, 7b. Linearity variation of frequency
frequency with control voltage with control voltage

6 Conclusion:
A voltage controlled oscillator is designed and implemented for the frequency of
1GHz. The parasitic are extracted and the back annotated circuit is simulated for all
the process corners, for a temperature ranging from -40oC to 125oC. The transient
analysis shows the obtained frequency is 1.06GHz in a typical corner and 860MHz in
a worst corner with 10% supply variation. The result in figure 7b shows linear
variation of output frequency with respect to control voltage over a frequency range
of 970MHz to 1.03GHz. The implemented architecture works for the frequency of
1.06GHz. Further high frequency can be achieved by varying the length of the active
device & current flowing in the delay stage.

References

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