8086 MICROPROCESSOR

Comprehensive Exam-Ready Study Notes

Topics: Features • Pin Diagram • Architecture • Addressing Modes
TOPIC OUTLINE
This document covers all major topics from the three lecture PDFs on Intel 8086 Microprocessor:

1. Features of the 8086 Microprocessor

2. Pin Diagram and Pin Signals (Common Signals)
3. Minimum Mode Signals
4. Maximum Mode Signals
5. Internal Architecture — BIU and EU
6. Segment Registers and Physical Address Calculation
7. Internal Registers of the 8086 (All Registers and Special Functions)
8. Flag Register (Condition Flags + Control Flags)
9. Segment : Offset Addressing with Worked Examples
10. All 8 Addressing Modes (with examples and EA formulas)
SECTION 1: FEATURES OF THE 8086 MICROPROCESSOR
The 8086 is Intel's landmark 16-bit microprocessor. Understanding its features is foundational for
everything else in this course.

1.1 Basic Characteristics

• Data Width: 16-bit processor — it processes 16 bits (2 bytes) of data at a time.
• Technology: N-channel HMOS (High-speed Metal Oxide Semiconductor). An improved CMOS
version, the 80C86, is also available.
• Power: The 8086 draws 360 mA at 5V. The CMOS version (80C86) draws only 10 mA — much
more power efficient.
• Introduction Year: Introduced by Intel in 1978.
• Transistor Count: Contains the electronic circuitry of approximately 29,000 transistors on a
single semiconductor chip.

1.2 Physical Packaging

• Package Type: DIP — Dual In-Line Package. This is the standard rectangular chip package
with pins on two sides.
• Pin Count: 40 pins total on the IC package.

1.3 Bus Structure

• Address Bus: 20 address lines (A0–A19). This means the 8086 can directly address 2²⁰ = 1
Megabyte (1,048,576 bytes) of memory.
• Data Bus: 16 data lines (D0–D15). Data is transferred as a 16-bit word.
• High-Low Byte Split: The 16-bit data word is split into a low-order byte (D0–D7) and a high-
order byte (D8–D15).

1.4 Multiplexed Bus Lines

To save chip pins, the 8086 shares (multiplexes) its address and data lines:
• AD0–AD15 (pins 2–16 & 39): The lower 16 address lines are time-multiplexed with 16 data
lines. During the first part of a bus cycle (T1), these carry address bits A0–A15. Later in the
cycle (T2–T4), they carry data bits D0–D15.
• A16/S3 to A19/S6 (pins 35–38): The upper 4 address lines (A16–A19) are time-multiplexed
with status signals (S3–S6).

1.5 Clock Frequencies

• Standard 8086: 5 MHz
• 8086-2: 8 MHz
• 8086-1: 10 MHz
1.6 Operating Temperature
• Standard range: 32°F to 180°F (commercial grade)
• Extended range: –40°F to +225°F (industrial grade)

⭐ Exam Tip: Features are a very common short-answer question. Remember: 16-bit, 29000
transistors, 40-pin DIP, 20 address lines → 1MB memory, clock = 5/8/10 MHz.
SECTION 2: PIN DIAGRAM AND PIN SIGNALS
The 8086 is housed in a 40-pin DIP package. All 40 pins are organized around two sides of the chip.
The pins serve different purposes depending on whether the chip is in Minimum Mode or Maximum
Mode.

2.1 Understanding the Pin Diagram Layout

The 40 pins are arranged as follows (left side = pins 1–20, right side = pins 21–40):

Pin
Pin Name Direction Function (Brief)
#

1 GND — Ground reference

2 AD14 Bidirectiona Address/Data bus bit 14

l

3 AD13 Bidirectiona Address/Data bus bit 13

l

4 AD12 Bidirectiona Address/Data bus bit 12

l

5 AD11 Bidirectiona Address/Data bus bit 11

l

6 AD10 Bidirectiona Address/Data bus bit 10

l

7 AD9 Bidirectiona Address/Data bus bit 9

l

8 AD8 Bidirectiona Address/Data bus bit 8

l

9 AD7 Bidirectiona Address/Data bus bit 7

l

10 AD6 Bidirectiona Address/Data bus bit 6

l

11 AD5 Bidirectiona Address/Data bus bit 5

l

12 AD4 Bidirectiona Address/Data bus bit 4

l

13 AD3 Bidirectiona Address/Data bus bit 3

l

14 AD2 Bidirectiona Address/Data bus bit 2

l

15 AD1 Bidirectiona Address/Data bus bit 1

l

16 AD0 Bidirectiona Address/Data bus bit 0

Pin
Pin Name Direction Function (Brief)
#

17 NMI Input Non-Maskable Interrupt

18 INTR Input Maskable Interrupt Request

19 CLK Input Clock input

20 GND — Ground reference

21 RESET Input Reset processor

22 READY Input Slow device handshake

23 TEST Input WAIT instruction control

24 INTA / QS1 Output Interrupt Ack (min) / Queue Status (max)

25 ALE / QS0 Output Address Latch Enable (min) / Queue Status (max)

26 DEN / S0 Output Data Enable (min) / Status (max)

27 DT/R / S1 Output Data Transmit/Receive (min) / Status (max)

28 M/IO / S2 Output Memory or I/O select (min) / Status (max)

29 WR / LOCK Output Write signal (min) / LOCK prefix (max)

30 HLDA / Bidirec. Hold Acknowledge (min) / Bus Grant (max)

RQ/GT1

31 HOLD / Bidirec. Hold request (min) / Bus Request (max)

RQ/GT0

32 RD Output Read signal (common)

33 MN/MX Input Mode select: Min or Max mode

34 BHE/S7 Output Bus High Enable / Status 7

35 A19/S6 Output High address bit 19 / Status 6

36 A18/S5 Output High address bit 18 / Interrupt status

37 A17/S4 Output High address bit 17 / Segment status S4

38 A16/S3 Output High address bit 16 / Segment status S3

39 AD15 Bidirectiona Address/Data bus bit 15

l

40 VCC — Power supply (+5V)

📝 Note: Pin 35–38 are correctly labeled A19/S6 through A16/S3 (not AD16–AD19 as sometimes
mistakenly written).
2.2 Common Signals (Present in Both Modes)
These signals exist in both Minimum and Maximum mode. They are always available regardless of the
MN/MX pin setting.

AD0–AD15 | Address/Data Bus (Bidirectional)

These 16 pins are the heart of the 8086's external communication. They are multiplexed — meaning
they serve two different roles at two different times within a single bus cycle:
•During T1 (Address Phase): These pins carry the lower 16 bits of the 20-bit memory address
(A0–A15). When used in this role, they are denoted as A0–A15.
• During T2–T4 (Data Phase): These same pins carry the actual data being read from or written
to memory/I/O. When used in this role, they are denoted as D0–D15.
This multiplexing technique allows 16 pins to serve two purposes, reducing the total pin count of the
chip.

A16/S3, A17/S4, A18/S5, A19/S6 (Output)

The upper 4 address bits are also multiplexed with status signals:
• A16 and A17: Multiplexed with segment identifier signals S3 and S4 respectively. Together, S3
and S4 tell you which segment is currently being accessed.
• A18: Multiplexed with interrupt enable status flag S5. It reflects the current state of the Interrupt
Flag (IF) from the processor's flag register.
• A19: Multiplexed with status signal S6, which is always 0 during memory access.

The S3 and S4 status bits encode which memory segment is currently active:
S3 S4 Segment Being Accessed

0 0 Extra Segment (ES)

0 1 Stack Segment (SS)

1 0 Code Segment (CS)

1 1 Data Segment (DS)

BHE (Active Low) / S7 — Pin 34 (Output)

BHE stands for Bus High Enable. It is an important control signal for byte-wide memory access:
• Purpose: When BHE is LOW, it enables data onto the upper half of the data bus (D8–D15). 8-
bit devices connected to the upper data bus use this signal to know they should respond.
• Multiplexed: BHE is active only during T1. During T3 and T4, this pin carries status signal S7.

The combination of BHE and A0 determines what type of data transfer occurs:
BHE (Low) A0 Transfer Type

0 0 Whole 16-bit word transferred

0 1 Upper byte only (from/to odd address)

 BHE (Low) A0 Transfer Type

1 0 Lower byte only (from/to even address)

1 1 No transfer

MN/MX — Pin 33 (Input)

• This single pin determines the operating mode of the entire chip.
• When HIGH (tied to VCC): Minimum Mode. The 8086 works alone, generating all bus control
signals by itself. No co-processor support.
• When LOW (grounded): Maximum Mode. The 8086 works with co-processors or in a multi-
processor system. A separate bus controller chip (Intel 8288) is required to generate control
signals.

RD (Read) — Pin 32 (Output, Active Low)

• This output signal is driven LOW by the 8086 whenever it wants to read data from memory or an
I/O device.
• It is an active-low output signal (a bar over RD means active when low).

TEST — Pin 23 (Input)

• This pin is examined by the WAIT instruction in the instruction set.
• If TEST is LOW: Execution continues normally.
• If TEST is HIGH: The processor enters an Idle state and keeps checking until TEST goes LOW.
• Purpose: Used to synchronize an external co-processor or peripheral activity with the
processor's internal operation. The signal is synchronized internally on the leading edge of CLK.

RESET — Pin 21 (Input, Active High)

• Causes the processor to immediately stop whatever it is doing and restart from a known state.
• The RESET signal must remain HIGH for at least 4 clock cycles to be effective.
• On reset, the CS register is set to FFFFH and IP is set to 0000H, so execution begins from
physical address FFFF0H (top of memory).

CLK — Pin 19 (Input)

• The clock input is the heartbeat of the processor.
• All internal operations are synchronized to this signal.
• Available frequencies: 5 MHz, 8 MHz, or 10 MHz depending on the chip version.

INTR (Interrupt Request) — Pin 18 (Input, Active High)

• A maskable interrupt input. 'Maskable' means it can be disabled by the programmer using the
CLI instruction.
• The 8086 checks this pin at the end of every instruction.
• If INTR is HIGH and the Interrupt Flag (IF) is enabled, the processor enters an interrupt
acknowledge cycle.
• This signal is internally synchronized (it does not need external synchronization circuitry).
NMI (Non-Maskable Interrupt) — Pin 17 (Input)
• A higher-priority interrupt that cannot be disabled by software.
• Triggered on a rising edge (low-to-high transition), not a level.
• Used for critical events like power failure detection.

READY — Pin 22 (Input, Active High)

• Purpose: This is an acknowledgement signal from slow memory or I/O devices. It tells the
processor that the peripheral is ready to complete the data transfer.
• If READY is LOW: The processor inserts wait states (extra T-states) until the device asserts
READY HIGH.
• The READY signal from the device is synchronized to the 8086 clock using an external 8284A
Clock Generator chip.

⭐ Exam Tip: Know the difference between INTR and NMI: INTR is maskable (can be disabled) and
level-triggered. NMI is non-maskable (always responds) and edge-triggered.
2.3 Minimum Mode Signals (Pins 24–31, when MN/MX = HIGH)
In Minimum Mode, the MN/MX pin is tied to VCC (logic HIGH). In this mode, the 8086 itself generates
all bus control signals. This is used for simple, single-processor systems.

DT/R — Data Transmit/Receive (Pin 27, Output)

• Controls the direction of data flow through external data bus transceivers (bidirectional buffers
like the 8286/8287).
• HIGH: Data is being transmitted OUT (written) from the processor to memory/I/O.
• LOW: Data is being received INTO the processor (read from memory/I/O).

DEN (Active Low) — Data Enable (Pin 26, Output)

• Acts as an output enable for the data bus transceivers.
• When DEN is LOW, it enables the transceivers to connect the local data bus to the system data
bus.

ALE — Address Latch Enable (Pin 25, Output)

• Since the address and data share the same pins (AD0–AD15), external logic needs to know
when an address is present versus data.
• ALE is pulsed HIGH during T1 (when the address is valid on the bus) to signal external latch
circuits (like the 8282) to capture and hold the address.
• After the address is latched, ALE goes LOW and the data phase begins.
📝 Note: ALE is the key signal that solves the address/data multiplexing problem. External 8282
latches use ALE to 'capture' the address and hold it steady throughout the data transfer.

M/IO (Active varies) — Memory or I/O Select (Pin 28, Output)

• This signal tells external memory and I/O devices whether the processor is accessing memory
or an I/O port.
• HIGH: Memory reference instruction (e.g., MOV AX, [1000H])
• LOW: I/O instruction (IN or OUT instructions)

WR (Active Low) — Write Control (Pin 29, Output)

• Asserted LOW whenever the processor writes data to memory or an I/O port.
• Memory and I/O devices use this signal to know they should accept the data on the bus.

INTA (Active Low) — Interrupt Acknowledge (Pin 24, Output)

• When the processor accepts an INTR interrupt request, it signals the interrupting device by
driving INTA LOW.
• The external interrupt controller (like the 8259A PIC) responds by placing the interrupt vector
number on the data bus.
HOLD — Pin 31 (Input) and HLDA — Pin 30 (Output)
• HOLD: An input from another bus master (usually a DMA controller). When asserted, it requests
the 8086 to release control of the system bus.
• HLDA (Hold Acknowledge): The 8086's response. When the 8086 accepts HOLD, it floats (tri-
states) its address, data, and control lines, then asserts HLDA HIGH to inform the DMA
controller it now has control of the bus.

⭐ Exam Tip: In Minimum Mode: HOLD/HLDA = DMA handshake. ALE demultiplexes address from
data. DT/R controls transceiver direction. M/IO distinguishes memory from I/O.
2.4 Maximum Mode Signals (Pins 24–31, when MN/MX = LOW)
In Maximum Mode, the MN/MX pin is grounded (logic LOW). Pins 24–31 are completely reassigned to
new functions. The 8086 no longer generates direct control signals; instead, it outputs status
information that the Intel 8288 Bus Controller decodes into proper control signals.

S0, S1, S2 (Active Low) — Status Signals (Pins 26–28, Output)

These three status lines are sent to the Intel 8288 Bus Controller. The 8288 decodes them to generate
all memory and I/O control signals (like MRDC, MWTC, IORC, IOWC, etc.).

S2 (Bar) S1 (Bar) S0 (Bar) Machine Cycle / Bus Operation

0 0 0 Interrupt Acknowledge

0 0 1 Read I/O Port

0 1 0 Write I/O Port

0 1 1 Halt

1 0 0 Code Access (Fetch)

1 0 1 Read Memory

1 1 0 Write Memory

1 1 1 Passive / Inactive (bus idle)

QS0, QS1 — Queue Status (Pins 25–24, Output)

These pins indicate the status of the internal 6-byte instruction queue. External devices (like the 8087
Math co-processor) use these signals to track the 8086's internal queue and stay synchronized with
instruction execution.

QS1 QS0 Queue Operation

0 0 No operation — queue is idle

0 1 First byte of opcode was fetched from queue

1 0 Queue was emptied (e.g., after a jump)

1 1 Subsequent byte of instruction fetched from queue

RQ/GT0 and RQ/GT1 — Bus Request/Grant (Pins 31–30, Bidirectional)

• These are bidirectional pins used for multi-master bus arbitration.
• A co-processor or another local bus master uses these pins to request the bus from the 8086.
• Protocol: The bus master sends a pulse on the RQ line → 8086 finishes its current bus cycle
→ sends an acknowledgement pulse on GT → master takes the bus → master sends another
pulse when done → 8086 reclaims the bus.
• RQ/GT0 has higher priority than RQ/GT1.
LOCK (Active Low) — Bus Lock (Pin 29, Output)
• Activated by the LOCK prefix instruction in the 8086 assembly language.
• While LOCK is active (LOW), other bus masters are prevented from gaining control of the
system bus.
• LOCK remains active from the start of the locked instruction until it completes.
• This ensures that a read-modify-write operation is atomic (uninterruptible).

Signals Moved to 8288 Bus Controller in Max Mode

The following signals, which are directly output by the 8086 in Minimum Mode, are NOT directly
available from the processor in Maximum Mode. They are generated by the Intel 8288 Bus Controller
after it decodes S0/S1/S2:
• WR (Low) — Write
• ALE — Address Latch Enable
• DEN (Low) — Data Enable
• DT/R (Low) — Data Transmit/Receive

⭐ Exam Tip: Max Mode vs Min Mode comparison: In Min Mode, 8086 generates all control signals
(pin 28 = M/IO, pin 29 = WR, etc.). In Max Mode, 8086 outputs status codes (S0, S1, S2) to the 8288
which then generates the actual control signals. Max Mode supports co-processors.
SECTION 3: INTERNAL ARCHITECTURE OF THE 8086
The 8086 is divided internally into two major functional units that operate in parallel. This parallel
operation is the secret behind the 8086's improved performance.

3.1 The Two Functional Units: BIU and EU

Feature BIU (Bus Interface Unit) EU (Execution Unit)

Role Handles all external bus Decodes and executes instructions

communication

What it does Fetches instructions from memory, Receives opcode from queue,
reads/writes data to memory and I/O decodes and runs it

Internal storage Instruction Queue (6-byte FIFO), General Purpose Regs, ALU,
Segment Registers, IP Pointer & Index Regs, Flags

Operates While EU is executing, BIU pre- While BIU is fetching, EU is

fetches next instruction executing current instruction

Key mechanism Pipelining (overlap of fetch and ALU performs arithmetic/logic

execute)

What is Pipelining?
In older processors, instructions were fetched and executed one at a time sequentially — fetch, then
execute, then fetch, then execute. The bus was idle during execution.
The 8086 solves this with pipelining:
11. While the EU is executing instruction N, the BIU simultaneously fetches instruction N+1 (and
N+2, etc.) and stores them in the instruction queue.
12. This overlapped operation significantly speeds up program execution.
13. The BIU fetches a new word (2 bytes) from memory whenever there are 2 or more empty bytes
in the queue.
14. If a branch/jump instruction is executed, the queue is discarded and refilled from the new
address.

3.2 Bus Interface Unit (BIU) — Detailed

The BIU contains the following components:

3.2.1 Instruction Queue

• A 6-byte First-In-First-Out (FIFO) buffer.
• The BIU pre-fetches up to 6 bytes of instruction code from memory and stores them here.
• The EU picks opcodes from this queue to execute, without waiting for memory access.
• This is the hardware implementation of pipelining.
3.2.2 Segment Registers
The 8086 divides its 1MB memory space into logical segments. There are four segment registers, each
16 bits wide:

Register Full Name Points To Offset Register Used

CS Code Segment Start of the current program IP (Instruction Pointer)

code

DS Data Segment Start of the program's data SI, DI, BX, or direct
area displacement

SS Stack Segment Start of the stack area SP (Stack Pointer) or BP (Base

Pointer)

ES Extra Segment Additional data storage (for DI (Destination Index)

string ops)

• Each segment can be up to 64 KB in size.

• Segments can overlap in memory.
• A segment register holds the starting (base) address of its segment, but not the full 20-bit
address — it holds a 16-bit paragraph address, which is shifted left by 4 bits to get the 20-bit
physical address.

3.2.3 Instruction Pointer (IP)

• 16-bit register that always points to the NEXT instruction to be fetched.
• It holds the 16-bit offset (distance) from the start of the Code Segment to the next instruction.
• IP is automatically incremented after each instruction fetch.
• The programmer cannot directly read or write IP; it is updated automatically by the BIU.
• Physical address of next instruction = (CS × 16) + IP

3.2.4 Address Generation and Internal Bus

• The BIU contains an adder/shifter that computes 20-bit physical addresses from the
segment:offset pair.
• The C-BUS (internal communication bus) connects BIU components.
• The B-BUS connects BIU to EU for instruction transfer via the queue.

3.3 Execution Unit (EU) — Detailed

The EU is responsible for actual computation. It contains:

3.3.1 ALU — Arithmetic Logic Unit

• A 16-bit ALU that performs all arithmetic (add, subtract, multiply, divide) and logical (AND, OR,
XOR, NOT) operations.
• The ALU uses temporary registers internally during calculations.
3.3.2 General Purpose Registers (4 × 16-bit)
Each of the four general purpose registers can be used as a full 16-bit register, or split into two
independent 8-bit registers:

16-bit High Byte (8-bit) Low Byte (8-bit) Primary Special Function

AX AH AL Accumulator — I/O, multiply, divide

BX BH BL Base register — memory addressing via

DS

CX CH CL Counter — SHIFT, ROTATE, LOOP

instructions

DX DH DL Data register — 32-bit multiply/divide

results

Accumulator Register (AX)

• AL holds the 8-bit result; AX holds the 16-bit result of arithmetic/logic.
• All I/O instructions (IN, OUT) must use AX or AL.
• Multiply and divide instructions implicitly use AX.

Base Register (BX)

• This is the only general-purpose register that can be used as a memory address pointer.
• When BX is used in an address calculation, the default segment register is DS.
• Example: MOV AL, [BX] — reads from address DS:BX.

Counter Register (CX)

• Implicitly used as a counter in SHIFT, ROTATE, and LOOP instructions.
• LOOP instruction: automatically decrements CX by 1, then jumps to the loop label if CX ≠ 0.
• REP prefix (for string operations) also uses CX as a count.

Data Register (DX)

• In 16×16 multiplication: AX × operand → result is 32 bits, stored in DX:AX (DX = high word, AX
= low word).
• In 32÷16 division: dividend is in DX:AX, divisor is a 16-bit operand → quotient in AX, remainder
in DX.
• Also used with IN/OUT for indirect I/O port addressing (DX holds the port number).

3.3.3 Pointer Registers (2 × 16-bit)

Register Name Function

SP Stack Pointer Holds the offset of the current top of the stack within SS. Auto-
updated by PUSH/POP.

BP Base Pointer Holds a base offset for accessing data within the stack segment
(SS). Used in based addressing mode.
 • SP and BP both work with the SS (Stack Segment) register.
• PUSH decrements SP by 2 (stack grows downward), then stores data.
• POP reads data from stack, then increments SP by 2.

3.3.4 Index Registers (2 × 16-bit)

Register Name Function

SI Source Index Holds the offset of the source operand for string instructions
(works with DS).

DI Destination Index Holds the offset of the destination operand for string instructions
(works with ES).

• Used in indexed addressing mode and string operations (MOVS, CMPS, SCAS, LODS, STOS).

3.3.5 Complete Register Summary Table

Register Name Width Special Purpose

AX Accumulator 16-bit I/O, multiply, divide, 16-bit results

AL Low Accumulator 8-bit 8-bit I/O, 8-bit results

AH High Accumulator 8-bit High byte of AX

BX Base 16-bit Memory base address (uses DS)

CX Counter 16-bit SHIFT, ROTATE, LOOP count

DX Data 16-bit 32-bit multiply/divide, indirect I/O port

SP Stack Pointer 16-bit Top of stack offset (uses SS)

BP Base Pointer 16-bit Stack frame base (uses SS)

SI Source Index 16-bit Source for string ops (uses DS)

DI Destination Index 16-bit Destination for string ops (uses ES)

IP Instruction Pointer 16-bit Next instruction offset (uses CS)

CS Code Segment 16-bit Base of code segment

DS Data Segment 16-bit Base of data segment

SS Stack Segment 16-bit Base of stack segment

ES Extra Segment 16-bit Base of extra (string dest.) segment

FLAGS Flag Register 16-bit Status and control flags

3.4 The Flag Register
The 8086 has a 16-bit Flag Register (also called the Program Status Word, PSW). Only 9 of the 16 bits
are used. They are divided into two categories: Condition Flags (set automatically by results) and
Control Flags (set deliberately by programmers).

Flag bit positions (bit 15 down to bit 0):

Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

— — — — OF DF IF TF SF ZF — AF — PF — CF

3.4.1 Condition (Status) Flags

These flags are automatically set or cleared by the processor after arithmetic/logical operations. The
programmer reads them to make decisions (using conditional jump instructions).

CF — Carry Flag (Bit 0)

• Set to 1 when there is a carry out of the MSB (Most Significant Bit) during addition.
• Set to 1 when there is a borrow during subtraction.
• Used to chain multi-word arithmetic (e.g., 32-bit addition using two 16-bit ADDs).

PF — Parity Flag (Bit 2)

• Set to 1 if the lower byte of the result contains an even number of 1 bits.
• Set to 0 if the lower byte contains an odd number of 1 bits.
• Used in communications for error checking.

AF — Auxiliary Carry Flag (Bit 4)

• Set when there is a carry from bit 3 to bit 4 (from the lower nibble to the upper nibble) during
addition.
• Set when there is a borrow from bit 4 to bit 3 during subtraction.
• Used by BCD (Binary-Coded Decimal) arithmetic instructions like DAA and DAS.

ZF — Zero Flag (Bit 6)

• Set to 1 when the result of an operation is zero.
• Cleared to 0 when the result is non-zero.
• Heavily used by conditional jumps (JZ = Jump if Zero, JNZ = Jump if Not Zero).

SF — Sign Flag (Bit 7)

• Set to 1 when the result of a signed operation is negative (i.e., the MSB of the result is 1).
• Cleared to 0 when the result is positive.

OF — Overflow Flag (Bit 11)

• Set to 1 when the result of a signed operation is too large to fit in the destination register.
 • For 8-bit operations: overflow if result > +127 or < –128.
• For 16-bit operations: overflow if result > +32767 or < –32768.
• Important: CF is for unsigned overflow; OF is for signed overflow.

3.4.2 Control Flags

These flags are set or cleared deliberately by the programmer using specific instructions. They control
the behavior of certain instructions.

TF — Trap Flag (Bit 8)

• When set to 1, the processor enters single-step mode.
• In single-step mode, after each instruction executes, the processor generates an internal
interrupt (INT 1), pausing execution.
• This is used by debuggers (like [Link]) to allow step-by-step program tracing.

IF — Interrupt Enable Flag (Bit 9)

• IF = 1 (set): The INTR (maskable interrupt) pin is enabled — the processor will respond to
external interrupts.
• IF = 0 (cleared): The INTR pin is disabled — the processor ignores external interrupt requests.
• Set using the STI instruction (Set Interrupt Enable).
• Cleared using the CLI instruction (Clear Interrupt Enable).
• NMI (Non-Maskable Interrupt) is NEVER affected by the IF flag — it always gets through.

DF — Direction Flag (Bit 10)

• Used exclusively by string manipulation instructions (MOVS, CMPS, SCAS, LODS, STOS).
• DF = 0: String is processed from LOW address to HIGH address (auto-increment mode). SI and
DI are incremented after each operation.
• DF = 1: String is processed from HIGH address to LOW address (auto-decrement mode). SI
and DI are decremented after each operation.
• Set using STD (Set Direction), Cleared using CLD (Clear Direction).

⭐ Exam Tip: Remember the 6 condition flags: CF, PF, AF, ZF, SF, OF. Remember the 3 control
flags: TF, IF, DF. A useful mnemonic: 'Can People Always Zero Signals Overflow? Try If Directed.'
3.5 Physical Address Calculation — Segment:Offset Addressing
This is one of the most important and frequently examined topics in the 8086. Understanding exactly
HOW the processor translates a logical address to a physical address is crucial.

Why Segment:Offset Addressing?

• The 8086 registers are 16 bits wide, but the address bus is 20 bits wide.
• A 16-bit register can only address 2¹⁶ = 64KB. But we need to address 2²⁰ = 1MB.
• The solution: Use TWO registers — a segment register (base) + an offset register — to form a
20-bit address.

The Formula
Physical Address = (Segment Register × 16) + Offset
Multiplying by 16 in decimal is the same as shifting left by one hexadecimal digit (appending one zero
on the right in hex).

Step-by-Step Method
15. Take the 16-bit content of the segment register.
16. Shift it left by 4 bits (equivalent to multiplying by 16, or appending a '0' in hex).
17. Add the 16-bit offset value.
18. The result is the 20-bit physical address.

Worked Example 1
If CS = 0400H and IP = 0056H, what is the physical address of the next instruction?
• Step 1: Shift CS left by 4 bits: 0400H → 04000H
• Step 2: Add IP: 04000H + 0056H = 04056H
• Physical address = 04056H (decimal: 16470)

Worked Example 2
If DS = 7FA2H and offset = 438EH:
• a) Physical address: 7FA20H + 438EH = 83DAEH
• b) Lower range of segment: 7FA20H + 0000H = 7FA20H
• c) Upper range of segment: 7FA20H + FFFFH = 8FA1FH
• d) Logical address notation: 7FA2:438E

Worked Example 3 (Practice)

What physical address corresponds to logical address 028F:0030?
• 028FH → 028F0H (shift left by one hex digit)
• 028F0H + 0030H = 02920H ✓
Segment:Offset for Different Segments
Segment
Segment Offset Register Formula Used For
Register

Code CS IP CS×16 + IP Next instruction to fetch

Data DS SI / DI / BX / disp DS×16 + EA Data operands

Stack SS SP or BP SS×16 + SP or BP Stack operations

Extra ES DI ES×16 + DI String destinations

📝 Note: One important insight: Multiple logical addresses can map to the same physical address! For
example, 1234:0016 and 1235:0006 both resolve to physical address 12356H. This is called
'aliasing.'
SECTION 4: ADDRESSING MODES OF THE 8086
An addressing mode defines HOW an instruction specifies where its operand (data) is located. The
8086 supports 8 addressing modes, grouped into two categories.

4.1 Overview and Grouping

Group Addressing Mode Where is the Data?

Group I Register Addressing In a CPU register

Group I Immediate Addressing In the instruction itself

Group II Direct Addressing In memory, at a fixed address given in the

instruction

Group II Register Indirect Addressing In memory, at address held in BX/BP/SI/DI

Group II Based Addressing In memory, at BX or BP + a constant

displacement

Group II Indexed Addressing In memory, at SI or DI + a constant

displacement

Group II Based Indexed Addressing In memory, at base register + index register

Group II Based Indexed with Displacement In memory, at base + index + constant

4.2 Physical Address Calculation for Memory Modes

For all Group II (memory) addressing modes, the processor calculates the physical address as follows:
• The Effective Address (EA) is the 16-bit offset, calculated from the addressing mode formula.
• Physical Address = (Segment Register × 16) + EA
By default, most data accesses use DS as the segment register (except BP-based, which uses SS).
4.3 Group I: Register and Immediate Addressing

4.3.1 Register Addressing Mode

The operand is located directly inside a CPU register. The instruction names the register.

• Formula: No memory access. Data is in the register.

• Fastest mode: No memory bus cycle needed — register access is extremely fast.

Examples:
• MOV CL, DH — Copies content of 8-bit register DH into 8-bit register CL. Operation: (CL) ←
(DH)
• MOV AX, BX — Copies 16-bit content of BX into AX. Operation: (AX) ← (BX)
• ADD AX, CX — Adds CX to AX and stores result in AX. Operation: (AX) ← (AX) + (CX)

📝 Note: Both source and destination must be the same size (both 8-bit, or both 16-bit). You cannot
mix sizes: MOV AL, BX is INVALID.

4.3.2 Immediate Addressing Mode

The operand is a constant value (a literal number) that is part of the instruction itself — it is embedded
directly in the instruction's binary encoding. There is no need to fetch it from a register or memory
location.

• Formula: Data is part of the instruction — it comes from the instruction queue.
• The immediate value can be 8-bit or 16-bit.

Examples:
• MOV DL, 08H — Loads the 8-bit immediate value 08H into DL. Operation: (DL) ← 08H
• MOV AX, 0A9FH — Loads the 16-bit immediate value 0A9FH into AX. Operation: (AX) ←
0A9FH
• ADD BX, 100H — Adds 256 (100H) to the current content of BX.

📝 Note: The immediate value is always the SOURCE. You cannot use immediate addressing for the
destination. MOV 05H, AL is INVALID.
4.4 Group II: Memory Addressing Modes
For all of these modes, the data is in memory. The processor needs to calculate the memory address
(called the Effective Address or EA) before it can access the data.
Important: For Group II modes, the instruction uses square brackets [ ] around the address/register to
denote 'the contents at this memory location.' This is called indirection.

4.4.1 Direct Addressing Mode

The operand's 16-bit offset address is written directly as a number inside the instruction. The BIU uses
DS as the default segment register.

• Effective Address Formula: EA = Displacement (the 16-bit value written in the instruction)
• Physical Address: (DS × 16) + displacement
• Simplest memory mode: The address is fixed at assembly time.

Examples:
• MOV BX, [1354H] — Copies the 16-bit contents of memory location (DS:1354H) into BX.
• MOV BL, [0400H] — Copies the 8-bit content of memory location (DS:0400H) into BL.

Worked Calculation:
• If DS = 2000H and instruction is MOV BX, [1354H]:
• Physical address = (2000H × 16) + 1354H = 20000H + 1354H = 21354H

📝 Note: This mode is called 'direct' because the memory address is directly specified in the
instruction with no computation needed at runtime.

4.4.2 Register Indirect Addressing Mode

The 16-bit offset address is NOT written in the instruction. Instead, it is held inside one of the registers
BX, BP, SI, or DI. The instruction tells the processor which register to look at.

• Registers allowed: BX, BP, SI, or DI (only these four)

• EA Formula: EA = (Register) — the content of the named register IS the offset
• Default segment: DS for BX, SI, DI; SS for BP

Examples:
• MOV CX, [BX] — CX ← Memory[DS:BX]. BX holds the offset.
• ADD AL, [SI] — AL ← AL + Memory[DS:SI]. SI holds the offset.
• MOV AX, [DI] — AX ← Memory[DS:DI]. DI holds the offset.

Why is this powerful?

• You can change the register's value in a loop to access different memory locations! This makes
it ideal for array processing.
4.4.3 Based Addressing Mode
The effective address is calculated by adding a constant displacement (8-bit or 16-bit number) to the
content of a base register (BX or BP).

• Base registers allowed: BX (uses DS as default segment), BP (uses SS as default segment)

• EA Formula: EA = [BX] + displacement OR EA = [BP] + displacement

Examples:
• MOV AL, [BX + 05H] — EA = (BX) + 5. Reads byte from DS : ((BX)+5)
• MOV AL, [BX + 1346H] — EA = (BX) + 1346H. Reads byte from DS : ((BX)+1346H)
• MOV AX, [BP + 04H] — EA = (BP) + 4. Reads from SS : ((BP)+4) — useful for accessing
function parameters on the stack!

Practical Use: Based addressing is perfect for accessing fields of a structure (like a C struct) where BX
holds the start address of the structure and the displacement selects which field to access.

4.4.4 Indexed Addressing Mode

Very similar to Based Addressing, but uses an INDEX register (SI or DI) instead of a base register, plus
a constant displacement.

• Index registers allowed: SI or DI

• EA Formula: EA = [SI] + displacement OR EA = [DI] + displacement
• Default segment: DS for both SI and DI

Examples:
• MOV AX, [SI + 05] — EA = (SI) + 5. Reads 16-bit value from DS : ((SI)+5)
• MOV AX, [SI + 1528H] — EA = (SI) + 1528H

Practical Use: Indexed addressing is ideal for array access. The displacement gives the base address
of the array, and SI/DI is the index (element number × element size) to select which element.

4.4.5 Based Indexed Addressing Mode

Combines a BASE register (BX or BP) AND an INDEX register (SI or DI). No additional constant
displacement.

• EA Formula: EA = [BX or BP] + [SI or DI]

• Valid combinations: [BX+SI], [BX+DI], [BP+SI], [BP+DI]

Examples:
• ADD AX, [BX + SI] — EA = (BX) + (SI). Reads from DS : ((BX)+(SI))
• MOV CX, [BP + DI] — EA = (BP) + (DI). Reads from SS : ((BP)+(DI))
Practical Use: Excellent for accessing elements of a 2D array. BX can hold the row base address, and
SI can hold the column offset. Changing SI steps through one row; changing BX steps to the next row.

4.4.6 Based Indexed Addressing with Displacement

The most complex addressing mode. The EA is calculated from ALL THREE components: a base
register + an index register + a constant displacement.

• EA Formula: EA = [BX or BP] + [SI or DI] + 8-bit or 16-bit displacement

Examples:
• MOV AX, [BX + SI + 05] — EA = (BX) + (SI) + 5
• MOV AX, [BX + SI + 1235H] — EA = (BX) + (SI) + 1235H

Practical Use: Useful for accessing a record (structure) within an array. BX points to the array start, SI
selects the element (index), and the displacement selects the field within the element.
4.5 Complete Summary of All Addressing Modes

Mode EA Formula Example Segment Used

Register No EA — data in register MOV AX, BX N/A

Immediate No EA — data in instruction MOV AL, 55H N/A

Direct EA = displacement MOV BX, [1354H] DS

Register Indirect EA = [BX/BP/SI/DI] MOV CX, [BX] DS (or SS for BP)

Based EA = [BX/BP] + disp MOV AL, [BX+05H] DS (BX) / SS (BP)

Indexed EA = [SI/DI] + disp MOV AX, [SI+1528H] DS

Based Indexed EA = [BX/BP] + [SI/DI] ADD AX, [BX+SI] DS (BX) / SS (BP)

Based Indexed + Disp EA = [BX/BP]+[SI/DI]+disp MOV AX,[BX+SI+05] DS (BX) / SS (BP)

4.6 Important Rules for Memory Addressing

• Only BX, BP, SI, DI can be used in memory address calculations inside brackets [ ].
• AX, CX, DX cannot be used as memory pointers — MOV AL, [AX] is INVALID.
• BP always defaults to SS segment; BX, SI, DI default to DS.
• You can override the default segment using a segment override prefix: MOV AX, ES:[BX].

⭐ Exam Tip: For exam questions about addressing modes: always (1) identify the mode by name, (2)
write the EA formula, (3) calculate the physical address if segment register values are given. Practice
is key!
SECTION 5: QUICK REVISION TABLES

5.1 8086 Pins — Quick Reference

Pin(s) Name Mode Key Facts

1, 20 GND Both Ground

40 VCC Both +5V Power supply

2–16, 39 AD0–AD15 Both Multiplexed Address/Data bus

35–38 A16–A19 / S3–S6 Both High address lines / Status

34 BHE / S7 Both Bus High Enable for upper data byte

33 MN/MX Both Mode select: HIGH=Min, LOW=Max

32 RD Both Read control (active low)

31 HOLD (min) / RQ/GT0 Both Bus request

(max)

30 HLDA (min) / RQ/GT1 Both Bus acknowledge / grant

(max)

29 WR (min) / LOCK (max) Mode-dep. Write / Bus lock

28 M/IO (min) / S2 (max) Mode-dep. Mem vs I/O / Status

27 DT/R (min) / S1 (max) Mode-dep. Data direction / Status

26 DEN (min) / S0 (max) Mode-dep. Data enable / Status

25 ALE (min) / QS0 (max) Mode-dep. Address latch enable / Queue status

24 INTA (min) / QS1 (max) Mode-dep. Interrupt ack / Queue status

23 TEST Both WAIT instruction input

22 READY Both Slow device handshake

21 RESET Both Reset (must be HIGH ≥ 4 clocks)

19 CLK Both Clock (5/8/10 MHz)

18 INTR Both Maskable interrupt (active high)

17 NMI Both Non-maskable interrupt (edge triggered)

5.2 All Flags at a Glance
Flag Bit Type Set When... Instruction to Set/Clear

CF 0 Condition Unsigned carry/borrow at MSB STC (set), CLC (clear)

PF 2 Condition Lower byte of result has even Auto-set by ALU

count of 1s

AF 4 Condition Carry/borrow between nibbles Auto-set by ALU

(bit 3–4)

ZF 6 Condition Result is zero Auto-set by ALU

SF 7 Condition MSB of result is 1 (result Auto-set by ALU

negative)

TF 8 Control Single-step debug mode Auto-set/cleared by debugger

IF 9 Control Maskable interrupts enabled STI (set), CLI (clear)

DF 10 Control String processed high→low STD (set), CLD (clear)

OF 11 Condition Signed overflow occurred Auto-set by ALU

5.3 Addressing Mode Quick Reference

# Mode Group EA Calculation Key Registers

1 Register I No EA (data in register) AX BX CX DX SP BP SI DI

2 Immediate I No EA (data in instruction) Any destination register

3 Direct II EA = disp16 None (fixed address)

4 Register Indirect II EA = [Reg] BX BP SI DI

5 Based II EA = [BX/BP] + disp BX or BP + 8/16-bit disp

6 Indexed II EA = [SI/DI] + disp SI or DI + 8/16-bit disp

7 Based Indexed II EA = [Base] + [Index] (BX or BP) + (SI or DI)

8 Based Indexed + Disp II EA = [Base]+[Index]+disp (BX/BP)+(SI/DI)+disp

5.4 BIU vs EU Comparison

Aspect BIU EU

Full Name Bus Interface Unit Execution Unit

Main Role External bus communication Decode and execute instructions

Key Registers CS, DS, SS, ES, IP, Queue AX,BX,CX,DX, SP,BP,SI,DI, ALU,
Flags

Queue size 6 bytes (FIFO) —

Address generation Computes 20-bit physical addresses Uses EA from EU for memory modes
 Aspect BIU EU

Operates when BIU is always running (pre-fetching) Whenever a complete instruction is in

queue

5.5 Segment Register Default Associations

Segment Register Memory Region Default Offset Register When Used

CS Program Code IP Fetching every instruction

DS Data BX, SI, DI, displacement Most data reads/writes

SS Stack SP (PUSH/POP), BP PUSH, POP, CALL, RET

(based)

ES Extra Data (strings) DI String destination

operations
SECTION 6: PRACTICE QUESTIONS (Exam Style)

Short Answer Questions

19. What is the maximum memory addressable by the 8086 microprocessor and why?
Answer: 1 MB (1,048,576 bytes), because the 8086 has 20 address lines (2²⁰ = 1,048,576).

20. Differentiate between minimum mode and maximum mode of the 8086.
Answer: In minimum mode (MN/MX = HIGH), the 8086 generates all bus control signals itself (DEN,
ALE, WR, M/IO, DT/R, INTA) and cannot work with co-processors. In maximum mode (MN/MX =
LOW), pins 24–31 are reassigned as status outputs (S0–S2, QS0–QS1, LOCK, RQ/GT); an external
8288 Bus Controller decodes these to generate bus signals. Max mode supports co-processors and
multiprocessor systems.

21. What is the purpose of the ALE signal in the 8086?

Answer: ALE (Address Latch Enable) pulses HIGH during T1 of each bus cycle, when a valid 20-bit
address is present on the multiplexed AD0–AD19 bus. External 8282 latches use ALE to capture and
hold the address throughout the bus cycle, since the same pins will later carry data.

22. What are the differences between INTR and NMI?

Answer: INTR is a maskable interrupt (can be disabled with CLI instruction), level-triggered (active
high), and sampled at the end of each instruction. NMI is non-maskable (cannot be disabled by
software), edge-triggered (responds to rising edge), and always processed regardless of the IF flag.

Address Calculation Exercises

23. Calculate the physical address for CS = 3000H, IP = 0500H.
Solution: 30000H + 0500H = 30500H

24. If DS = 4A00H and a MOV instruction uses [BX] with BX = 0200H, find the physical
address.
Solution: (4A00H × 16) + 0200H = 4A000H + 0200H = 4A200H

25. Find the physical address for stack access with SS = 2000H, SP = 0100H.
Solution: (2000H × 16) + 0100H = 20000H + 0100H = 20100H

Identify the Addressing Mode

Instruction Addressing Mode Notes

MOV AX, BX Register Both operands are registers

MOV AL, 55H Immediate 55H is a constant in the instruction

MOV CX, [2050H] Direct 2050H is a fixed offset

 Instruction Addressing Mode Notes

MOV DX, [BX] Register Indirect BX holds the offset address

MOV AL, [SI+10H] Indexed EA = (SI) + 10H

MOV AX, [BX+20H] Based EA = (BX) + 20H

MOV AX, [BX+DI] Based Indexed EA = (BX) + (DI)

MOV AX, [BP+SI+04H] Based Indexed+Disp EA = (BP)+(SI)+4

 END OF STUDY NOTES
8086 Microprocessor | Compiled from course lecture slides