NUMBER SYSTEMS
A number system represents numbers using digits and a base (radix). 1) AND Gate
Weighted Code Output is 1 only when all inputs are 1
A B Y = A·B
Positional weighted system
Ex: Binary, octal, BCD, etc 0 0 0
0 1 0
Unweighted Code 1 0 0
Non- positional weighted system 1 1 1
Ex: Gray code, Excess 3 code, etc
2) OR Gate
Binary Number System Output is 1 if any input is 1
Uses only two digits: 0 and 1 A B Y=A+B
Each digit is called a bit 0 0 0
Example: 0 1 1
(1011)₂ = 1×2³ + 0×2² + 1×2¹ + 1×2⁰ = 11₁₀ 1 0 1
Notes (Boolean expressions) 1 1 1
n
Max possible minterm or maxterm: 2 3) NOT Gate (Inverter)
Max possible logical expressions: Output is opposite of input
A =
Max possible self dual expression: 0 1
1’s Complement 1 0
Change 0 → 1 and 1 → 0 4) NAND Gate
2’s Complement Opposite of AND
1’s complement + 1 A B Y = (A·B)
0 0 1
BCD (Binary Coded Decimal) 0 1 1
Each decimal digit → 4-bit binary 1 0 1
Also called 8421 code 1 1 0
Excess-3 Code (XS-3) 5) NOR Gate
BCD + 3 (0011) Opposite of OR
Gray Code A B Y = (A + B)
Adjacent numbers differ by only one bit 0 0 1
Used to reduce errors in digital systems 0 1 0
1 0 0
Binary to Gray code conversion 1 1 0
6) XOR Gate (Exclusive OR)
Output is 1 when inputs are different
A B Y=A⊕B
0 0 0
0 1 1
1 0 1
Gray code to Binary conversion 1 1 0
7) XNOR Gate (Exclusive NOR)
Output is 1 when inputs are same
A B Y = (A B)
0 0 1
0 1 0
1 0 0
ASCII Code: American Standard Code for Information Interchange 1 1 1
Uses 7 bits → 128 characters
Represents characters (letters, numbers, symbols).
EBCDIC Code: Extended BCD Interchange Code
Uses 8 bits → 256 characters
Basic Boolean Laws 3. Distributive Law 6. Idempotent Law
A⋅(B+C)=A⋅B+A⋅C A+A=A
1. Commutative Law A+(B⋅C)(A+B)(A+C) A⋅A=A
A+B=B+A AND distributes over OR and OR 7. Complement Law
A⋅B=B⋅A distributes over AND. + ′=1
Order of variables does not matter.
4. Identity Law A⋅ ′=0
2. Associative Law A+0=A Absorption Theorem
A+(B+C)=(A+B)+C A⋅1=A A+A⋅B=A
A⋅(B⋅C)=(A⋅B)⋅C
5. Null (Domination) Law A⋅(A+B)=A
Grouping does not matter.
A+1=1 De Morgan’s Theorem *
8. Involution Law A⋅0=0 (A⋅B)′=A′+B′
( ′)′=
( +B)′= ′⋅B′
Circuit Inputs Outputs Implemented By Key Feature
Half Adder A, B (2) S=A⊕B 5- NAND Gates No carry-in; basic 1-bit addition
C=A⋅B 5 NOR Gates
Full Adder A, B, Cin (3) S=A⊕B⊕Cin 2 Half Adders + OR Supports carry-in; used for
Cout=A⋅B+Cin⋅(A⊕B) 9 NAND Gates multi-bit addition
Half Subtractor A, B (2) D=A⊕B 5- NAND Gates No borrow-in; basic subtraction
Bout= ′⋅B 5 NOR Gate
Full Subtractor A, B, Bin (3) D=A⊕B⊕Bin 2 Half Subtractors + OR Supports borrow-in
Bout=A′⋅B+Bin⋅(A⊕B)′ 9 NAND Gates
Multiplexer 2ⁿ data + n select 1 AND-OR + NOT Many inputs → One output
Parallel to Serial Converter
Demultiplexer 1 data + n select 2ⁿ AND gates One input → Many outputs
Serial to Parallel Converter
Encoder 2ⁿ n OR gates Converts active input to binary code
Octal to Binary (8 x 3 lines)
Decoder n 2ⁿ AND + NOT Activates one output line
Binary to Octal (3 x 8 lines)
Comparator Two n-bit 3 (>, =, <) XOR, AND, OR Compares magnitudes
numbers
A sequential circuit is a digital circuit in which: Types of Sequential Circuits
Output depends on present input + past output
1. Based on Clock
Contains memory elements
Synchronous Sequential Circuit
Usually requires a clock signal
Controlled by clock
Mathematically: Q(t+1)=f(Q(t),X) State changes only at clock edge
Where: More stable and widely used
Q(t) = present state
Q(t+1) = next state Asynchronous Sequential Circuit
X = input No clock
Output changes immediately with input
Faster but unstable
Memory Elements (Flip-Flops)
Flip-flop stores 1 bit of information. 3. D Flip-Flop: Q(next)=D
“Delay” Flip-Flop
1. SR Flip-Flop: Q(next)=S+R′Q
Inputs: S (Set), R (Reset) D Q(next)
Outputs: Q Q 0 0
S R Q(next) 1 1
0 0 No change Characteristic Equation: Q(next)=D
0 1 0 Application:
1 0 1 Registers
Data storage
1 1 Invalid
Shift registers
Implementation: NOR or NAND gates
4. T Flip-Flop: Q(next)=Q⊕T
2. JK Flip-Flop: Q(next)=JQ′+K′Q
“T” = Toggle
Improved version of SR.
T Q(next)
J K Q(next)
0 No change
0 0 No-change
1 Toggle
0 1 0 Characteristic Equation: Q(next)=T⊕Q
1 0 1 Application:
1 1 Toggle (RAC) Binary counters
Characteristic Equation: Q(next)=JQ′+K′Q
Application:
Counters, Frequency division
Triggering refers to the method by which a flip-flop changes its state in response to a clock signal. It determines when input data is accepted
Level Trigger: responds while clock is at a particular level. (Ex- Latch)
Edge Trigger: changes state only at the instant of clock transition. (Flip flop)
A shift register is a sequential circuit that: A counter is a sequential circuit that:
Stores binary data Counts clock pulses
Shifts data one bit at a time with each clock pulse Goes through a fixed sequence of binary states
Built using flip-flops (usually D flip-flops) Built using flip-flops
Used for data transfer and storage Output represents count value
Feature Synchronous Counter Asynchronous
Type Input Output Key Feature Clock Input All flip-flops
st
Only 1 flip-flop
SISO Serial Serial Delay line Speed High Low
SIPO Serial Parallel Receiver side Propagation Low High(cumulative)
PISO Parallel Serial Transmitter side Delay
PIPO Parallel Parallel Storage register Sequence Fixed (Up, Down) Any (Ripple)
Decoding Error No Yes
Ring Counter (Synchronous) Johnson Counter (Twisted Ring Counter) (Synchronous)
A shift register counter in which: A shift register counter in which:
Output of last flip-flop is fed back to first flip-flop Complement of last output is fed back to first input
Only ONE flip-flop contains ‘1’ at any time
Parameter Value
Parameter Value
Flip-flops required n
Flip-flops required n
MOD 2n
MOD (number of states) n
Decoding Simple
Decoding Not required
Efficiency Higher than ring
Speed High n
n ✔ Unused state: 2 – 2n
✔Unused state: 2 – 2n
✔Output Frequency: fout = fin / n
✔Output Frequency: fout = fin / n
RTL — Resistor-Transistor Logic ECL — Emitter-Coupled Logic
Oldest logic family Fastest bipolar logic family.
Uses resistors for input network Extremely high speed
Very low speed Very high power consumption
High power dissipation Small Voltage swing
Poor noise immunity Used in high-frequency applications
It provide wired AND logic It provide wired OR logic
DTL — Diode-Transistor Logic Also called Current mode logic
Uses diodes for input logic Fan-In
Better noise immunity than RTL Maximum number of inputs to a gate.
Moderate speed Fan-Out
Largely obsolete Number of standard loads an output can drive.
It provide wired AND logic Propagation Delay
TTL — Transistor-Transistor Logic ⭐⭐⭐ Time between input change and output response.
Uses BJT transistors only Noise Margin
Good speed Tolerance to unwanted signals.
Moderate power consumption Power Dissipation
Supply voltage ≈ +5 V Power consumed by gate.
Widely used in 74xx series ICs
Speed-Power Product
It provide wired AND logic
Trade-off between speed and power consumption.
DAC — Digital to Analog Converter ADC — Analog to Digital Converter
Working Principle Basic Steps of Conversion
Each binary bit contributes a weighted value to produce a smooth 1. Sampling — Capture signal at intervals
analog output. 2. Quantization — Approximate amplitude levels
Type Method Key Feature 3. Encoding — Convert to binary number⭐
Binary Weighted Uses weighted Fast but needs precise Type Method Key Feature
DAC resistors resistors
Flash ADC Parallel comparators Fastest, expensive
Uses only two
R–2R Ladder DAC Most popular, accurate Successive
resistor values Binary search method Most widely used
Approximation
Pulse-width
PWM DAC Low cost Dual Slope ADC Integrating method High accuracy, slow
modulation + filter
Counter ADC Depends on input Ramp type
Important Specifications
No. of Clock: Flash-1, SAR-n, Dual Slope-2
n+1 n
Resolution = Number of bits , Counter-2 -1
Step Size (LSB value) = Vref / (2ⁿ − 1)