PCIe x16 Gen 5 → MXM 3.

0B Adapter
Schematic Routing Map — Direct Connector Connections (No Inline Components)
Rev 1 · J1 = PCIe x16 CEM Edge (164-pin) · J2 = MXM 3.0B Slot (314-pin, 0.5 mm pitch, Molex 67491-3140)
Naming: PCIe Gen 5 CEM Specification (PETp/PETn host TX; PERp/PERn host RX) · MXM 3.1 Module Specification (PEX_TX GPU transmit; PEX_RX GPU receive)

Legend & Signal Direction Conventions

Symbol Meaning Symbol Meaning
PCIe Host TX pair (host→GPU). Direct
PETp/PETn connection — AC coupling confirmed on PEX_RX / PEX_RX# MXM GPU receive (host→GPU)
Z890 motherboard upstream of J1.
PCIe Host RX pair (GPU→host). Direct
PERp/PERn connection — AC coupling caps are on PEX_TX / PEX_TX# MXM GPU transmit (GPU→host)
the MXM module itself.
Physical pin number on PCIe CEM edge Physical pin number on MXM 3.0B slot
J1 Pin J2 Pin
connector (per PCIe 5.0 CEM spec) connector (per MXM 3.1 spec)

1 PCIe Sideband & Control Signals — Direct (No Inline Components except as noted)
These signals route point-to-point from J1 to J2 with no intervening components. The REFCLK pair must be length-matched within ±100 mil (P/N pair); the PEX_RST# and
PEX_CLK_REQ# lines must not share ground return paths with high-current domains.

J1
Signal Inline J2 Pin J2 Signal
J1 Pin Net Name Direction Notes
(PCIe Component (MXM) (MXM 3.1)
CEM)

PERST# B3 PEX_RST# — 156 PEX_RST# Host → GPU Active-low reset; J1 B3

tied directly to J2-156

REFCLK+ B9 PEX_REFCLK — 155 PEX_REFCLK Host → GPU 100 MHz differential;

match within ±100 mil
Pair with REFCLK+;
REFCLK− B10 PEX_REFCLK# — 153 PEX_REFCLK# Host → GPU route as tightly coupled
diff pair

CLKREQ# B40 PEX_CLK_REQ# — 154 PEX_CLK_REQ# GPU → Host Open-drain; MXM has
internal 100 kΩ pull-up
Open-drain; optional —
WAKE# B41 WAKE# — 4 WAKE# Bidir may leave open w/ 10
kΩ pull-up to 3.3V
Short A1 to GND on
PRSNT1# A1 GND_PRSNT — — (GND only) — PCIe edge connector;
no MXM connection
Short B164 to GND on
PRSNT2# B164 GND_PRSNT — — (GND only) — PCIe edge connector;
no MXM connection
2 PCIe Host TX Lanes — J1 PETp/PETn → J2 MXM PEX_RX (Direct — No Inline Components)
Host transmits on PCIe B-side (PET) → GPU receives on MXM PEX_RX pins. All 16 lanes route directly with no inline components — AC coupling is confirmed to be handled by the
ASUS Z890 upstream of J1. Net names use host-centric convention: PEX_TX_P[n] / PEX_TX_N[n].

J1 Signal (+) J1 Signal (−) J2 Pin J2 Signal (+) J2 Pin J2 Signal (−)
Lane J1 Pin Net (+) Net (−) J1 Pin
(PCIe CEM) (PCIe CEM) (+) (MXM 3.1) (−) (MXM 3.1)
L0 PETp0 PEX_TX_P0 PEX_TX_N0 PETn0 149 PEX_RX0 147 PEX_RX0#
L1 PETp1 PEX_TX_P1 PEX_TX_N1 PETn1 143 PEX_RX1 141 PEX_RX1#
L2 PETp2 PEX_TX_P2 PEX_TX_N2 PETn2 137 PEX_RX2 135 PEX_RX2#
L3 PETp3 PEX_TX_P3 PEX_TX_N3 PETn3 123 PEX_RX3 121 PEX_RX3#
L4 PETp4 PEX_TX_P4 PEX_TX_N4 PETn4 117 PEX_RX4 115 PEX_RX4#
L5 PETp5 PEX_TX_P5 PEX_TX_N5 PETn5 111 PEX_RX5 109 PEX_RX5#
L6 PETp6 PEX_TX_P6 PEX_TX_N6 PETn6 105 PEX_RX6 103 PEX_RX6#
L7 PETp7 PEX_TX_P7 PEX_TX_N7 PETn7 99 PEX_RX7 97 PEX_RX7#
L8 PETp8 PEX_TX_P8 PEX_TX_N8 PETn8 93 PEX_RX8 91 PEX_RX8#
L9 PETp9 PEX_TX_P9 PEX_TX_N9 PETn9 87 PEX_RX9 85 PEX_RX9#
L10 PETp10 PEX_TX_P10 PEX_TX_N10 PETn10 79 PEX_RX10 77 PEX_RX10#
L11 PETp11 PEX_TX_P11 PEX_TX_N11 PETn11 73 PEX_RX11 71 PEX_RX11#
L12 PETp12 PEX_TX_P12 PEX_TX_N12 PETn12 67 PEX_RX12 65 PEX_RX12#
L13 PETp13 PEX_TX_P13 PEX_TX_N13 PETn13 61 PEX_RX13 59 PEX_RX13#
L14 PETp14 PEX_TX_P14 PEX_TX_N14 PETn14 55 PEX_RX14 53 PEX_RX14#
L15 PETp15 PEX_TX_P15 PEX_TX_N15 PETn15 51 PEX_RX15 49 PEX_RX15#

3 PCIe Host RX Lanes — J1 PERp/PERn ← J2 MXM PEX_TX (Direct, No Components)

GPU transmits on MXM PEX_TX pins → Host receives on PCIe A-side (PER). No AC coupling capacitors on this direction. Net names: PEX_RX_P[n] / PEX_RX_N[n] (host-centric).

J1 Signal (+) J1 Signal (−) J2 Pin J2 Signal (+) J2 Pin J2 Signal (−)
Lane J1 Pin Net (+) Net (−) J1 Pin
(PCIe CEM) (PCIe CEM) (+) (MXM 3.1) (−) (MXM 3.1)
L0 PERp0 PEX_RX_P0 PEX_RX_N0 PERn0 150 PEX_TX0 148 PEX_TX0#
L1 PERp1 PEX_RX_P1 PEX_RX_N1 PERn1 144 PEX_TX1 142 PEX_TX1#
L2 PERp2 PEX_RX_P2 PEX_RX_N2 PERn2 138 PEX_TX2 136 PEX_TX2#
L3 PERp3 PEX_RX_P3 PEX_RX_N3 PERn3 122 PEX_TX3 120 PEX_TX3#
 J1 Signal (+) J1 Signal (−) J2 Pin J2 Signal (+) J2 Pin J2 Signal (−)
Lane J1 Pin Net (+) Net (−) J1 Pin
(PCIe CEM) (PCIe CEM) (+) (MXM 3.1) (−) (MXM 3.1)
L4 PERp4 PEX_RX_P4 PEX_RX_N4 PERn4 116 PEX_TX4 114 PEX_TX4#
L5 PERp5 PEX_RX_P5 PEX_RX_N5 PERn5 110 PEX_TX5 108 PEX_TX5#
L6 PERp6 PEX_RX_P6 PEX_RX_N6 PERn6 104 PEX_TX6 102 PEX_TX6#
L7 PERp7 PEX_RX_P7 PEX_RX_N7 PERn7 98 PEX_TX7 96 PEX_TX7#
L8 PERp8 PEX_RX_P8 PEX_RX_N8 PERn8 92 PEX_TX8 90 PEX_TX8#
L9 PERp9 PEX_RX_P9 PEX_RX_N9 PERn9 86 PEX_TX9 84 PEX_TX9#
L10 PERp10 PEX_RX_P10 PEX_RX_N10 PERn10 80 PEX_TX10 78 PEX_TX10#
L11 PERp11 PEX_RX_P11 PEX_RX_N11 PERn11 74 PEX_TX11 72 PEX_TX11#
L12 PERp12 PEX_RX_P12 PEX_RX_N12 PERn12 68 PEX_TX12 66 PEX_TX12#
L13 PERp13 PEX_RX_P13 PEX_RX_N13 PERn13 62 PEX_TX13 60 PEX_TX13#
L14 PERp14 PEX_RX_P14 PEX_RX_N14 PERn14 56 PEX_TX14 54 PEX_TX14#
L15 PERp15 PEX_RX_P15 PEX_RX_N15 PERn15 50 PEX_TX15 48 PEX_TX15#

4 DisplayPort Outputs — J2 MXM CONP1C → DP20 Connectors (Direct)

All four DP links route directly from MXM CONP1C pins to standard 20-pin DP female receptacles. DP data lanes carry 0.22 µF AC coupling (typically already on the MXM module
— verify against MS-1W0V1 schematic before adding board-level caps). AUX channels require a 1 kΩ + 100 nF RC filter on each line; HPD requires a 100 kΩ pull-up to 3.3V and an
ESD diode at the connector. These passive elements are not listed here — see Section 5 of the full design document.

DP Link A — Primary Display (full 4-lane DP 1.4)

J2 Pin J2 Pin MXM 3.1 Signal MXM 3.1 Signal DP Conn
Signal Notes
(+) (−) (+) (−) Pin +/−
L0 255 253 DP_A_L0 DP_A_L0# 2 / 3 Lane 0 — main link
L1 261 259 DP_A_L1 DP_A_L1# 5 / 6 Lane 1
L2 267 265 DP_A_L2 DP_A_L2# 11 / 12 Lane 2
L3 273 271 DP_A_L3 DP_A_L3# 14 / 15 Lane 3

AUX 279 277 DP_A_AUX DP_A_AUX# 17 / 16 AUX channel; add 1 kΩ + 100 nF

RC on each line

DP Link B — Secondary Display (4-lane DP)

J2 Pin J2 Pin MXM 3.1 Signal MXM 3.1 Signal DP Conn
Signal Notes
(+) (−) (+) (−) Pin +/−
L0 249 247 DP_B_L0 DP_B_L0# 2 / 3 DP_B Lane 0
L1 243 241 DP_B_L1 DP_B_L1# 5 / 6 DP_B Lane 1
L2 237 235 DP_B_L2 DP_B_L2# 11 / 12 DP_B Lane 2
 J2 Pin J2 Pin MXM 3.1 Signal MXM 3.1 Signal DP Conn
Signal Notes
(+) (−) (+) (−) Pin +/−
L3 231 229 DP_B_L3 DP_B_L3# 14 / 15 DP_B Lane 3

AUX 274 246 DP_B_AUX DP_B_AUX# 17 / 16 AUX; add 1 kΩ + 100 nF RC on

each line

DP Link C — Third Display

J2 Pin J2 Pin MXM 3.1 Signal MXM 3.1 Signal DP Conn
Signal Notes
(+) (−) (+) (−) Pin +/−
L0 201 199 DP_C_L0 DP_C_L0# 2 / 3 DP_C Lane 0
L1 207 205 DP_C_L1 DP_C_L1# 5 / 6 DP_C Lane 1
L2 213 211 DP_C_L2 DP_C_L2# 11 / 12 DP_C Lane 2
L3 219 217 DP_C_L3 DP_C_L3# 14 / 15 DP_C Lane 3

AUX 225 223 DP_C_AUX DP_C_AUX# 17 / 16 AUX; add 1 kΩ + 100 nF RC on

each line

DP Link D — Fourth Display

J2 Pin J2 Pin MXM 3.1 Signal MXM 3.1 Signal DP Conn
Signal Notes
(+) (−) (+) (−) Pin +/−
L0 208 206 DP_D_L0 DP_D_L0# 2 / 3 DP_D Lane 0
L1 214 212 DP_D_L1 DP_D_L1# 5 / 6 DP_D Lane 1
L2 220 218 DP_D_L2 DP_D_L2# 11 / 12 DP_D Lane 2
L3 226 224 DP_D_L3 DP_D_L3# 14 / 15 DP_D Lane 3

AUX 234 232 DP_D_AUX DP_D_AUX# 17 / 16 AUX; add 1 kΩ + 100 nF RC on

each line