8086 Microprocessor
Complete Exam Notes
Interrupts · Memory Architecture · Timing & Signals
Instruction Set · Encoding & Decoding
Detailed concepts · Examples · Diagrams · Tables
Table of Contents
1. Interrupts Unit
Types 0–4, NMI, IVT, Lifecycle, STI/CLI
2. Memory & Architecture
Physical org, Banking, A0/BHE, Interfacing
3. Timing & Signals
T-states, RD/WR/M-IO/ALE/BHE diagrams
4. Instruction Set & Programming
Categories, palindrome, Fibonacci, arrays
5. Instruction Encoding & Decoding
Opcode, Mod-Reg-R/M, Addressing modes
Chapter 1: Interrupts Unit
Types · Lifecycle · IVT · STI / CLI
An interrupt is a signal that temporarily halts the CPU's current execution, transfers control to a special
routine called the Interrupt Service Routine (ISR), and returns to the original program after servicing. Think
of it like a doorbell — you pause your work, answer the door, and come back.
1.1 Interrupt Lifecycle (Step-by-Step)
Ste
p Action Detail
1 Interrupt signal arrives INTR pin goes HIGH (hardware) or INT n instruction executes (software)
2 Check IF flag For INTR only — if IF=0 (CLI), interrupt is ignored. NMI is always accepted.
3 Finish current instruction CPU completes the instruction in progress (atomicity).
4 Push FLAGS to stack All status flags saved. IF and TF are cleared automatically.
5 Push CS to stack Code Segment register saved.
6 Push IP to stack Instruction Pointer saved (return address).
7 Fetch ISR address from IVT Physical address = Type_Number × 4. Read IP then CS from IVT.
8 Execute ISR CPU jumps to ISR and executes the interrupt handler code.
9 IRET instruction Pops IP, CS, FLAGS from stack — resumes original program exactly.
Note: NMI (Type 2) always bypasses the IF check — it cannot be masked by CLI.
1.2 Interrupt Types (0–4), NMI, and INTR
The 8086 supports 256 interrupt types (Type 0 – Type 255). The first five are hardware-dedicated; the rest
are software-assignable.
Type
# Name Trigger Maskable? Example
0 Divide Error DIV or IDIV with zero divisor No DIV BX when BX=0
1 Single Step TF=1 (Trap Flag set) No Debugger step-by-step mode
2 NMI NMI pin goes HIGH No Power failure, memory error
3 Breakpoint INT 3 instruction (1 byte) No Software debugger breakpoint
4 Overflow INTO instruction + OF=1 No Signed arithmetic overflow
INTR Hardware IRQ INTR pin + IF=1 (STI) Yes (CLI) Keyboard, timer, disk
INT n Software INT INT instruction (any n) No INT 21H (DOS services)
1.3 STI and CLI — Controlling INTR
STI — Set Interrupt Flag (IF = 1)
• Enables the INTR pin to be recognized.
• After STI, the CPU will service hardware interrupts.
• Syntax: STI (no operands)
CLI — Clear Interrupt Flag (IF = 0)
• Disables the INTR pin — hardware interrupts are ignored.
• Used in critical sections to prevent race conditions.
• NMI and software interrupts are still accepted.
• Syntax: CLI (no operands)
1.4 Interrupt Vector Table (IVT)
The IVT occupies the first 1KB of RAM — addresses 00000H to 003FFH. It holds 256 entries, each 4 bytes
wide (2 bytes for IP, 2 bytes for CS), storing the starting address of each ISR.
Formula: Vector Address = Type_Number × 4
Example: Keyboard = Type 9 → address = 9 × 4 = 0x0024
At 0x0024: read 2 bytes → ISR_IP, read next 2 bytes → ISR_CS
Type IVT Address Content
0 00000H–00003H IP then CS of Divide Error ISR
1 00004H–00007H IP then CS of Single Step ISR
2 00008H–0000BH IP then CS of NMI ISR
3 0000CH–0000FH IP then CS of Breakpoint ISR
4 00010H–00013H IP then CS of Overflow ISR
9 00024H–00027H IP then CS of Keyboard ISR
Chapter 2: Memory & Architecture
Physical Organization · Banking · A0/BHE · Interfacing
2.1 Physical Memory Organization
The 8086 has a 20-bit address bus (pins A0–A19), allowing it to address 220 = 1,048,576 bytes = 1 MB of
memory (addresses 00000H to FFFFFH). The data bus is 16 bits wide (D0–D15).
Because internal registers are only 16 bits, the 8086 uses a segmented memory model to reach 20-bit
addresses:
Physical Address Calculation
• Physical Address (PA) = Segment Register × 10H + Offset Register
• Example: CS = 1234H, IP = 5678H
• PA = 12340H + 5678H = 179B8H
• The × 10H shifts the segment left by one hex digit (4 bits).
Register Pair Segment Used for
CS : IP Code Segment Fetching instructions
SS : SP/BP Stack Segment Stack operations (PUSH/POP)
DS : SI/DI/BX Data Segment Data memory access
ES : DI Extra Segment String destination, extra data
2.2 Memory Banking — A0 and BHE
The 1 MB address space is split into two parallel 512 KB banks. The 16-bit data bus is physically divided —
Bank 0 drives D0–D7, Bank 1 drives D8–D15.
Data
Signal Value Bank Selected Lines Addresses
Even Bank (Bank
A0 0 0) D0–D7 00000H, 00002H, ... (even)
BHE 0 Odd Bank (Bank 1) D8–D15 00001H, 00003H, ... (odd)
Both A0=0,
BHE=0 — Both banks D0–D15 Word read in 1 bus cycle
A0=1, BHE=0 — Odd only D8–D15 Misaligned word → 2 cycles
Note: A word at an even address takes 1 bus cycle. A word at an odd address takes 2 cycles (the 8086 splits it into two
byte transfers). Always align word data to even addresses for speed.
2.3 Memory Interfacing Problems
Memory interfacing means connecting external RAM/ROM chips to the 8086 bus. The key steps are: (1)
determine chip count, (2) connect address lines, (3) use A0/BHE for bank selection, (4) decode higher
address lines for chip select.
Solved Example — Interface 8KB RAM at F0000H
• 8KB = 8192 bytes → needs 13 address lines (A0–A12) for internal addressing.
• Two 4KB × 8 chips needed: one for Even Bank (D0–D7), one for Odd Bank (D8–D15).
• Even chip: A0 = CS (active LOW means even address selected).
• Odd chip: BHE = CS (active LOW means high byte selected).
• A13–A19 decoded to generate base address F0000H → chip enable logic.
• A1–A12 connect to both chips for row/column addressing within the chip.
Chapter 3: Timing & Signals
Bus Cycle · T-States · Control Signals
3.1 The 8086 Bus Cycle
Every memory or I/O access takes at least 4 clock cycles, called T-states (T1, T2, T3, T4). Slow memory
may insert wait states (Tw) between T3 and T4.
T-State What the CPU does Key signals
Outputs address on AD0–AD15. ALE goes HIGH
T1 to latch address. ALE=HIGH, Address on AD0–AD15
Address lines float (tri-state). RD or WR goes
T2 LOW. RD or WR = LOW, AD lines float
Data appears on bus (read) or CPU drives data
T3 (write). Data valid on D0–D15
Wait state — inserted if READY pin is LOW (slow
Tw memory). READY = LOW
CPU latches data (read) or write completes.
T4 RD/WR goes HIGH. RD or WR = HIGH, cycle ends
3.2 Key Control Signals
Signal Type Active Function
RD Output LOW CPU is reading from memory or I/O
WR Output LOW CPU is writing to memory or I/O
HIGH=Mem,
M/IO Output LOW=I/O Distinguishes memory vs I/O access
ALE Output HIGH Address Latch Enable — address valid on AD bus
BHE Output LOW Bus High Enable — D8–D15 carry valid data
READY Input LOW Memory inserts wait states when pulled LOW
DEN Output LOW Data Enable — enables data bus transceivers
DT/R Output HIGH=Write Data Transmit/Receive direction control
HOLD Input HIGH DMA requests bus control
HLDA Output HIGH CPU acknowledges bus release to DMA
3.3 Multiplexed Address/Data Bus
The 8086 has only 40 pins. To fit 20 address lines and 16 data lines, pins AD0–AD15 carry the address
during T1 (while ALE is HIGH), then switch to carry data during T3. An external 8282/74LS373 latch
captures the address using ALE.
Why multiplexing?
• 40-pin DIP package limits available pins.
• ALE (T1 HIGH pulse) tells the latch: capture these 16 bits as address.
• After T1, the same pins carry 16-bit data.
• A4–A19 remain dedicated address lines (not multiplexed).
Chapter 4: Instruction Set & Programming
Categories · Key Instructions · Assembly Programs
4.1 Instruction Set Categories
Data Transfer
• MOV src, dst — move data between registers/memory
• PUSH / POP — stack operations
• IN / OUT — I/O port access
• XCHG — exchange two operands
• LEA — load effective address
• XLAT — table lookup translation
Arithmetic
• ADD, ADC (add with carry), SUB, SBB (subtract with borrow)
• MUL/IMUL — unsigned/signed multiply (result in AX or DX:AX)
• DIV/IDIV — unsigned/signed divide
• INC, DEC, NEG — increment, decrement, negate
• CMP — subtract without storing result (sets flags)
• DAA, DAS — decimal adjust after BCD add/subtract
Logical
• AND, OR, XOR — bitwise operations
• NOT — bitwise complement
• TEST — AND without storing (sets flags only)
• Used for masking bits, setting/clearing flags
Shift & Rotate
• SHL/SAL — shift left (multiply by 2)
• SHR — logical shift right (divide unsigned by 2)
• SAR — arithmetic shift right (preserves sign bit)
• ROL, ROR — rotate left/right through carry
• RCL, RCR — rotate through carry flag
• Count in CL register for shifts > 1
String Operations
• MOVS — move string (DS:SI to ES:DI)
• CMPS — compare strings byte/word
• SCAS — scan string (compare AL/AX with ES:DI)
• LODS — load string element into AL/AX
• STOS — store AL/AX to ES:DI
• REP, REPE, REPNE — repeat prefix using CX as counter
Control Transfer
• JMP — unconditional jump
• CALL / RET — subroutine call and return
• Jcc — conditional jumps: JZ, JNZ, JC, JNC, JA, JB, JG, JL...
• LOOP — decrement CX; jump if CX != 0
• INT n — software interrupt
• IRET — return from interrupt
4.2 Important Assembly Programs
Program 1: Palindrome Check — checks if a string reads the same forwards and backwards.
; Palindrome check
; String at 0500H, length 8
MOV SI, 0500H ; pointer to start
MOV DI, 0507H ; pointer to end
MOV CX, 04H ; compare half the length
LOOP1:
MOV AL, [SI] ; byte from start
CMP AL, [DI] ; compare with byte from end
JNE NOT_PAL ; mismatch -> not palindrome
INC SI ; move start pointer right
DEC DI ; move end pointer left
LOOP LOOP1 ; repeat CX times
MOV BL, 01H ; BL=1 means IS palindrome
JMP DONE
NOT_PAL:
MOV BL, 00H ; BL=0 means NOT palindrome
DONE: HLT
Program 2: Fibonacci Sequence — stores first N Fibonacci numbers in memory.
; Fibonacci sequence — store 8 terms at 0600H
MOV DI, 0600H ; destination pointer
MOV AX, 0000H ; F(0) = 0
MOV [DI], AX
ADD DI, 2
MOV AX, 0001H ; F(1) = 1
MOV [DI], AX
ADD DI, 2
MOV CX, 0006H ; generate 6 more terms
MOV BX, 0000H ; BX = previous-previous
MOV AX, 0001H ; AX = previous
FIB_LOOP:
MOV DX, AX ; save current
ADD AX, BX ; next = prev + prev-prev
MOV [DI], AX
ADD DI, 2
MOV BX, DX ; shift: prev-prev = old prev
LOOP FIB_LOOP
HLT
Program 3: Largest element in an array
; Find largest element in array at 0700H, count = 05H
MOV SI, 0700H ; start of array
MOV CX, 0004H ; compare count-1 times
MOV AL, [SI] ; assume first is largest
INC SI
CHECK:
CMP AL, [SI] ; compare with next element
JAE SKIP ; if AL >= [SI], skip update
MOV AL, [SI] ; new largest found
SKIP:
INC SI
LOOP CHECK
MOV [0800H], AL ; store result
HLT
Chapter 5: Instruction Encoding & Decoding
Opcode Format · Mod-Reg-R/M · Addressing Modes
5.1 General Instruction Format
Every 8086 instruction is stored as 1 to 6 bytes in memory. The CPU fetches these bytes from CS:IP and
decodes them to determine the operation.
Byte Name Size Required?
Byte 1–2 Opcode (+ D, W, S bits) 1–2 bytes Always
Byte 2–3 Mod-Reg-R/M 1 byte When memory/register operand used
Byte 3–4 Displacement (Lo, Hi) 0, 1, or 2 bytes When MOD=01 or MOD=10
Byte 5–6 Immediate data 0, 1, or 2 bytes When instruction has immediate operand
5.2 Opcode Byte — D and W Bits
D bit (Direction bit)
• D=1: REG field is the destination operand.
• D=0: REG field is the source operand (R/M is destination).
W bit (Word/Byte bit)
• W=1: Operation is on a 16-bit word (AX, BX, CX, DX, SP, BP, SI, DI).
• W=0: Operation is on an 8-bit byte (AL, AH, BL, BH, CL, CH, DL, DH).
5.3 Mod-Reg-R/M Byte (8 bits = 2 + 3 + 3)
When an instruction references a register or memory location as an operand, the second byte is the
Mod-Reg-R/M byte. It encodes the addressing mode.
Field Bits Values & Meaning
00 = no displacement (except R/M=110 → direct address) 01 = 8-bit signed displacement added to
MOD 2 base 10 = 16-bit displacement added to base 11 = register-to-register (no memory access)
Register code: 000=AX/AL, 001=CX/CL, 010=DX/DL, 011=BX/BL, 100=SP/AH, 101=BP/CH,
REG 3 110=SI/DH, 111=DI/BH
Memory mode: 000=[BX+SI], 001=[BX+DI], 010=[BP+SI], 011=[BP+DI], 100=[SI], 101=[DI],
R/M 3 110=[BP]/direct, 111=[BX]
5.4 Addressing Modes
Mode Assembly Example Effective Address Notes
Register MOV AX, BX EA = BX (no memory) Fastest — no memory access
Immediate MOV AX, 1234H Data in instruction Data is literal value
Direct MOV AX, [2000H] EA = 2000H Fixed memory location
Register Indirect MOV AX, [BX] EA = BX BX/BP/SI/DI hold address
Based MOV AX, [BX+10H] EA = BX + 10H Base + displacement
Indexed MOV AX, [SI+20H] EA = SI + 20H Index + displacement
Based Indexed MOV AX, [BX+SI] EA = BX + SI Base + Index
Based Indexed+Disp MOV AX, [BX+SI+5H] EA = BX+SI+5H Most complex mode
5.5 Encoding Example — MOV AX, BX
Step-by-step encoding of MOV AX, BX
• Operation: Move contents of BX into AX (word, register-to-register).
• Opcode for MOV reg, reg/mem = 1000 101x → 89H (D=0, W=1).
• Mod-Reg-R/M: MOD=11 (reg-reg), REG=000 (AX), R/M=011 (BX).
• Binary: 11 000 011 = C3H.
• Final machine code: 89H C3H (2 bytes).
Quick Reference Sheet
REG Field Codes (W=1 / W=0)
Code W=1 (Word) W=0 (Byte)
000 AX AL
001 CX CL
010 DX DL
011 BX BL
100 SP AH
101 BP CH
110 SI DH
111 DI BH
Conditional Jump Instructions
Mnemonic Condition Flag tested
JZ / JE Jump if Zero / Equal ZF=1
JNZ / JNE Jump if Not Zero / Not Equal ZF=0
JC / JB Jump if Carry / Below (unsigned) CF=1
JNC / JAE Jump if No Carry / Above or Equal CF=0
JS Jump if Sign (negative) SF=1
JO Jump if Overflow OF=1
JG / JNLE Jump if Greater (signed) ZF=0 and SF=OF
JL / JNGE Jump if Less (signed) SF != OF
8086 Flags Register
Flag Bit Meaning
CF 0 Carry Flag — set on unsigned overflow
PF 2 Parity Flag — set if low byte has even parity
AF 4 Auxiliary Carry — BCD carry from bit 3 to 4
ZF 6 Zero Flag — set if result is zero
SF 7 Sign Flag — set if result is negative
TF 8 Trap Flag — enables single-step mode (Type 1 interrupt)
IF 9 Interrupt Flag — STI sets, CLI clears; enables INTR
DF 10 Direction Flag — STD=1 auto-decrement SI/DI; CLD=0 auto-increment
OF 11 Overflow Flag — set on signed overflow
End of Notes — Good luck on your exam!