Al-Zaiem Al-Azahry University

Digital Systems Design II

(ENE309)

Outlines:
Memory and Programmable Logic
Lecture Objectives
• Define the architecture and operation of Random-Access
Memory (RAM).
• Analyze memory decoding techniques (1D vs. 2D Coincident
Decoding) to optimize hardware.
• Implement Error Detection and Correction using Hamming
Codes.

Introduction:
A memory unit is a device to which binary information is transferred for storage and from
which information is retrieved when needed for processing. When data processing takes
place, information from memory is transferred to selected registers in the processing unit.

There are two types of memories that are used in digital systems: random‐access memory
(RAM) and read‐only memory (ROM). RAM stores new information for later use.

The process of storing new information into memory is referred to as a memory write
operation. The process of transferring the stored information out of memory is referred to as
a memory read operation.

RAM can perform both write and read operations. ROM can perform only the reading
operation.
ROM is a programmable logic device (PLD), The binary information that is stored within such
a device is specified in some fashion and then embedded within the hardware in a process
is referred to as programming the device, such units are the programmable logic array (PLA),
programmable array logic (PAL), and the field‐programmable gate array (FPGA).

Part 1: Random-Access Memory (RAM)

1.1 Definitions and Architecture

While registers hold small amounts of data for immediate processing, a Memory Unit is a
collection of cells capable of storing large quantities of binary information.

The architecture of memory is such that information can be selectively retrieved from any of
its internal locations. The time it takes to transfer information to or from any desired random
location is always the same.

• RAM (Random-Access Memory): A memory where the time required to transfer information
to or from any desired location is the same, regardless of the location.

• Word: The entity of bits that move in and out of storage as a unit. A memory of 𝑚 words and
𝑛 bits per word is often described as an 𝑚 𝑥 𝑛 memory.

• Address: An identification number assigned to each word, ranging from 0 to2𝑘 − 1, where
𝑘 is the number of address lines.

Block Diagram Inputs/Outputs of Memory

• The memories vary in size and range from 1,024 words to 232 words requiring 32
addresses, the number of words are referred with one letter, K (kilo), M (mega), and G
(giga). K is equal to 210 , M is equal to 220 and G is equal to 230 .

1.2 Timing Waveforms

The operation of the memory unit is controlled by an external device such as a central
processing unit (CPU). The CPU is usually synchronized by its own clock. The memory,
however, does not employ an internal clock. Instead, its read and write operations are
specified by control inputs.

The access time of memory is the time required to select a word and read it. The cycle time
of memory is the time required to complete a write operation.

1.3 HDL description:

Memory is modeled in the Verilog hardware description language (HDL) by an array of

registers. It is declared with a reg keyword, using a two‐dimensional array. The first number
in the array specifies the number of bits in a word (the word length) and the second gives
the number of words in memory (memory depth). For example, a memory of 1,024 words
with 16 bits per word is declared as:

reg [15: 0] memword [0: 1023];

If the readeWrite is 1, the memory performs the read operations symobolized by the
statement:

DataOut Mem [Address];

Execution of this statement causes a transfer of four bits from the selected memory word

specified by Address onto the DataOut lines.

If ReadWrite is 0, the memory performs a write operation symbolized by the statement

Mem [Address]  DataIn;

1.4 Types of RAMS:

• Static RAM (SRAM): Uses internal latches to store binary information. It is easier to
use and has shorter read/write cycles but is less dense.
• Dynamic RAM (DRAM): Stores information as electric charges on capacitors. It
offers higher density and lower power consumption but requires refreshing
(periodically recharging the capacitors).

Part 2: Memory Decoding

Decoding circuits are required to select the specific memory word specified by the address
lines.

2.1 One-Dimensional (1D) Decoding (

For small memories, a single decoder is used. A memory with m words requires a 𝑘 𝑥 𝑚
decoder (where 𝑘 is the number of address bits).

The equivalent logic of a binary cell that stores one bit of information is shown in the below
figure. The storage part of the cell is modeled by an SR latch with associated gates to form a
D latch. Where the mechanism is instead of one large decoder, we use two smaller
decoders (Row Decoder and Column Decoder). A word is selected by the coincidence of
one active row line and one active column line.

But this type has its limitations as the memory size grows, the decoder becomes
enormous. A 1K word memory would require a 10×1024 decoder (1024 AND gates with 10
inputs each), which is physically impractical.
 Block Diagram of a 4 x 4 RAM
2.2 Two-Dimensional (Coincident) Decoding:

To reduce decoder size, cells are arranged in a square matrix. The address is split into two
parts: a Row Address and a Column Address.

The mechanism is instead of one large decoder; we use two smaller decoders (Row
Decoder and Column Decoder). A word is selected by the coincidence of one active row
line and one active column line.

Example: 1K Word Memory (1024 X 1)

• 1D Approach: Requires one 10×1024 decoder.

• 2D Approach: Arrange cells in a 32×32 matrix.
Address is 10 bits. Split into 5 bits for Row (X) and 5 bits for Column (Y), use two
5×32 decoders.
1D requires 1024 NAND gates. 2D requires only 64 NAND gates (32+32)
 Block Diagram of Two-Dimensional decoding of 1K RAM

Part 3: Error Detection and Correction

Reliability is critical. Errors can occur due to noise or component failure. The reliability of a
memory unit may be improved by employing error‐detecting and error‐correcting codes.

3.1 Hamming Code (Single Error Correction)

Hamming codes allow us to detect and correct a single bit error by adding k parity bits to
an n-bit data word.

In the hamming code the bits are added as in the relationship 2𝑘 ≥ 𝑛 + 𝑘 + 1, and the
positions numbered as powers of 2 (1,2,4,8...) are reserved for parity bit (𝑃1 𝑃2 𝑃3 𝑃4 ). The
remaining positions are data bits.

Consider, for example, the 8‐bit data word 11000100. We include 4 parity bits with

the 8‐bit word and arrange the 12 bits as follows:

3.2 Generation and Checking

• Parity Generation: Each parity bit checks specific bit positions.

checks positions from the above example:

𝑃1 checks positions XOR of bits (3, 5, 7, 9, 11) = 1 ⊕ 1 ⊕ 0 ⊕ 0 ⊕ 0 = 0

𝑃2 checks positions XOR of bits (3, 5, 7, 10, 11) = 1 ⊕ 0 ⊕ 0 ⊕ 1 ⊕ 0 = 0

𝑃3 checks positions XOR of bits (5, 6, 7, 12) = 1 ⊕ 0 ⊕ 0 ⊕ 0 = 1

𝑃4 checks positions XOR of bits (9, 10, 11, 12) = 0 ⊕ 1 ⊕ 0 ⊕ 0 = 1

The 8‐bit data word is stored in memory together with the 4 parity bits as a 12‐bit

composite word.

When the 12 bits are read from memory, they are checked again for errors. The parity is

checked over the same combination of bits, including the parity bit. The 4 check bits are

evaluated as follows:

When reading, we recalculate the check bits (C). If C=0, no error. If C≠0, the binary value of
C indicates the position of the error. We simply complement that bit to fix it.
Solved Problems:

a) How many address lines and input/output data lines are needed for a 64K x 8
memory unit?
Solution: 1K = 210 = 1024, 64K = 64 x 1024 = = 26 𝑥 210 = 216 𝑤𝑜𝑟𝑑𝑠 , we need 16
address lines, The memory is "x 8", meaning 8 bits per word. Thus, we need 8 data
input lines and 8 data output lines
b) Obtain the 13‐bit Hamming code word for the 9‐bit data word 110110110.
Solution:
Total bits = 12. Parity bits at 1, 2, 4, 8. Data bits at 3, 5, 6, 7, 9, 10, 11, 12.
1 2 3 4 5 6 7 8 9 10 11 12 13
𝑃1 𝑃2 1 𝑃4 1 0 1 𝑃8 1 0 1 1 0

Calculate Parity (Even Parity):

𝑃1 checks positions (3, 5, 7, 9, 11,13) = 1 ⊕ 1 ⊕ 1 ⊕ 1 ⊕ 1 ⊕ 0 = 1

𝑃2 checks positions (3, 6, 7, 10, 11) = 1 ⊕ 0 ⊕ 1 ⊕ 0 ⊕ 1 = 1

𝑃3 checks positions (5, 6, 7, 12,13) = 1 ⊕ 0 ⊕ 1 ⊕ 1 ⊕ 0 = 1

𝑃4 checks positions (9, 10, 11, 12,13) =1 ⊕ 0 ⊕ 1 ⊕ 1 ⊕ 0 = 1

1 2 3 4 5 6 7 8 9 10 11 12 13
1 1 1 1 1 0 1 1 1 0 1 1 0

The 13-bit Hamming code word is: 1111101110110