VLSI Testing
Test Compression
Motivating Problem
You generate 100Gb of test patterns
but ATE has only 80Gb ….
Your manger asks you to reduce 25% test patterns
but maintain same fault coverage
f1 f2 f3 f4 f5
t1 X
t2 X X
t3 X X X
t4 X X
Why Am I Learning This?
Test compression reduces test data
Reduces ATE cost, test cost and package cost
It is essential for modern complex designs
Introduction
What is test compression?
Reduces test data, keeps same test quality
Why test compression?
Reduce test data (ATE cost )
Reduce test time (test cost )
Reduce DFT pins (Package/ATE cost )
Why can we compress test data?
Test stimulus: ATPG patterns have many don’t care bits
Test responses: Not every bit needs to be observed
Compression v.s. compaction
Test stimulus compression is lossless
Test response compaction is lossy
Sometimes people use them interchangeably
More & More Compression Needed
Required compression ratio keep increasing
More 1,000x test compression needed by 2020!
Original Data
Compression Ratio
Compressed Data
Test Compression
Introduction
Software Techniques
Hardware Techniques
Test Stimulus Compression
Test Response Compaction
CUT
Test Compression
Introduction
Hardware Techniques
Test Stimulus Compression
Test Response Compression
Comparison of Techniques
Pure BIST HW Test Compression Traditional ATPG/ATE
+ Low cost ATE + Low cost ATE - Expensive ATE
+ Zero test data + Small test data - Large test data
- Low F.C. + High F.C. + High F.C.
- No test time reduction + Test time reduction - No test time reduction
Test Compression Has Advantages of Both Sides
W/Wo Test Compression DFT
Without compression Large
n very large ATE
CUT
n
chip
With compression
m << n
decompress
compressor
Small
ATE CUT
m
n
chip
Test Compression
Introduction
Hardware Techniques
Test Stimulus Compression
Code-based schemes
Dictionary code (fixed-to-fixed)
Huffman code (fixed-to-variable)
Broadcast-based schemes
Linear-decompression-based schemes
Test Response Compression
CUT
Dictionary Code (fixed-to-fixed)
Dictionary compresses a symbol into a codeword
2b codewords, 2n symbols. n > b b=2 n=4
Fixed-to-fixed: original data is fixed rate (=n) 00 0011
compressed data is fixed rate (=b) 01 0101
A scan slice is a vertical column of scan data 11 0111
10 1110
Original Data n
Compression Ratio
Compressed Data b
Huffman Code (fixed-to-variable)
Count the frequency of occurrence for each symbol
Higher frequency symbols are shorter codewords
Fixed-to-variable: original data is fixed rate
compressed data is variable rate
Original test pattern
Compressed test pattern
10 00 10 110 0110 10 111010 00 00 00 110 10
10 00 10 110 0110 110 10 00 110 10 10 0110
10 110 10 10 10 00 110 10 10 0111 11100
111100 00 10 010 10 010 010 00 00 00 0111 11100
111011 00 00 010 10 10 110 111101 10 00 111110 111111
Q: What is compression ratio of this Huffman code?
Frequency Pattern Huffman
code
6 0000 1
3 0100 00
1 1010 01
ANS:
4 10 40
CR 2.9
6 1 3 2 1 2 14
Problems with Code-based Schemes
Dictionary too large
Hardware overhead
Synchronization problem (Huffman)
ATE sends data at fixed rate, but Huffman require variable rate
Not easy to implement n=4 m=variable
decompress
compressor
Small
ATE CUT
m=?
n=4
chip
Code-based Not Useful in Practice
Test Compression
Introduction
Hardware Techniques
Test Stimulus Compression
Test Response Compaction(TRC)
CUT
What is Good TRC?
1. High Compaction Ratio (CR)
Original Data Volume
CR
Compacted Data Volume
2. Low Aliasing
number of faulty outputs that generate gold signature
PAL
total number of faulty outputs
Test Response Compactor (TRC)
space
CUT time
Space compaction Time compaction
reduces output pins reduces output length
110
010 010 110010 0
100 100 010101 1
010 001
001
5 6
Compaction Ratio Compaction Ratio
3 1
Test Compression
Introduction
Hardware Techniques
Test Stimulus Compression
Test Response Compaction
CUT
Space Compaction
X-compact
Time Compaction
MISR
Other X-handling techniques
X-blocking
X-masking
Single XOR-Tree
1. High CR CR # CUT outputs
2. Bad PAL
1
Detects odd number of errors, not even PAL
2
CUT
X-compact
Multiple XOR trees can detect errors in presence of X
Example
Scan chain (SC) 6 produces unknown ‘X’
The other 7 scan chains are not contaminated
X X X
Test Compression
Introduction
Hardware Techniques
Test Stimulus Compression
Test Response Compaction
CUT
Space Compaction
X-compact
Time Compaction
MISR
Review: MISR
MISR (multiple input signature register) is similar to LFSR
except parallel inputs feed XOR between stages
Right bit first
010110 010111 010110 011011
+ Q0 + Q1 + Q2 + Q3
f(x) = 1+x3+x4
MISR
011011
010110
010111
+ 010110
011011011 + Q0 Q1 Q2 + Q3
Equivalent LFSR M(x)=x+x2+x4+x5+x7+x8
CR=? Aliasing=?
MISR degree = N, input bit sequence length = m
Signature is N bits
Original Data N m
CR m PAL 2 N (see 14.3)
Compacted Data N
m-bit sequence
...010110 ...010111 ...010110 ...011011
+ Q0 + Q1 + Q2 + Q3
MISR has High CR and Low PAL
Q: What is signature if one bit is changed to X ‘unknown’ ?
ANS:
010110 010111 010110 X
011011
+ Q0 + Q1 + Q2 + Q3
MISR is NOT X-tolerant
Test Compression
Hardware Techniques
Test Stimulus Compression
Test Response Compaction
CUT
Space Compaction
X-compact
Time Compaction
MISR
Other X-handling techniques
X-blocking
X-masking
X-blocking (or X-bounding)
Add extra DFT inside CUT to block X before reaching compactor
Area overhead and extra delay
X source can be
non-scan FF, memory, multi-cycle paths, false paths*…
CUT
*multi-cycle paths needs more than 1 cycle to finish computation so test responses can be X
*false paths are not activated by normal operation so test responses can be X
X-masking
Add extra mask between CUT and compactor
Example: mask outputs by OR gates
1 = mask
0 = pass through
mask
X 1
1
CUT X 1
1
0 0
0
control
signal
Summary
Test Response Compaction
Space Compaction
XOR-tree, X-compact
CUT
Time Compaction
MISR
High CR, Low PAL
Cannot tolerate X
X-bounding, X-masking
Can mask many X
X-Masking + MISR/XOR-tree
is Most Popular Solution