DIGITAL CONTROL SYSTEM

(CONTROLLER REALIZATION)
[Link]. Satit mangkalajan ([Link].)
 CONTROLLER REALIZATION
A control algorithm which takes the form of a z-transform polynomial must be realized in the
computer in the form of a program containing unit delays, constant multipliers, and adders. A given
controller transfer function can be realized in many different ways. Mathematically the alternative
realizations are all equivalent, differing only in the way they are implemented. Different realizations
have different computational efficiencies, different sensitivities to parameter errors, and different
programming efforts are needed in each case. Only some of the important realizations, such as the
direct structure, cascaded structure and parallel structure, as well as the second-order structures, are
described in this chapter.
➢ Direct structure
➢ Cascaded structure
➢ Parallel structure
Digital Control System 2/2567
Next Slide
 DIRECT STRUCTURE
The transfer function D(z) of a digital controller can be represented in general by a ratio of two
polynomials
n

U ( z)
a z j
−j

D( z ) = = j =0
n
(1)
1 +  bj z− j
E( z)
j =1

In direct structure the coefficients aj and bj appear as multipliers. There are several forms of direct
structure, and we shall look at two of the most popular ones: the direct canonical structure and the
direct noncanonical structure.

Digital Control System 2/2567

Next Slide
 DIRECT CANONICAL STRUCTURE (DIRECT FORM II)
n

U ( z)
a z j
−j

Remembering that b 0 = 1, we can rewrite (1) as D( z ) = = j =0

n
(2)
1 +  bj z− j
E( z)
j =0
n

U ( z ) R( z )
a z j
−j

Let us now introduce a variable R(z) such that = j =0

n
(3)
b z
R( z ) E ( z ) −j
j
j =0

where U ( z) n
=  a j z− j (4)
R ( z ) j =0
E( z) n
and =  bj z− j (5)
R ( z ) j =0

Digital Control System 2/2567

Next Slide
 DIRECT CANONICAL (DIRECT FORM II) (CONT’D)
n
Assume that the transfer function of a digital controller is R( z ) = E ( z ) −  b j z − j R( z ) (6)
j =1
n
We can rewrite (4) as U ( z ) =  a j z − j R( z ) (7)
j =0
n
Equations (6) and (7) can be written in the time domain as rk = ek −  b j rk − j (8)
j =1
n
and uk =  a j rk − j (9)
j =0

Equations (8) and (9) define the direct form, and the block diagram of the implementation is shown
in Figure 1. The controller is made up of delays, adders and multipliers.

Digital Control System 2/2567

Next Slide
 DIRECT CANONICAL (DIRECT FORM II) (CONT’D)

n
uk =  a j rk − j
n j =0
rk = ek −  b j rk − j
j =1

Figure 1 Canonical direct structure

Digital Control System 2/2567
Next Slide
 SUMMARY OF DIRECT CANONICAL (DIRECT FORM II)
A canonical structure is a realization that uses the minimum number of delay elements
necessary to implement the system. It is also called the minimum realization form.

❖ Key Feature: Uses the fewest number of memory elements (delay registers).
❖ Example: Direct Form II is a canonical structure because it reduces redundant delays.
❖ Advantage: Saves memory, making it efficient for microcontrollers and DSPs.
❖ Disadvantage: More sensitive to numerical precision errors in fixed-point implementations.

Figure 1 Canonical direct structure

Digital Control System 2/2567
Next Slide
 EXAMPLE 1.1
1 + 2 z −1 + 4 z −2
The transfer function of a digital controller is found to be D( z ) =
1 + 2 z −1 + 5 z −2
Draw the block diagram of the direct canonical realization of this controller.

Solution
With reference to (8), (9) and Figure 1, we can
draw the required block diagram as in Figure 2.

Figure 2 Block diagram for Example 1.1

Digital Control System 2/2567
Next Slide
 DIRECT NONCANONICAL STRUCTURE (DIRECT FORM I)
n

U ( z)
a z j
−j

Consider Equation (2) with b0 = 1: D( z ) = = j =0

n

b z
E( z) −j
j
j =0

n n
Cross multiplying and rewriting this equation we obtain U ( z ) b j z −j
= E ( z ) a j z − j (10)
j =0 j =0

n n
or, since b 0 = 1, U ( z ) =  a j z E ( z ) −  b j z − jU ( z )
−j
(11)
j =0 j =1

Writing (11) in the time domain, we obtain the noncanonical form of the direct realization
n n
uk =  a j ek − j −  b j uk − j
j =0 j =1 (12)
Digital Control System 2/2567
Next Slide
 DIRECT NONCANONICAL STRUCTURE (DIRECT FORM I)
n

U ( z)
a z j
−j

Consider Equation (2) with b0 = 1: D( z ) = = j =0

n

b z
E( z) −j
j
j =0

n n
Cross multiplying and rewriting this equation we obtain U ( z ) b j z −j
= E ( z ) a j z − j (10)
j =0 j =0

n n
or, since b 0 = 1, U ( z ) =  a j z E ( z ) −  b j z − jU ( z )
−j
(11)
j =0 j =1

Writing (11) in the time domain, we obtain the noncanonical form of the direct realization
n n
uk =  a j ek − j −  b j uk − j (12)
j =0 j =1

Digital Control System 2/2567

Next Slide
DIRECT NONCANONICAL STRUCTURE (DIRECT FORM I)

n n
uk =  a j ek − j −  b j uk − j
j =0 j =1

Figure 3 Noncanonical direct structure

Digital Control System 2/2567
Next Slide
 EXAMPLE 1.2
1 + 2 z −1 + 4 z −2
The transfer function of a digital controller is found to be D( z ) =
1 + 2 z −1 + 5 z −2
Draw the block diagram of the direct canonical realization of this controller.

Solution
With reference to (12) and Figure 3, we can
draw the required block diagram as in Figure 4.

Figure 4 Block diagram for Example 10.1

Digital Control System 2/2567
Next Slide
 SUMMARY OF DIRECT NONCANONICAL (DIRECT FORM I)
A non-canonical structure uses more delay elements than the minimum required for
implementation.

❖ Key Feature: Contains redundant delays.

❖ Example: Direct Form I is a non-canonical structure because it uses separate delay elements
for the numerator and denominator.
❖ Advantage: Often numerically more stable in fixed-point systems.
❖ Disadvantage: Uses more memory, which is inefficient in embedded systems.

Digital Control System 2/2567

Next Slide
 COMPARISON DIRECT FORM I AND DIRECT FORM II
Feature Non-Canonical Canonical
(Direct Form I) (Direct Form II)

Numerical Stability More stable More sensitive

Memory Usage Higher (redundant delays) Minimal (efficient)

Implementation Complexity Easier Slightly higher

Common Use Floating-point systems Microcontrollers, DSPs

➢ Use canonical form (Direct Form II) when memory efficiency is a priority (e.g., Arduino DUE,
DSP, or real-time systems).
➢ Use non-canonical form (Direct Form I) when numerical stability is more important (e.g.,
floating-point processors).
Digital Control System 2/2567
Next Slide
 CASCADE REALIZATION
The cascade realization is less sensitive to coefficient sensitivity problems. In this method the
transfer function is implemented as a product of first-order and second-order transfer functions.
Thus, the controller transfer function is written as
m
D ( z ) = P ( z ) Qi ( z ) For n odd (13)
i =1

and m
D ( z ) =  Qi ( z ) For n even (14)
i =1

where m is the smallest integer greater than or equal to n/2. P(z) in (13) is the first-order transfer
function
1 +  z −1
P( z ) = (15)
1+  z−1

Digital Control System 2/2567

Next Slide
 CASCADE REALIZATION (CONT'D)
The cascade realization is less sensitive to coefficient sensitivity problems. In this method the
transfer function is implemented as a product of first-order and second-order transfer functions.
Thus, the controller transfer function is written as
m
D ( z ) = P ( z ) Qi ( z ) For n odd (13)
i =1
and
m
D ( z ) =  Qi ( z ) For n even (14)
i =1 Figure 5 Realization of P(z)
where m is the smallest integer greater than or With reference to Figure 5, we can write
equal to n/2. P(z) in (13) is the first-order
rk = ek −  rk −1 (16)
transfer function shown in Figure 5. and
1 +  z −1 uk = rk +  rk −1 (17)
P( z ) = (15)
1+  z −1
Next Slide
Digital Control System 2/2567
 CASCADE REALIZATION (CONT'D)
In practice, in order to avoid coefficient sensitivity problems
Q(z) in equation (13) and (14) is a second-order transfer
second-order transfer function modules of the form given by
function, shown in Figure 6.
a0 + a1 z −1 + a2 z −2
(18) are frequently used and the modules are cascaded to
Q( z ) = (18) give the required order as shown in Figure 7.
1 + b1 z −1 + b2 z −2

Figure 6 Realization of Q(z)

With reference to Figure 6, we can write
rk = ek − b1rk −1 − b2 rk −2 (19) Figure 7 Realization of Q(z) drawn vertically
uk = a0 rk + a1rk −1 + a2 rk −2 (20) Next Slide
Digital Control System 2/2567
 PARALLEL REALIZATION (FIRST-ORDER)
The parallel realization also avoids the coefficient sensitivity problem. In this method the transfer function is factored and written
as a sum of first-order and second-order transfer functions:
D ( z ) =  0 + D1 ( z ) + D2 ( z ) + + Dm ( z ), 1 m  n
 (21)
First-order transfer functions are of the form D1 ( z ) =
1+  z −1

Figure 8 First-order element for parallel realization

as shown in Figure 8. With reference to this figure, we can write rk = ek −  rk −1 (22)
uk =  rk (23) Next Slide
Digital Control System 2/2567
 PARALLEL REALIZATION (SECOND-ORDER)
Second-order transfer functions are of the form a1 + a2 z −1
D2 ( z ) = (24)
1 + b1 z −1 + b2 z −2

Figure 9 Second-order element for parallel realization

as shown in Figure 9. With reference to this figure, we can write
rk = ek − b1rk −1 − b2 rk −2 (25) uk = a0 rk + a1rk −1 + rk −2 (26)

Digital Control System 2/2567

Next Slide
 COMPARISON WITH OTHER REALIZATIONS
Feature Direct Form Realization Cascade Realization Parallel Realization
Lower (prone to coefficient
Numerical Stability More sensitive High (independent small systems)
errors)
Implementation Complexity Simple More structured Moderate
Simple but not optimal for Requires sequential Can be efficient in parallel
Computational Efficiency
high-order systems computation hardware
Decomposed systems (from
Low-order systems, simple High-order systems with
Best for Partial Fraction Expansion, PFE),
implementations stability concerns
parallel hardware
Implementation in DSPs and More stable for high-order Best suited for parallel processing
Efficient for small systems
Microcontrollers filters and controllers in high-performance DSPs

Digital Control System 2/2567

Next Slide
 CHOOSING THE RIGHT REALIZATION
System Requirement Best Realization
Simple, low-order controller Direct Form I
Memory-efficient implementation (e.g., microcontrollers) Direct Form II
High-order filter or controller with better stability Cascade
Digital control system using Partial Fraction Expansion Parallel
DSP-based system with parallel processing capabilities Parallel
FPGA-based implementation with pipelining Parallel or Cascade

Digital Control System 2/2567

Next Slide
 PID CONTROLLER IMPLEMENTATIONS
PID controllers are very important in many process control applications. In this section we shall look at the realization of this type
of controller. The z-transform of the PID controller was derived and is reproduced here for convenience:
K pT K pTd (1 − z −1 )
D( z ) = K p + −1
+ (27)
Ti (1 − z ) T
As shown in Figure 10.13, this transfer function may be implemented
as a parallel structure by summing the proportional, integral and
derivative [Link] reference to Figure 10.13 we can write the
following difference equations: for the proportional section,
For the proportional section,
wk = K p * ek (28)
For the integral section,
pk =  ek + pk −1 (29)
And for the derivative section, Figure 10 PID controller as a parallel structure
qk =  (ek − ek −1 ) (30) Digital Control System 2/2567
Next Slide
 PID CONTROLLER IMPLEMENTATIONS
The output is given by uk = wk + pk + qk (31)
An alternative implementation of the PID would be to find a second order transfer function for (27) and then use the direct
structure to implement it. Equation (27) can be written as
K p (1 − z −1 ) + ( K pT / Ti ) + ( K pTd / T )(1 − z −1 ) 2
D( z ) =
1 − z −1
K p − K p z −1 + ( K pT / Ti ) + ( K pTd / T ) + ( K pTd / T ) z −2 − 2( K pTd / T ) z −1
=
1 − z −1
K p + ( K pT / Ti ) + ( K pTd / T ) − ( K p + 2 K pTd / T ) z −1 + ( K pTd / T ) z −2
=
1 − z −1
which is in the form where a0 = K p (1 + T / Ti + Td / T ) a1 = − K p (1 + 2Td / T ) a2 = K pTd / T

a0 + a1 z −1 + a2 z −2 b1 = −1 b2 = 0
(32)
1 + b1 z −1 + b2 z −2

Digital Control System 2/2567

Next Slide
 PID CONTROLLER IMPLEMENTATIONS
Figure 14 shows the implementation of the PID controller as a
second-order direct canonical structure. The velocity form of the PID
controller is used frequently in practice and the difference equation
for this controller was derived in Chapter 6. Considering this
equation again and replacing kT simply by subscript k, we can write
K pT K pTd
uk = uk −1 + K p [ek − ek −1 ] + ek + [ek − 2ek −1 − ek −2 ] (33)
Ti T
or
 K pT K pTd   2 K pTd  K pTd
uk = uk −1 +  K p + +  ek −  K p +  ek −1 + ek −2
 Ti T   T  T
Figure 11 PID implementation as
Alternatively, we can write this in a simpler form as uk = uk −1 + aek + bek −1 + cek −2 (34) a direct canonical structure
K pT K pTd  2 K pT  K pTd
where a = K p + + b = − K p +  c=
Ti T  Ti  T
Digital Control System 2/2567
Next Slide
 PID CONTROLLER IMPLEMENTATIONS
By taking the z-transform of equation(34), we obtain
U ( z ) = z −1U ( z ) + aE ( z ) + bz −1 E ( z ) + cz −2 E ( z )

U ( z ) a + bz −1 + cz −2
or D( z ) = = (35)
E( z) 1 − z −1

Equation (35) can easily be implemented using a direct realization. Notice that if only proportional
plus integral (PI) action is required, the derivative constant Td can be set to zero and we get the PI
equation D( z ) =
U ( z ) a + bz −1
= (36)
E( z) 1 − z −1
K pT
where a = Kp +
Ti
b = Kp

Equation (36) can easily be implemented as a first-order transfer function.

Digital Control System 2/2567
Next Slide
 MICROCONTROLLER IMPLEMENTATIONS
One of the most common, which has the advantage of
accurate implementation, is the use of a timer interrupt to
generate the required loop delay (or the sampling interval). In
this method the software consists of two parts: the main
program and the interrupt service routine. As shown in Figure
12, in the main program various variables, as well as the A/D
converter and the timer interrupt mechanism, are initialized.
The timer is set to interrupt at an interval equivalent to the
sampling interval of the required digital controller. The main
program then enters a loop waiting for the timer interrupts to
occur. Whenever a timer interrupt occurs the program jumps
the interrupt service routine (ISR). Figure 12 Controller implementation

Digital Control System 2/2567

Next Slide
 IMPLEMENTING FIRST-ORDER MODULES
The first-order module can be realized using adders, multipliers
and delay elements. The first-order module is shown in Figure 13.
The difference equations describing a first-order module were
found to be rk = ek − b1rk −1

and uk = a0ek + a1rk −1

If we let M 1 = −b1rk −1 and M 2 = a1rk −1

then the difference equations for the first-order

module becomes rk = ek + M 1 uk = a0 ek + M 2 Figure 13 First-order module
The implementation of the first-order module is similar to the second-order module and an
example is given next slide. Next Slide
Digital Control System 2/2567
 EXAMPLE 1.3
Assume that the digital controller to be implemented is in
the form of a first-order module, and write a program in C
to implement this controller. The controller parameters
are assumed to be: a0 = 1, a1 = 0.8, b1 = 1.85, i.e. the
required controller transfer function is
1 + 0.8 z −1
D( z ) =
1 + 1.85 z −1

Also assume that the required sampling interval is

T = 0.01 s.

Digital Control System 2/2567

Next Slide
 IMPLEMENTING SECOND-ORDER MODULES
we saw how a second-order module can be realized using adders, multipliers and delay elements.
The second-order module is shown in Figure 14. The difference equations describing such a module
are (19) and (20). If we let
M 1 = −b1rk −1 − b2 rk −2 and M 2 = a1rk −1 + a2 rk −2

then the difference equations for the second-order

module become
rk = ek + M 1 and uk = a0 rk + M 2
The implementation of the second-order module is shown as
a flow-chart in Figure 10.17. This figure does not show the
initialization of the variables T1 , T2 , r1 , r2 , the A/D Figure 14 Second-order module
initialization, the I/O port initialization, etc.; it only shows the
interrupt service routine. Digital Control System 2/2567
Next Slide
 EXAMPLE 1.4
Assume that the digital controller to be
implemented is in the form of a second-order
module, and write a program in C to implement
this controller. The controller parameters are
assumed to be a0 = 1, a1 = 0.8, a2 = 1.2, b1 =
1.85, b2 = 0.92. Also assume that the required
sampling interval is T = 0.01 s.
1 + 0.8 z −1 + 1.2 z −2
D( z ) =
1 + 1.85 z −1 + 0.92 z −2

Digital Control System 2/2567

Next Slide
 IMPLEMENTING HIGHER-ORDER MODULES
Higher-order controllers can be implemented by
cascading first-order and second-order modules.
For example, a fourth-order controller can be
implemented by cascading two second-order
modules, as shown in Figure 15.

second-order module #1

second-order module #2

Figure 15 Implementing a fourth-order module

Digital Control System 2/2567
Next Slide
 CHOICE OF SAMPLING INTERVAL
Various empirical rules have been suggested by many researchers for the selection of the sampling
interval. These rules are based on practical experience and simulation results. Among them are the
following
➢ If the plant has the dominant time constant T p , then the sampling interval T for the closed
loop system should be selected such that T < Tp/10.
➢ Assuming that the process has a Ziegler–Nichols open-loop model then the sampling interval
should be selected such that T < T1/4. G ( s) = e− sT 1

1 + sT2

➢ If the closed-loop system is required to have a settling time T ss or a natural frequency of ω n

then choose the sampling interval T such that T < Tss/10 and ωs > 10ωn , where ω s is the
sampling frequency, i.e. ωs = 2π/T .
Digital Control System 2/2567
Next Slide
 DIGITAL FILTER APPLICATION

05/03/68
Digital Control System 2/2567
 FIR DIRECT FORM – FINITE IMPULSE RESPONSE FILTER
M
y[ n ]
A general FIR filter is represented by the convolution sum: H ( z ) = =  b[k ]z − k
where: x[n] k =0
y[z] = Output signal, x[z] = Input signal, b[k] = Filter coefficients, M = Order of the FIR filter
In Direct Form, the output is computed by directly applying the filter coefficients to the delayed input
samples. Basic FIR Direct Form Structure: y[n] = b0 x[n] + b1 x[n − 1] + b2 x[n − 2] + + bM x[n − M ]
Uses Delay Elements (z−1) to store past input values.
Each stored input is multiplied by a corresponding coefficient h[k].
The results are summed to produce the output y[n].

05/03/68
Digital Control System 2/2567
 IIR DIRECT FORM – INFINITE IMPULSE RESPONSE FILTER
An IIR (Infinite Impulse Response) filter has both feedforward (FIR-like) and feedback components.
The general equation is:
M N
y[n] =  b[k ]x[n − k ] −  a[ j ] y[n − j ]
k =0 j =1

where:
•y[n] = Output signal
•x[n] = Input signal
•b[k] = Feedforward coefficients (numerator)
•a[j] = Feedback coefficients (denominator)
•M = Order of the feedforward section
•N = Order of the feedback section
05/03/68
Digital Control System 2/2567
Question & Answer
Digital Control System 2/2567
Thank You
Digital Control System 2/2567