Journal of Network Communications and Emerging Technologies (JNCET) [Link].

org
Volume 6, Issue 12, December (2016)

Design and Implementation of D Flip-Flops for

maximum Performance VLSI using 180nm CMOS
Technology
Priyanka Tripathi
M. Tech. student Dept. of ECE, S.R.I.T, RGPV, Jabalpur, India.

Divyanshu Rao
ECE dept. S.R.I.T., RGPV, Jabalpur, India.

Ravi Mohan
HOD ECE Dept. S.R.I.T., RGPV, Jabalpur, India.

Abstract – This paper presents low power master slave d Flip- total number of states is called its modulus. Thus if a counter
Flop. As these flip flop topologies have little area and low power has „m‟ distinct states, then it is called a modulus-m counter or
consumption, they can be used in different applications like digital mod-m counter. The order in which the states appear is referred
VLSI clocking system, buffers, registers, microprocessors etc. The to as its counting sequence.
Flip-Flops are analyzed at 180nm technologies. The above
designed Flip-Flops and Latches are compared in terms of its 2. LITERATURE SURVEY
area, transistor count, and power dissipation. As chip
manufacturing technology is suddenly on the threshold of major This paper enumerates a low power, high speed design of flip-
evaluation, which shrinks chip in size and performance is flop having less number of transistors. In flip-flop design only
implemented in layout level which develops the low power one transistor is being clocked by short pulse train which is
consumption chip using recent CMOS micron layout tools. This known as True Single Phase Clocking (TSPC) flip-flop. The
project proposes low power design of flip flop. true single-phase clock (TSPC) is common dynamic flip-flop
Index Terms – Counter, Master Slave D flip-flop, DSCH, which performs the flip-flop operation with little power and at
MicroWind. high speeds. In this paper, an extensive comparison of existing
designs of positive edge triggered True Single Phase Clocking
1. INTRODUCTION Flip-flop is carried out. As True Single Phase Clocking (TSPC)
Counting is a fundamental function of digital circuits. A digital flip-flop design has small area and low power consumption.
counter consists of a collection of flip-flops that change state And it can be used in various applications like digital VLSI
(set or reset) in a prescribed sequence. The primary function of clocking system, microprocessors, buffers etc. The analysis for
a counter is to produce a specified output pattern sequence. For various flip-flops for power dissipation and propagation delay
this reason, it is also a pattern generator. This pattern sequence has been carried out at different foundries. The designed flip-
might correspond to the number of occurrences of an event or flops are compared in terms of power consumption and
it might be used to control various portions of a digital system. propagation delay and power delay product using DSCH and
In this latter case each pattern is associated with a distinct MICROWIND tools.
operation that the digital system must perform. There are 3. THE PROPOSED COUNTER
tremendous applications of a counter in the digital consumer
electronics market. A counter can play a vital role in several Master-Slave D Flip-Flop:
circuits ranging from a simple display to complex
A master-slave D flip-flop is created by connecting two gated
microcontroller circuits. Some of the apparent applications of
D latches in series and inverting the enable input to one of
a counter are: frequency divider in phase-locked loops,
them. It is called master-slave because the second (slave) latch
frequency synthesizers, signal generation and processing
in the series only changes in response to a change in the first
circuits, microcontrollers, digital memories and in digital clock
(master) latch. The term pulse-triggered means that data is
and timing circuits. A counter is another example of a register
entered on the rising edge of the clock pulse, but the output
as in the case of a register each of the 0-1 combinations that are
does not reflect the change until the falling edge of the clock
stored in the collection of flip-flops that comprise the counter,
pulse. Master-slave flip-flops can be constructed to behave as
that is the output pattern, is known as a state of the counter. The

ISSN: 2395-5317 ©EverScience Publications 11

Journal of Network Communications and Emerging Technologies (JNCET) [Link]
Volume 6, Issue 12, December (2016)

a J-K, R-S, T or D flip-flop. The purpose of master-slave flip- A set of CMOS processes ranging from 1.2µm down to state-
flops is to protect a flip-flop’s output from inadvertent changes of-the-art 0.25µm are proposed.
caused by glitches on the input. Master-slave flip-flops are used
To use the MICROWIND program use the following
in applications where glitches may be prevalent on inputs. The
procedure:
master-slave configuration has the advantage of being pulse-
triggered, making it easier to use in larger circuits, since the  Go to the directory in which the software has been
inputs to a flip-flop often depend on the state of its output. copied
(The default directory is MICROWIND)
 Double-click on the Microwind icon
The MICROWIND display window is shown in Figure 1. It
includes four main windows: the main menu, the layout
Fig-1: Master-slave D flip-flop displays window, the icon menu and the layer palette. The
cursor appears in the middle of the layout window and is
Fig.1 shows negative pulse-triggered master-slave D flip-flop. controlled by using the mouse.
It responds on the negative edge of the enable input (usually a
clock). The circuit consists of two D flip-flops connected The layout window features a grid that represents the current
together. When the clock is high, the D input is stored in the scale of the drawing, scaled in lambda units and in micron.
first latch, but the second latch cannot change state. When the The lambda unit is fixed to half of the minimum available
clock is low, the first latch's output is stored in the second latch, lithography of the technology. The default technology is a 0.8
but the first latch cannot change state. The result is that output µm technology, consequently lambda is 0.4 µm.
can only change state when the clock makes a transition from
high to low. 5. SCHEMATIC

4. SOFTWARE –MICROWIND Schematic of rising edge DFF:

The present experiment is a guide to using the « Microwind »

educational software on a PC computer. The MICROWIND
program allows the student to design and simulate an integrated
circuit. The package itself contains a library of common logic
and analog ICs to view and simulate. MICROWIND includes
all the commands for a mask editor as well as new original tools
never gathered before in a single module. You can gain access
to Circuit Simulation by pressing one single key. The electric
extraction of your circuit is automatically performed and the
analog simulator produces voltage and current curves
immediately.
A specific command displays the characteristics of pMOS and
nMOS, where the size of the device and the process parameters
can be very easily changed. Altering the MOS model
parameters and, then, seeing the effects on the Vds and Ids Schematic of falling edge DFF:
curves constitutes a good interactive tutorial on devices.
The Process Simulator shows the layout in a vertical
perspective, as when fabrication has been completed. This
feature is a significant aid to supplement the descriptions of
fabrication found in most textbooks.
The Logic Cell Compiler is a particularly sophisticated tool
enabling the automatic design of a CMOS circuit
corresponding to your logic description in VERILOG. The
DSCH software, which is a user-friendly schematic editor and
a logic simulator presented in a companion manual, is used to
generate this Verilog description. The cell is created in
compliance with the environment, design rules and
fabrication specifications.

ISSN: 2395-5317 ©EverScience Publications 12

Journal of Network Communications and Emerging Technologies (JNCET) [Link]
Volume 6, Issue 12, December (2016)

Layout of rising edge DFF Simulation result of falling edge DFF:

7. CONCLUSIONS

Layout of falling edge DFF: In this paper, master slave d flip flop has been implemented.
We also simulated and analyzed the master slave d flip flop.
The performance of the D flip flop is analyzed in terms of area
and power consumption. The main objective to minimize the
power consumption. The logic and output of the master-slave
D flip-flop are easily confirmed with the simulation results.
Thus we present the design and implementation of master slave
d flips flop which is having less area.
REFERENCES
[1] “Design and Analysis of Low Power Pulse Triggered Flip-Flop” by
[Link] priya, [Link] International Journal of
Scientific and Research Publications, Volume 3, Issue 4, April 2013 1
ISSN 2250-3153
[2] “A New Family of Semidynamic and Dynamic Flip-Flops with
Embedded Logic for High-Performance Processors” by Fabian
Klass, Chaim Amir, Ashutosh Das, Kathirgamar Aingaran, Cindy
Truong, Richard Wang, Anup Mehta, Ray Heald, and Gin Yee IEEE
JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 5, MAY
6. SIMULATION RESULTS 1999
[3] “Comparative Analysis of Master–Slave Latches and Flip-
Simulation result of rising edge DFF: Flops for High-Performance and Low-Power Systems “ by
adimir Stojanovic and Vojin G. Oklobdzija, Fellow, IEEE IEEE
JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 4, APRIL
1999
[4] “Design and analysis of flip flops for low power clocking system”
International Conference on Engineering Trends and Science &
Humanities (ICETSH-2015) Gabariyala sabadini.C Jeya
priyanka.P
[5] “Power Efficient Design Of Counter” On .12 Micron Technology Simmy
Hirkaney, Sandip Nemade, Vikash Gupta International Journal of Soft
Computing and Engineering (IJSCE) ISSN: 2231-2307, Volume-1,
Issue-1, March 2011
[6] “Design of Flip-Flops for High Performance VLSI Applications using
Deep Submicron CMOS Technology” Rishikesh V. Tambat and Sonal
A. Lakhotiya

ISSN: 2395-5317 ©EverScience Publications 13