Report Problem 1
For the following code snippets, draw the conceptual circuit diagram of each
code that it represents and explain the difference.
Solution:
For Code snippet 1:
The provided Verilog code describes a simple sequential circuit with two D flip-flops. This circuit
essentially delays the input signal by one clock cycle. When the clock signal rises, the input value
is captured by the first flip-flop. On the next rising edge, the value from the first flip-flop is
captured by the second flip-flop. Thus, the output is delayed by one clock cycle compared to the
input. This simple delay circuit can be used in various digital systems, such as synchronization,
data pipelining, and timing generation.
Circuit Diagram:
Fig: Conceptual Circuit Diagram for Code snippet 1
For Code snippet 2:
The provided Verilog code describes a simple sequential circuit with two D flip-flops. This circuit
essentially delays the input signal by one clock cycle. When the clock signal rises, the input value
is captured by the first flip-flop. On the next rising edge, the value from the first flip-flop is
captured by the second flip-flop. Thus, the output is delayed by one clock cycle compared to the
input. This simple delay circuit can be used in various digital systems, such as synchronization,
data pipelining, and timing generation.
However, there is a crucial difference between this code and the previous one: the use of blocking
assignments (=) instead of non-blocking assignments (<=). This change can lead to unexpected
behavior in sequential circuits, as it can cause race conditions and incorrect output values. In this
specific case, the output out may not be updated correctly on the first clock cycle, as the
assignments to q1 and q2 may be executed sequentially instead of concurrently.
Fig: Conceptual Circuit Diagram for Code snippet 2
Discussion:
The Verilog code describes a simple delay circuit using two D flip-flops, which delays the input
signal by one clock cycle. This type of circuit is useful in applications like data synchronization
and pipelining.
However, a crucial issue arises from using blocking assignments (`=`) instead of non-blocking
assignments (`<=`). Blocking assignments execute sequentially, which can cause race conditions
and incorrect timing behavior in sequential circuits. This can prevent the output from updating
correctly, as the values of intermediate signals (`q1` and `q2`) may not synchronize as expected.
To avoid this, non-blocking assignments should be used in sequential circuits triggered by the
clock. Non-blocking assignments ensure concurrent updates and reliable timing, which is essential
for predictable and accurate circuit behavior.
Report Problem 4
Write Verilog code that will divide the input clock frequency by a factor of 16.
Solution:
To create a clock divider that reduces the input clock frequency by a factor of 16, we can utilize a
synchronous counter. This counter increments its value on each rising edge of the input clock
signal. When the counter reaches a specific value, typically 15, the output clock signal is toggled,
and the counter resets to 0. This process effectively divides the input clock frequency by 16. We
can implement this logic using Verilog, a hardware description language, by defining a module
with an input clock and an output clock, and then designing a sequential circuit to control the
counter and output clock generation.
Code:
Fig: Verilog code for clock divider
Timing Diagram:
Fig: Timing Diagram for Clock Divider
Discussion:
To solve the problem of dividing the input clock frequency by a factor of 16, a sequential approach
using a counter was implemented in Verilog. A 4-bit counter (`counter`) was used to count the
number of clock cycles of the input clock (`clk_in`). Since a 4-bit counter can hold values from 0
to 15, it was designed to increment on each rising edge of `clk_in`. When the counter reaches a
value of 15, it resets to 0, effectively creating a cycle of 16 input clock pulses.
Each time the counter resets, the output clock signal (`clk_out`) toggles its state (from 0 to 1 or 1
to 0). This toggling divides the input clock frequency by 16, as the output clock only changes state
once every 16 input cycles. This simple approach ensures that the output clock frequency is
reduced without additional complex logic, providing an effective frequency divider. The result is
a clean, consistent output frequency at one-sixteenth the rate of the original clock, ideal for
applications that require a slower clock signal derived from a high-speed input clock.
Report Problem 5
Propose a digital scheme which will detect the number of 1’s in a 4-bit number
and it will do end around left shift total number of 1s’ times. e. g. If the number
is 0101, it will do end around left shift twice. If it is 1011, it will end around left
shift thrice. This is NOT a Verilog problem. You will have to draw logic circuit.
Solution:
1. Define the Input and Output Variables:
• The input is a 4-bit binary number represented by bits A, B, C, and D.
• The goal is to count how many bits are set to 1 in this input (i.e., the "number of 1s").
2. Define One-Hot Encoded Variables:
• Since the count of 1s in a 4-bit binary number can range from 0 to 4, five variables
are defined: Y0, Y1, Y2, Y3, and Y4.
• Each of these variables represents a possible count of 1s in a one-hot encoded format.
For instance, if there are exactly two 1s in the input, then Y2 will be set to 1, while all
other Yi variables will be 0.
3. Count the 1s:
• The circuit logic evaluates each bit in the 4-bit input to determine the total number of
1s. This can be achieved by summing up the bits using a series of logic gates.
• Based on the count, the corresponding one-hot encoded variable (Y0 to Y4) will be
activated.
4. Perform Shifting Based on the Count:
• Once the count of 1s is identified, the circuit can use this value to control the number
of end-around left shifts.
• An end-around shift takes the leftmost bit and moves it to the rightmost position. This
operation is repeated as many times as there are 1s in the input.
Fig: Functional Block Diagram