Chapter 5: Basic computer
Organization and design
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Basic computer Organization and
design
• Instruction Code
• Computer Register
• Computer Instructions
• Timing and control
• Memory reference Instruction
• Design of basic computer
• design of accumulator Logic
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Instruction Codes
• The internal organization of digital system is defined by
the sequence of microoperations it perform on data
stored in its register.
• The general-purpose digital computer is capable of
executing various microoperations.
• The user of a computer can control the process by means
of program.
• A program is a set of instructions that specify the
operations, data, and the control sequence by which
processing has to occur.
• Computer instruction is binary code that specifies a
sequence of microoperations
• Instruction codes together with data are stored in memory.
• Every computer has its unique instruction set.
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❖ Stored program organization
• The simplest way to organize a computer is to have one
processor register and an instruction code format with 2 parts
(the first specify the operation to be performed and the
second specifies an address).
• The memory address tells the control where to find an
operand in memory.
• Stored program concept:-the ability to store and execute
instructions.
• Stored program concept is the most important property of
general-purpose computer.
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• Instruction code is a group of bits that instruct the computer
to perform a specific operation.
• It has 2 parts:- operation code & immediate operand
❖ Operation code
• is a group of bits that define such operations as add, subtract,
multiply, shift and complement.
• The number of bits required for the operation code of an
instruction depends on the total number of operation
available in the computer.
• It must contain at least n bits for a given 2^n(or less) distinct
operations.
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• The operation part of an instruction code specifies the
operation to be performed.
• This operation must be performed on some data stored in
processor registers or in memory.
• The instruction code must specify not only the operation but
also the registers or the memory words where the operands
are to be found, as well as the registers or memory word
where the result is to be stored.
• Immediate operand :
• the second part of an instruction code(address field) specifies
an operand
• Two types:-direct and indirect
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• One bit of the instruction code is used to distinguish between
a direct and an indirect address.
❖ Direct address operand
• the second part of an instruction code specifies the address of
an operand
❖ Indirect address operand
• the bits in the second part of the instruction designate an
address of a memory word in which the address of the
operand is found (Pointer).
• Effective Address :-The operand address in computation-type
instruction or the target address in a branch-type instruction.
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Program statements and computer
instructions
Computer instruction
Field specifying the Field specifying the data
operation to be executed To be operated on
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Instruction code format
• Instruction code format with two parts : Op. Code + Address
✓ Op. Code : specify 16 possible operations(4 bits)
✓ Address : specify the address of an operand(12 bits)
✓ If an operation in an instruction code does not need an
operand from memory, the rest of the bits in the
instruction(address field) can be used for other purpose
15 12 11 0 15 12 11 0
data
Op. Code Address
instruction Not an instruction
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• Instructions can be formatted to fit in one or more memory
words.
• An instruction may contain
➢ An opcode + data (immediate operand)
➢ An opcode + the address of data (direct addressing)
➢ An opcode + an address where the address of the data is
found (indirect addressing)
➢ Data only (location has no instructions)
➢ An opcode only (register-reference or input/output
instruction)
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Computer Registers
• Computer instructions are normally stored in consecuitive
memory locations and are executed sequentially one at a
time.
• The control reads an instruction from specific address in
memory to executes it and continues by reading the next
instruction in sequence.
• This type of instruction sequencing needs a counter and
register in control unit for storing the instruction code after
it is read from memory.
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List of registers
Register Number of Register name Register function
symbol bits
DR 16 Data register Holds memory operands
AR 12 Address register Holds address for memory
AC 16 Accumulator Processor register
IR 16 Instruction register Holds instruction code
PC 12 Program counter Holds address of instruction
TR 16 Temporary register Holds temporary data
INPR 8 Input register Holds input character
OUTR 8 Output register Holds output character
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❖ Program Counter(PC) :
▪ hold the address of the next instruction to be read from
memory after the current instruction is executed
▪ Instruction words are read and executed in sequence
unless a branch instruction is encountered
▪ A branch instruction calls for a transfer to a
nonconsecutive instruction in the program
▪ The address part of a branch instruction is transferred to
PC to become the address of the next instruction
▪ To read instruction, memory read cycle is initiated, and PC
is incremented by one(next instruction fetch)
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Common Bus System
• The basic computer has eight registers, a memory unit, and a
control unit
• Paths must be provided to transfer information from one
register to another and between memory and registers
• A more efficient scheme for transferring information in a
system with many registers is to use a common bus
• The connection of the registers and memory of the basic
computer to a common bus system.
• The outputs of 8 registers and memory are connected to the
common bus.
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Computer Instruction
• The basic computer has 3 instruction code formats.
• Each format has 16 bits.
• The operation code part of instruction contains 3 bits and the
meaning of the remaining 13 bits depends on the operation
code encountered.
1. Register-reference instruction
Specify an operation on or a test of AC register.
An operand from memory is not needed ,therefore the other 12
bits are used to specify the operation or test to be executed.
15 14 12 11 0
0 1 1 1 Register Operation
Opcode =111,I=0
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2. Input-Output instruction
• Does not need reference to memory and is recognized by
the operation code 111 with 1 in the left most bit of the
instruction.
• The remaining 12 bits are used to specify the type of input
output operation or tested performed.
15 14 12 11 0
1 1 1 1 Opcode =111,I=1
I/O Operation
3. Memory-reference instruction
• Uses 12 bits to specify an address and one bit to specify
the addressing mode I.
• I is equal to 0 for direct address and to 1 for indirect
address.
15 14 12 11 0
I Opcode Address Opcode =000 through 110
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Hex Code
Symbol I=0 I=1 Description
AND 0xxx 8xxx And memory word to AC
ADD 1xxx 9xxx Add memory word to AC
LDA 2xxx Axxx Load memory word to AC
STA 3xxx Bxxx Store content of AC in memory
BUN 4xxx Cxxx Branch unconditionally
BSA 5xxx Dxxx Branch and Save return address
ISZ 6xxx Exxx Increment and skip if zero
CLA 7800 Clear AC
CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instruction if AC positive
SNA 7008 Skip next instruction if AC negative
SZA 7004 Skip next instruction if AC zero
SZE 7002 Skip next instruction if E is 0
HLT 7001 Halt computer
INP F800 Input character to AC
OUT F400 Output character from AC
SKI F200 Skip on input flag
SKO F100 Skip on output flag
ION F080 Interrup
IOF F040 Inter
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Instruction set completeness
• The set of instruction found in computer are said to be
complete if the computer includes a sufficient number of
instructions in each of the following categories:-
1. Arithmetic, logical, and shift instructions:-provide
computational capabilities for processing the type of data
that the user may wish to employ.
2. Instructions for moving information to and from memory and
processor registers
3. Program control instructions together with instructions that
check status conditions.
4. Input and output instructions for communication between
computer and user.
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Timing and control
• Clock pulses
• A master clock generator controls the timing for all registers
in the basic computer.
• The clock pulses are applied to all flip-flops and registers in
the control unit.
• The clock pulses do not change the state of a register unless
the register is enabled by a control signal
• The control signals are generated in the control unit.
• The control signals provide control inputs for the multiplexers
in the common bus, control inputs in processor registers, and
microoperations for the accumulator.
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• Two major types of control organization z Hardwired Control
and microprogrammed control.
❖ Hardwired control
• The control logic is implemented with gates, F/Fs, decoders,
and other digital circuits
• Fast mode of operation
• Require changes in wiring (if the design has to be modified)
❖ Microprogrammed Control
• The control information is stored in a control memory.
• The control memory is programmed to initiate the required
sequence of microoperations.
• Any required change can be done by updating the
microprogram in control memory.
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❖ Control unit
• It consist two decoders, a sequence counter, and a
number of control logic gates.
• An instruction read from memory is placed in the
instruction register.
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Instruction Cycle
• A computer goes through the following instruction
cycle:-
1. Fetch an instruction from memory
2. Decode the instruction
3. Read the effective address from memory if the
instruction has an indirect address
4. Execute the instruction until a HALT instruction is
encountered
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Instruction fetch
• Initially, the program counter pc is loaded with the address of
the first instruction in the program.
• The sequence counter SC is cleared to 0,providing a decoded
timing signal T0.
• After each clock pulse, SC is incremented by one, so that the
timing signals go through a sequence T0,T1,T2 and so on.
• T0=AR PC
• T1=IR M[AR], PC PC+1
• T2=D0…,D2 Decode IR(12-14), AR IR(0-11), I IR(15)
• Decoding at T2: The operation code in IR is decoded; the
indirect bit is transferred to I; the address part of the
instruction is transferred to AR.
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• T0 = 1
1) Place the content of PC onto the bus by making the bus
selection inputs S2S1S0=010.
2) Transfer the content of the bus to AR by enabling the LD input
of AR.
• T1 = 1
1) Enable the read input memory
2) Place the content of memory onto the bus by making S2S1S0=
111
3) Transfer the content of the bus to IR by enable the LD input of
IR
4) Increment PC by enabling the INR input of PC
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Instruction and Interrupt cycles
Interrupt Cycle
Instruction cycle
Interrupts Enabled
Interrupts Disabled
Fetch, decode
Execute Interrupt
START Next
Instruction Instruction cycle
HALT
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Instruction Cycle
• At T3, microoperations which take place depend on the type
of instruction. The four different paths are symbolized as
follows,
Control function Microoperation
D7`IT3: AR ¬ M[AR], indirect memory transfer
D7`IT3: Nothing, direct memory transfer
D7I`T3: Execute a register-reference instruction
D7IT3: Execute an I/O instruction
When D7`T3 = 1 (At T3 & IR(12-14) ¹ 111), the execution of
memory-reference instructions takes place with the next timing
variable T4.
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Register Reference Instruction
• Register-reference instructions are recognized by I = 0 and D7 = 1.
•These instructions use bits 0 through 11 of the instruction code to
specify one of 12 instructions.
• Each operation is designated by the presence of 1 in one of the bits
in IR(0-11). Therefore D7I`T3 r = 1 is common to all register-
transfer instructions.
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Memory Reference Instructions
• Opcode (000 - 110) or the decoded output Di (i = 0, ..., 6) are used
to select one memory-reference operation out of 7.
• Since the data stored in memory cannot be processed directly (the
memory unit is not connected to the ALU), the actual execution in
the bus system require a sequence of microoperations.
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AND to AC
• AND to AC: Logical AND operation between AC and the
memory word specified effective address.
• Note that T0-T2 for fetch an instruction; T3 for AR M[AR] if
indirect memory addressing.
• Need 2 more cycles for the AND logical operation since only
DR is connected to ALU.)
• D0T4: DR M[AR]
• D0T5: AC AC ˆ DR, SC 0
❖SC – start counter
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Add to AC and LDA
❖ ADD to AC
• Arithmetic addition operation between AC and the memory
word specified by AR.
• D1T4: DR M[AR]
• D1T5: AC AC + DR, SC 0
❖ Load to AC (LDA)
• Need 2 cycles since AC input is not connected to the bus.
• D2T4: DR M[AR]
• D2T5: AC DR, SC 0
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STA and BUN
❖ Store AC(STA)
• D3T4: M[AR] AC, SC 0
• BUN: Branch unconditionally. Transfers the program to the
instruction specified by AR. (Note that the branch target must
be in AR beforehand.)
• D4T4: PC AR, SC 0
❖ Branch unconditionally(BUN)
• Transfers the program to the instruction specified by AR.
(Note that the branch target must be in AR beforehand.)
• D4T4: PC AR, SC 0
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Branch and save return address
• This instruction is useful for branching to a position of the
program called a subprogram
• BSA: Branch and save return address. Branch to address AR
and save PC address.
• BSA is used to implement a subroutine call. The indirect BUN
instruction at the end of the subroutine performs the
subroutine return.
• Note that the above microoperations require 2 cycles.
• D5T4: M[AR] PC, AR AR + 1 (increment, INR AR)
• D5T5: PC AR, SC 0
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Increment and skip if zero(ISZ)
• Programmer usually stores a negative number in the memory
word (in two’s complement form).
• As this negative number is repeatedly incremented by one, it
eventually reaches zero. At that time PC is incremented by
one in order to skip the next instruction.
• increment: M[AR] M[AR] + 1, if (M[AR] + 1 = 0) then PC
PC + 1
• increment and skip if zero requires 3 cycles.
✓ D6T4: DR M[AR]
✓ D6T5: DR DR + 1
✓ D6T6: M[AR] DR, if DR=0 then PC PC + 1, SC 0
• • The ISZ instructions is used to implement a loop.
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Input-Output and Interrupt
❖ Input Register(INPR), Output Register(OUTR)
• These two registers communicate with a communication
interface serially and with the AC in parallel
• Each quantity of information has eight bits of an
alphanumeric code
❖ Input Flag(FGI), Output Flag(FGO)
• FGI : set when INPR is ready, clear when INPR is empty
• FGO : set when operation is complete, clear when output
device is in the process of printing
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Interrupt Cycle
❖ During the execute phase, IEN(interrupt enable) is checked by
the control
• IEN = 0 : the programmer does not want to use the interrupt,
so control continues with the next instruction cycle
• IEN = 1 : the control circuit checks the flag bit, If either flag set
to 1, R F/F is set to 1
❖ At the end of the execute phase, control checks the value of R
• If R=0,the control will go through a fetch phase.
• If r=1,the control will go through an interrupt cycle.
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Interrupt cycle
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Design of basic computer
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Control Logic Gates
❖ The output of control logic circuit are:-
• Signals to control the inputs of the nine registers
• Signals to control the read and write inputs of memory
• Signals to set, clear, or complement the F/Fs
• Signals for S2 S1 S0 to select a register for the bus
• Signals to control the AC adder and logic circuit
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Design of Accumulator logic
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Design of accumulator logic
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