East West College of Engineering

Digital Design and Computer Organization

Subject Code: BCS302

Course objectives:

 To demonstrate the functionalities of binary logic system

 To explain the working of combinational and sequential logic system
 To realize the basic structure of computer system
 To illustrate the working of I/O operations and processing unit

Introduction to Digital Design: Binary Logic, Basic Theorems and Properties of Boolean
Algebra, Boolean Functions, Digital Logic Gates, Introduction, The Map Method, Four-Variable
Map, Don’t-Care Conditions, NAND and NOR Implementation, Other Hardware Description
Language – Verilog Model of a simple circuit.

Combinational Logic: Introduction, Combinational Circuits, Design Procedure, Binary

Adder- Subtractor, Decoders, Encoders, Multiplexers. HDL Models of Combinational Circuits –
Adder, Multiplexer, Encoder. Sequential Logic: Introduction, Sequential Circuits, Storage
Elements: Latches, Flip-Flops.

Basic Structure of Computers: Functional Units, Basic Operational Concepts, Bus

structure, Performance – Processor Clock, Basic Performance Equation, Clock Rate,
Performance Measurement. Machine Instructions and Programs: Memory Location and
Addresses, Memory Operations, Instruction and Instruction sequencing, Addressing Modes.

Input/output Organization: Accessing I/O Devices, Interrupts – Interrupt Hardware,

Enabling and Disabling Interrupts, Handling Multiple Devices, Direct Memory Access: Bus
Arbitration, Speed, size and Cost of memory systems. Cache Memories – Mapping Functions.

Basic Processing Unit: Some Fundamental Concepts: Register Transfers, Performing ALU
operations, fetching a word from Memory, Storing a word in memory. Execution of a Complete
Instruction. Pipelining: Basic concepts, Role of Cache memory, Pipeline Performance.

Digital Design & Computer Organisation Prof. Tulasi K.L, CSE

 East West College of Engineering

PRACTICAL COMPONENT OF IPCC

1. Given a 4-variable logic expression, simplify it using appropriate technique and simulate the
same using basic gates.

2. Design a 4-bit full adder and subtractor and simulate the same using basic gates.
3. Design Verilog HDL to implement simple circuits using structural, Data flow and Behavioural
model.
4. Design Verilog HDL to implement Binary Adder-Subtractor – Half and Full Adder, Half and
Full Subtractor.
5. Design Verilog HDL to implement Decimal adder.
6. Design Verilog program to implement Different types of multiplexers like 2:1, 4:1 and 8:1.
7. Design Verilog program to implement types of De-Multiplexer.
8. Design Verilog program for implementing various types of Flip-Flops such as SR, JK and D.

Course outcomes (Course Skill Set):

At the end of the course, the student will be able to:

CO1: Apply the K–Map techniques to simplify various Boolean expressions.

CO2: Design different types of combinational and sequential circuits along with Verilog
programs.

CO3: Describe the fundamentals of machine instructions, addressing modes and Processor
performance.

CO4: Explain the approaches involved in achieving communication between processor and I/O
devices.

CO5: Analyse internal Organization of Memory and Impact of cache/Pipelining on Processor

Performance.

Digital Design & Computer Organisation Prof. Tulasi K.L, CSE

 East West College of Engineering

Introduction to Digital Design

Digital design refers to the process of creating digital circuits, systems or products using digital
logic. It involves the use of binary values to represent and manipulate data. Ex: Design of Logic
gates, microprocessors, digital systems etc.

Comparison between Analog and Digital:

Parameter Analog Digital
Analog represents data in a Digital represents data using discrete
Data
continuous form. values, often in binary (0s and 1s).
Representation

Analog signals accuracy can be

Accuracy and Digital signals offer higher accuracy
affected by noise and signal
Precision and consistency.
degradation.
Storage and processing of
Storage and Digital data can be easily stored,
analog data are often more
Processing copied, and manipulated.
complex and less flexible.
Analog data requires more Digital signal requires less processing
Processing Time
processing time. time.
Manipulating analog signals
Flexibility and Digital offers greater flexibility in
typically involves physical
Manipulation manipulation.
adjustments or conversions.
Error handling in analog
systems can be challenging, Digital systems have built-in error-
Error Handling
with noise and signal loss checking and correction capabilities.
affecting accuracy.
Traditional fields like analog
Modern applications including digital
photography, Radio and
Applications photography, web design, Digital
Television Broadcasting, Analog
signal processors.
Audio Systems etc.

Waveform

Digital Design & Computer Organisation Prof. Tulasi K.L, CSE

 East West College of Engineering

Binary logic is a fundamental concept in digital electronics and computer science, where data
is represented and manipulated using binary numbers 0s and 1s. It forms the basis for designing
digital circuits, algorithms, and systems.

What is Positive Logic?

In digital electronic systems, if the high value of signal (voltage or current) is used to represent
the logic 1 and the low value of signal (voltage or current) is used to represent the logic 0, then it
is called a positive logic system.

The pulse waveform representation of a positive logic is shown in Figure-1. In the case of positive
logic, the voltage at 0 volts level represents the logic 0 (Logic LOW), and the voltage at +VCC volts
level represents the logic 1 (Logic HIGH).

In the generalized form, the positive logic is expressed as,

Higher Voltage = Logic HIGH
Lower Voltage = Logic LOW

Example of Positive Logic − Consider an NPN transistor. If the transistor is OFF, then its output
will be at +VCC that represents the logic 1 (HIGH) state. On the other hand, if the transistor is
ON, then its output will be 0 volts, and it represents the logic 0 (LOW) state.

What is Negative Logic?

In digital electronic systems, if the high value of signal (voltage or current) is used to represent
the logic 0 and the low value of signal (voltage or current) is used to represent the logic 1, then it
is called a negative logic system.

The pulse waveform representation of a negative logic is shown in Figure-2. In the case of
negative logic, the voltage at -VCC volts level represents the logic 0 (Logic LOW), and the voltage
at 0 volts level represents the logic 1 (Logic HIGH).

In the generalized form, the negative logic is expressed as,

Higher Voltage = Logic LOW (0)
Lower Voltage = Logic HIGH (1)

Digital Design & Computer Organisation Prof. Tulasi K.L, CSE

 East West College of Engineering

Example of Negative Logic − Consider a PNP transistor. If the transistor is OFF, then its output
will be at -VCC volts that represents the logic 0 (LOW) state. On the other hand, if the transistor
is ON, then its output will be 0 volts, and it represents the logic 1 (HIGH) state.

Binary System:
Definition: A number system that uses only two digits, 0 and 1, to represent data.
Base: Binary is a base-2 system, meaning each digit (bit) represents a power of 2.

Boolean algebra is a mathematical structure used to work with binary variables and logic
operations. It is fundamental to digital circuit design and computer science. Here are the basic
theorems and properties of Boolean algebra:

Basic Properties:
1. Commutative Properties:
 Commutative Law of Addition (OR): A+B = B+A
 Commutative Law of Multiplication (AND): A⋅B = B⋅A
2. Associative Properties:
 Associative Law of Addition (OR): (A+B) + C=A+ (B+C)
 Associative Law of Multiplication (AND): (A⋅B)⋅C = A⋅(B⋅C)
3. Distributive Property:
 Distributive Law: A⋅(B+C) = (A⋅B) + (A⋅C) : A+(B⋅C)=(A+B)⋅(A+C)
4. Identity Properties:
 Identity Law of Addition: A+0=A
 Identity Law of Multiplication: A⋅1= AA
5. Null Properties:
 Null Law of Addition: A+A’=1
 Null Law of Multiplication: A⋅A’= 0
6. Idempotent Properties:
 Idempotent Law of Addition: A+A = A

 Idempotent Law of Multiplication: A⋅A = A

7. Complement Properties:
 Complement Law: A+A’=1

Digital Design & Computer Organisation Prof. Tulasi K.L, CSE

 East West College of Engineering

8. Involution Property:
 Involution Law: A’= A

Basic Theorems
1. De Morgan's Theorems:
 First Theorem: (A⋅B)’= A’+B’
 Second Theorem: (A+B)’= A’⋅B’
2. Absorption Laws:
 Absorption Law 1: A+(A⋅B) = A
 Absorption Law 2: A⋅(A+B) = A
 Absorption Law 3: (A + A’B) = A +B
3. Consensus Theorem:
 Consensus Law: (A⋅B) + (A’⋅C) + (B⋅C) = (A⋅B) + (A’⋅C)
4. Redundancy Theorem:
 Redundancy Law: A⋅(A+B )=A
5. Duality Principle:
 Duality Law: Every Boolean algebraic expression remains valid if we interchange
the AND & OR operations and the 0s and 1s.

Applications

1. Simplification of Logic Circuits:

 Boolean algebra is used to simplify complex digital logic circuits to minimize the
number of gates and components.

2. Designing Digital Systems:

 The principles and theorems are applied to design reliable and efficient digital
systems, such as processors, memory, and communication systems.

3. Error Detection and Correction:

 Boolean algebra plays a role in developing algorithms for error detection and
correction in data transmission and storage.

4. Computer Programming:
 Understanding Boolean logic is essential for programming, especially in
conditions and loops.

Digital Design & Computer Organisation Prof. Tulasi K.L, CSE

 East West College of Engineering

Logic Gates: Basic building blocks of digital circuits that perform logical operations on binary
inputs.

 AND Gate: Outputs goes high (1) only when both the inputs are high (1).
 OR Gate: Outputs goes low (0) only when both the inputs are low (0).
 NOT Gate (Inverter): Outputs the opposite of the input (0 becomes 1, and 1 becomes 0).
 NAND Gate: Outputs goes high (0) only when both the inputs are high (1).
 NOR Gate: Outputs goes low (1) only when both the inputs are low (0).
 XOR Gate: Outputs goes high (1) when inputs differ.
 XNOR Gate: Outputs goes high (1) when inputs are same.

Digital Design & Computer Organisation Prof. Tulasi K.L, CSE

 East West College of Engineering

Simplify the following expressions using boolean laws

1. = + ’+ A
solution:

Y = BC + BC’+ BA
Y = B (C + C’) + BA
Y = B + BA (∵ C + C’= 1)

Y = B (1 + A) (∵ 1 + A = 1)
Y = B. 1
=B

2. F (A, B, C)=A′B+BC′+BC+AB′C′
Solution:

F=A′B+BC′+BC+AB′C′
F=A′B+(BC′+BC′)+BC+AB′C′ [By idempotent law, BC’ = BC’ + BC’]
F=A′B+(BC′+BC)+(BC′+AB′C′)

F=A′B+B(C′+C)+C′(B+AB′) [By distributive laws]

F =A′B+B.1+C′(B+A) (C' + C) = 1 and absorption law (B + AB')= (B + A)]
F=A′B+B+C′(B+A) [ B.1 = B ]
F=B(A′+1)+C′(B+A)
F=B.1+C′(B+A) [ (A' + 1) = 1 ]
F=B+C′(B+A) [ As, B.1 = B ]
F=B+BC′+AC′
F=B(1+C′)+AC′
F=B.1+AC′
[As, (1 + C') = 1]
F=B+AC′

3. = + ( )’
Solution:

Y = C + B’ + C’
Y = (C + C’) + B’
Y = 1 + B’
=1

Digital Design & Computer Organisation Prof. Tulasi K.L, CSE

 East West College of Engineering

5. = ( + ) ( + ’) + +
Solution:

Y = (A + C) (A(D + D’)) + AC + C
Y = (A + C) (A)(1) + AC + C
Y = AA + AC + AC + C

Y = A + AC + C
Y = A (1 + C) + C
= +

6. = ’ ( + ) + ( + ) ( + ’)
Solution:

Y = (A’A+ A’B + BA + BB’+ AAA + AAB’

Y=0+ + AB + 0 + A + AB’
Y = B (A’+ A) + A + AB’
Y = B + A (1 + B’)
= +

7. = + ( + )+ ( + )
Solution:

Y = AB + AB + AC + BB + BC
Y = AB + AC + B + BC [B(1 + C)]
Y = AB + AC + B
Y = B(A + 1) + AC
= +

8. F = AB + (AC)′ + AB′C(AB + C).

Solution:

F = AB + (AC)′ + AB′C(AB + C)
F= AB + A′ + C′+ AB′[Link] + AB′C.C

F= AB + A′ + C′ + 0 + AB′C (B.B′ = 0 and C.C = C)

F= ABC + ABC′ + A′ + C′ + AB′C (AB = AB(C + C′) = ABC + ABC′)
F= AC(B + B′) + C′(AB + 1) + A′
F= AC + C′+A′ (B + B′ = 1 and AB + 1 = 1)

F= AC + (AC)′ = 1

Digital Design & Computer Organisation Prof. Tulasi K.L, CSE

 East West College of Engineering

Definitions:
Literal: A variable or its complement
Product term: Literals connected by •
Sum term: Literals connected by +
Minterm: A product term in which all the variables appear exactly once, either complemented
or uncomplemented.

Maxterm: A sum term in which all the variables appear exactly once, either complemented or
uncomplemented.

Canonical form: Boolean functions expressed as a sum of Minterms or product of Maxterms

are said to be in canonical form.

Truth Table notation for Minterms and Maxterms

• Minterms and Maxterms are easy to denote using a truth table.

Example: Assume 3 variables x, y, z (order is fixed)

Digital Design & Computer Organisation Prof. Tulasi K.L, CSE

 East West College of Engineering

Example
Consider a Truth table for f1(a,b,c) at right
The canonical sum-of-products form for f1 is
f1(a,b,c) = m1 + m2 + m4 + m6

= a’b’c + a’bc’ + ab’c’ + abc’

The canonical product-of-sums form for f1 is
f1(a,b,c) = M0 • M3 • M5 • M7

= (a+b+c) • (a+b’+c’) • (a’+b+c’) • (a’+b’+c’).

Note: Observe that: mj =Mj’

Shorthand: ∑ and ∏
• f1(a,b,c) = ∑ m(1,2,4,6), where ∑ indicates that this is a sum-of-products form, and m(1,2,4,6)
indicates that the minterms to be included are m1, m2, m4, andm6.
• f1(a,b,c) = ∏ M(0,3,5,7), where ∏ indicates that this is a product-of-sums form, and M(0,3,5,7)
indicates that the maxterms to be included are M0, M3, M5, andM7.

• Since mj = Mj’ for any j,

∑m (1,2,4,6) = ∏ M(0,3,5,7) = f1(a,b,c)

Conversion between Canonical Forms

• Replace ∑ with ∏ (or vice versa) and replace those j’s that appeared in the original form with
those that do not.

Example:
f1(a,b,c)= a’b’c + a’bc’ + ab’c’ + abc’
= m1 + m2 + m4 + m6
= ∑m (1,2,4,6)
= ∏ M(0,3,5,7)

= (a+b+c) • (a+b’+c’) • (a’+b+c’) • (a’+b’+c’)

Conversion of SOP from standard to canonical form
Example - 1
Express the Boolean function F = A + B’C as a sum of minterms.
Solution: The function has three variables: A, B, and C. The first term A is missing two variables:
therefore,

A = A (B + B’) = AB + AB’

Digital Design & Computer Organisation Prof. Tulasi K.L, CSE

 East West College of Engineering

This function is still missing one variable, so

A = AB (C + C’) + AB’ (C + C’)

= ABC + ABC’ + AB’C + AB’C’

The second term B’C is missing one variable: hence,
B’C = B’C (A + A’) = AB’C + A’B’C
Combining all terms, we have
F = A + B’C

= ABC + ABC’ + AB’C + AB’C’+ A’B’C

But AB’C appears twice, and according to theorem (x + x = x), it is possible to remove one of
those occurrences. Rearranging the minterms in ascending order, we finally obtain

F = A’B’C + AB’C + AB’C + ABC’ + ABC

= m1 + m4 + m5 + m6 + m7

When a Boolean function is in its sum‐of‐minterms form, it is sometimes convenient to express

the function in the following brief notation:

F (A, B, C) = ∑m (1, 4, 5, 6, 7)

Map Method:
The Map Method (often referred to as Karnaugh Maps or K-Maps) is a graphical tool used to
simplify Boolean expressions and design digital circuits. It helps in visualizing and minimizing
complex Boolean functions by organizing truth table values into a grid. Here’s a detailed
explanation of the Map Method, focusing on the four-variable map and handling don't-care
conditions.

1. Karnaugh Maps (K-Maps)

Karnaugh Maps are used for simplifying Boolean expressions by visually grouping together
adjacent cells in a grid that represent minterms (or maxterms). Each cell in the map corresponds
to a combination of variable states and the output of the Boolean function.

Simplify the boolean expression using K-Map

1. Determine the Variables

Identify the number of variables in the Boolean function. This will determine the size of
the K-map:

2 variables: 2x2 K-map

Digital Design & Computer Organisation Prof. Tulasi K.L, CSE

 East West College of Engineering

3 variables: 2x4 K-map

4 variables: 4x4 K-map
2. Create the K-map Grid
Create the grid based on the number of variables. Each cell in the grid corresponds to a
minterm of the Boolean function.

3. Label the Rows and Columns

 2-variable K-map: Rows and columns are labelled with the possible values of each
variable.
 3-variable K-map: Rows are labelled with one variable, and columns are labelled with
the other two variables in Gray code.
 4-variable K-map: Rows and columns are labelled with Gray code sequences for each
pair of variables.

4. Fill in the K-map

Enter the values (0 or 1) into the K-map based on the given Boolean function or truth table.
Each cell corresponds to a minterm.

5. Group the 1s
 Identify Groups: Group adjacent 1s into rectangles. The groups can be of sizes 1, 2, 4, 8,
etc., and must be powers of 2.

 Rectangles: Groups can wrap around the edges of the map.

Rules for Grouping:
 Each group must contain 1, 2, 4, 8, etc., cells.
 Groups should be as large as possible to simplify the expression.
 Each cell with a 1 must be included in at least one group.

6. Write the Simplified Boolean Expression

For each group:
 Identify the Common Variables: Determine which variables stay constant across the
entire group.
 Form Product Terms: Each group will give a product term for the simplified expression.
 Combine Product Terms: Combine all the product terms using OR operations.

Digital Design & Computer Organisation Prof. Tulasi K.L, CSE

 East West College of Engineering

Sum of Product (SOP) FORM:

1. Minimize the following Boolean function-

F (A, B, C, D) = Σ m (0, 1, 2, 5, 7, 8, 9, 10, 13, 15)
Solution:

 Since the given boolean expression has 4 variables, so we draw a 4 x 4 K Map.

 We fill the cells of K Map in accordance with the given boolean function.
 Then, we form the groups in accordance with the K-MAP rules.

Now,
F (A, B, C, D)
= (A’B + AB) (C’D + CD) + (A’B’ + A’B + AB + AB’) C’D + (A’B’ + AB’) (C’D’ + CD’)
= BD + C’D + B’D’

Thus, minimized boolean expression is-

F (A, B, C, D) = BD + C’D + B’D’

2. Minimize the following boolean function-

F (A, B, C, D) = Σ m (0, 1, 3, 5, 7, 8, 9, 11, 13, 15)
Solution:

 Since the given boolean expression has 4 variables, so we draw a 4 x 4 K Map.

 We fill the cells of K Map in accordance with the given boolean function.
 Then, we form the groups in accordance with the K-MAP rules.

Digital Design & Computer Organisation Prof. Tulasi K.L, CSE

 East West College of Engineering

Now,
F (A, B, C, D)
= (A’B’ + A’B + AB + AB’) (C’D + CD) + (A’B’ + AB’)(C’D’ + C’D)
= D + B’C’

Thus, minimized boolean expression is-

F (A, B, C, D) = B’C’ + D

3. Minimize the following boolean function-

F (A, B, C, D) = Σ m (3, 4, 5, 7, 9, 13, 14, 15)
Solution:

 Since the given boolean expression has 4 variables, so we draw a 4 x 4 K Map.

 We fill the cells of K Map in accordance with the given boolean function.
 Then, we form the groups in accordance with the K-Map rules.

Now,
F (A, B, C, D)
= A’B (C’D’ + C’D) + (A’B’ + A’B) (CD) + (AB + AB’) (C’D) + AB (CD + CD’)

Digital Design & Computer Organisation Prof. Tulasi K.L, CSE

 East West College of Engineering

= A’BC’ + A’CD + AC’D + ABC

Thus, minimized boolean expression is-
F (A, B, C, D) = A’BC’ + A’CD + AC’D + ABC
It is important to note that we are not considering the quad group because we must consider the
duets anyhow.

4. Consider the following boolean function

F (W, X, Y, Z) = Σ m (1, 3, 4, 6, 9, 11, 12, 14)

This function is independent number of variables. Fill in the blank.

Solution:
 Since the given boolean expression has 4 variables, so we draw a 4 x 4 K Map.
 We fill the cells of K Map in accordance with the given boolean function.
 Then, we form the groups in accordance with the K-Map rules.

Now,
F (W, X, Y, Z)

= (W’X + WX) (Y’Z’ + YZ’) + (W’X’ + WX’) (Y’Z + YZ)

= XZ’ + X’Z

=X⊕Z
Thus, minimized boolean expression is-
F (W, X, Y, Z) = X ⊕ Z
Clearly, the given boolean function depends on only two variables X and Z.
Hence, it is independent of other two variables W and Y.

Digital Design & Computer Organisation Prof. Tulasi K.L, CSE

 East West College of Engineering

5. Minimize the following boolean function-

F (A, B, C, D) = Σ m (1, 3, 4, 6, 8, 9, 11, 13, 15) + Σ d (0, 2, 14)
Note: For certain input combinations, the value of the output is unspecified either because the
input combinations are invalid or because the precise value of the output is of no consequence.
The combinations for which the value of experiments is not specified are called don ‘t care
combinations are invalid or because the precise value of the output is of no consequence. The
combinations for which the value of expressions is not specified are called don ‘t care
combinations or Optional Combinations, such expressions stand incompletely specified. The
output is a don ‘t care for these invalid combinations.

Solution:
 Since the given boolean expression has 4 variables, so we draw a 4 x 4 K Map.
 We fill the cells of K Map in accordance with the given boolean function.
 Then, we form the groups in accordance with the K-Map rules.

Now,
F (A, B, C, D)
= (AB + AB’) (C’D + CD) + (A’B’ + AB’) (C’D + CD) + (A’B’ + AB’) (C’D’ + C’D) + (A’B’ + A’B) (C’D’ +
CD’)

= AD + B’D + B’C’ + A’D’

Thus, minimized boolean expression is-
F (A, B, C, D) = AD + B’D + B’C’ + A’D’

6. Minimize the following boolean function-

F (A, B, C, D) = Σ m (0, 2, 8, 10, 14) + Σ d (5, 15)

Digital Design & Computer Organisation Prof. Tulasi K.L, CSE

 East West College of Engineering

Solution:
 Since the given boolean expression has 4 variables, so we draw a 4 x 4 K Map.
 We fill the cells of K Map in accordance with the given boolean function.
 Then, we form the groups in accordance with the K-Map rules.

Now,
F (A, B, C, D)
= (AB + AB’) CD’ + (A’B’ + AB’) (C’D’ + CD’)
= ACD’ + B’D’

Thus, minimized boolean expression is-

F (A, B, C, D) = ACD’ + B’D’

7. Minimize the following boolean function-

F (A, B, C) = Σ m (0, 1, 6, 7) + Σ d (3, 5)
Solution:

 Since the given boolean expression has 3 variables, so we draw a 2 x 4 K Map.

 We fill the cells of K Map in accordance with the given boolean function.
 Then, we form the groups in accordance with the K-Map rules.

Digital Design & Computer Organisation Prof. Tulasi K.L, CSE

 East West College of Engineering

Now,
F (A, B, C)

= A'(B’C’ + B’C) + A (BC + BC’)

= A’B’ + AB

Thus, minimized boolean expression is-

F (A, B, C) = AB + A’B’
NOTE:

 It may be noted that there is no need of considering the quad group.

 This is because even if we consider that group, we will have to consider the other two
duets.
 So, there is no use of considering that quad group.

8. Minimize the following boolean function-

F (A, B, C) = Σ m (1, 2, 5, 7) + Σ d (0, 4, 6)
Solution:

 Since the given boolean expression has 3 variables, so we draw a 2 x 4 K Map.

 We fill the cells of K Map in accordance with the given boolean function.
 Then, we form the groups in accordance with the K-Map rules.

Now,
F (A, B, C)
= (A + A’) (B’C’ + B’C) + A (B’C’ + B’C + BC + BC’)
= B’ + A

Thus, minimized boolean expression is-

F (A, B, C) = A + B’

Digital Design & Computer Organisation Prof. Tulasi K.L, CSE

 East West College of Engineering

Exercise:
1. Design a Logic Circuit to provide an output when any two or three of four input switches are
closed(on).

2. Design a system with four inputs where output goes high only when majority of the inputs are
high. Implement the circuit using NAND & NOR realization.

3. Design a car safety alarm circuit diagram. The system considers four inputs: door (D), key (K),
seat pressure (P) and seat belt (B). The input is considered HIGH (1) if the door is closed, the
key is in, the driver is on the seat, or the seat belt is fastened. The alarm (A) should sound
with two conditions as stated below: The door is not closed, and the key is in. The door is
closed, the key is in the driver's seat, and the seat belt is not closed.

a. Construct a truth table for the system based on input arrangement D, K, P, B with A as an
output.

b. Design a Karnaugh map to verify the simplified expression.

c. Draw the simplified circuit using NOR gates only.
4. A digital system is to be designed in which the month of the year is given as I/P in four-bit
form. The month of January is represented as '0000', February as "0001" and so on. The
output of the system should correspond to the input of the month containing 31 days, or
otherwise, it is '0'. Consider the excess number in the I/P beyond 1011' as don't care
condition:

(i) Write truth table, SOP Σm and POS ∏M form

(ii) Simplify for SOP using K-map
(iii) (iii) Realize using basic gates

Universal Logic Gates – NAND Gate and NOR Gate

A universal logic gate is a type of logic gate that can be used to implement any logical function
without using any other type of logic gate.

There are two types of universal logic gates: NAND gate and NOR gate. These are called universal
logic gates because they can perform all three basic logic operations, i.e. AND, OR, and NOT.
Let us explore how these 2 universal logic gates work.

Digital Design & Computer Organisation Prof. Tulasi K.L, CSE

 East West College of Engineering

Digital Design & Computer Organisation Prof. Tulasi K.L, CSE

 East West College of Engineering

Example for NAND realization of the function F = A B + B C + D

Solution:

This function is in simplified Sum of Product form. First, we need to draw its AND-OR schematic.

Now we convert the above-given schematic into mixed notation by converting AND gate into
AND-INVERT and OR gate into INVERT-OR.

In the above circuit check for serial NOT gates (bubble or NOT), if any such case cancels the
serial NOT gates and replace all the remaining basic gates (AND, OR, NOT) by NAND gates.

Digital Design & Computer Organisation Prof. Tulasi K.L, CSE

 East West College of Engineering

Example for NOR realization of the function F = (A + B) (B + C) D

Solution:

This function is in simplified Product of Sum form. First, we need to draw its OR-AND schematic.

Now we convert the above-given schematic into mixed notation by converting OR gate into OR-
INVERT and AND gate into INVERT-AND.

In the above circuit check for serial NOT gates (bubble or NOT), if any such case cancels the
serial NOT gates and replace all the remaining basic gates (AND, OR, NOT) by NOR gates.

Digital Design & Computer Organisation Prof. Tulasi K.L, CSE

 East West College of Engineering

Hardware DESCRIPTION language

Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL). It is a language used for describing a
digital system like a network switch or a microprocessor or a memory or a flip−flop. It means; by
using an HDL we can describe any digital hardware at any level.

Syntax:
module module_name (Variables);
input input variables;
output ouput variables;
<body of module>

Endmodule

Verilog basic Operators

Operator Description

a&b Bitwise a AND b

a|b Bitwise a OR b

~a Bitwise NOT of a

a^b Bitwise a XOR b

a+b a plus b

a–b a minus b

a*b a multiplied to b

a/b a divided by b

a ** b a to the power of b

a%b a modulo b

a && b Logical a AND b

a || b Logical a OR b

!a Logical NOT of a

Digital Design & Computer Organisation Prof. Tulasi K.L, CSE

 East West College of Engineering

Design a Verilog model of a circuit having inputs A, B, C, D and outputs E, F, with functionality
specified by the following boolean expressions:

b) Y1=A+BC+B′D
c) Y2=B′C+BC′D′
Solution:

module Boolean expression(A,B,C,D,E,F);

input A, B, C, D;

output Y1, Y2;

assign Y1= A | (B & C) | (~ B & D);
assign Y2= (~B & C) | (B & ~C & ~D)
endmodule

Hardware Description Language: Verilog Model of a simple circuit.

NOT gate using Structural modeling NOT gate using data flow modeling

module not_gate_s(a , y); module not_gate_d(a, y);

input a; input a;

output y; output y;
not (y, a); assign y = ~a;
endmodule endmodule
AND gate using Structural modeling AND gate using data flow modeling
module and_gate_s(a,b,y); module and_gate_d(a,b,y);
input a,b; input a,b;

output y; output y;
and (y,a,b); assign y = a & b;
endmodule endmodule

OR gate using Structural modeling OR gate using data flow modeling

module not_gate_s(a,b,y); module not_gate_d(a,b,y);
input a,b; input a,b;

output y; output y ;
or (y,a,b); assign y = a | b;
endmodule endmodule

Digital Design & Computer Organisation Prof. Tulasi K.

L
East West College of Engineering

NAND gate using Structural modeling NAND gate using data flow modeling

module nand_gate_s(a,b,y); module nand_gate_d(a,b,y);

input a,b; input a,b;

output y; output y;
nand (y,a,b); assign y = ~ (a & b);
endmodule endmodule

NOR gate using Structural modeling NOR gate using data flow modeling

module nor_gate_s(a,b,y); module nor_gate_d(a,b,y);

input a,b; input a,b;

output y; output y;
nor (y,a,b); assign y = ~ (a | b);
endmodule endmodule
EX-OR gate using Structural modeling EX-OR gate using data flow modeling
module xor_gate_s(a,b,y); module xor_gate_d(a,b,y);
input a,b; input a,b;

output y; output y;
xor (y,a,b); assign y = a ^ b;
endmodule endmodule
EX-NOR gate using Structural modeling EX-NOR gate using data flow modeling
module xnor_gate_s(a,b,y); module xnor_gate_d(a,b,y);
input a,b; input a,b;

output y; output y;
xnor (y,a,b); assign y = ~ (a ^ b);
endmodule endmodule
Half adder using Structural modeling Half adder using data flow modeling
module half_adder s(a,b,sum,carry); module half_adder d(a,b,sum,carry);
input a,b; input a,b;

output sum,carry; output sum,carry;

xor (sum, a, b); assign sum = a ^ b;
and (carry, a, b); assign carry = a & b;
endmodule endmodule
Digital Design & Computer Organisation Prof. Tulasi K.L, CSE
East West College of Engineering

Full Adder using structural modeling Full Adder using data flow modeling
module full_add_d (a,b,c,sum,carry); module full_add_d (a,b,c,sum,carry);
input a,b,c; input a,b,c;

output sum,carry; output sum, carry;

wire w1,w2,w3,w4; assign sum = (a^b^cin);
xor (w1,a,b); assign carry = (a & b) | (b & c) | (c & a);
xor (sum,w1,c); endmodule
and (w2,a,b);
and (w3,b,c);
and (w4,c,a);
or (carry,w2,w3,w4);
endmodule
Digital Design & Computer Organisation Prof. Tulasi K.L, CSE