UNIT IV - ARM PROCESSOR

The history of computer architecture is punctuated by significant shifts in design philosophy,

but few have been as transformative as the emergence and subsequent dominance of the
Advanced RISC Machine (ARM) architecture. Originally conceptualized in the early 1980s by
Acorn Computers Limited in Cambridge, England, the ARM processor was born out of a
necessity for a high-performance, low-power replacement for the aging 8-bit MOS 6502 used
in the BBC Micro.1 Between 1983 and 1985, a small team of four designers developed a
proprietary 32-bit Reduced Instruction Set Computing (RISC) microprocessor that challenged
the prevailing Complex Instruction Set Computing (CISC) models of the era. 1 This architectural
lineage, characterized by simplicity, efficiency, and a unique licensing business model, has
evolved into an ecosystem that powers the vast majority of mobile devices, embedded systems,
and an increasing share of the high-performance computing market.3

The ARM design philosophy differentiates itself from traditional architectures through its focus
on energy efficiency and code density, which were initially driven by the physical constraints of
early mobile computing and the limited memory available in embedded systems.1 Unlike
manufacturers like Intel, which both design and fabricate silicon, ARM Holdings functions as a
provider of Intellectual Property (IP), licensing its Instruction Set Architecture (ISA) and core
designs to partners such as Apple, Qualcomm, and Samsung.4 This modular approach has
facilitated a diverse range of implementations, spanning from ultra-low-power microcontrollers
to multi-gigahertz application processors.4

The RISC Architectural Paradigm and ARM

Implementation
At its core, the ARM processor is an implementation of the RISC philosophy, which posits that a
processor can achieve higher performance and better energy efficiency by using a small,
uniform set of instructions that execute within a single clock cycle. 9 This contrasts fundamentally
with the CISC approach, where single, complex instructions might perform multiple
operations—such as loading data from memory, performing an arithmetic calculation, and
storing the result back to memory—over several clock cycles.9 By simplifying the instruction set,
RISC architectures allow for more efficient pipelining and higher clock frequencies, shifting the
burden of task complexity from the hardware to the software compiler.9

The ARM implementation of RISC principles is characterized by several defining features: a load-
store architecture where data processing instructions only operate on registers, fixed-length
instructions (typically 32 bits), and a large general-purpose register file.12 However, ARM is often
described as an "Advanced" RISC machine because it incorporates features that deviate from
"pure" RISC to improve code density and performance in practical embedded environments. 1
These enhancements include conditional execution of every instruction, an inline barrel shifter
that can scale operands before they reach the Arithmetic Logic Unit (ALU), and powerful multi-
register load and store instructions.13

Comparative Framework: RISC vs. CISC Architectures

Feature RISC (e.g., ARM) CISC (e.g., x86)

Instruction Set Small, simple, and uniform Large, complex, and varied

Instruction Size Fixed (usually 32 bits) Variable (1 to 15 bytes)

Cycles per Instruction (CPI) Aimed at 1.0 (Single-cycle) Variable (Multi-cycle)

Addressing Modes Simple and limited Complex and many

Memory Access Load/Store instructions only Memory-to-Memory

arithmetic possible

Registers Large general-purpose file Fewer, often specialized

Pipelining Easy to implement and Hard to implement due to

optimize instruction variation

Transistor Count Lower (simpler decoders) Higher (complex control logic)

The shift toward RISC was driven by the realization that complex instructions were infrequently
used by compilers, yet their presence in the hardware increased decoding overhead and cycle
times.9 By focusing on single-cycle execution of the most common instructions, RISC designs
like ARM could achieve higher throughput per milliwatt, making them the ideal choice for
battery-powered devices.6
Taxonomy of ARM Processor Families and Profiles
To address the divergent needs of the computing landscape, ARM introduced the Cortex series,
which segments the architecture into three distinct profiles: Application (Cortex-A), Real-time
(Cortex-R), and Microcontroller (Cortex-M).8 This "A-R-M" taxonomy ensures that a processor
can be optimized for its specific operational environment—whether that involves running a full-
featured operating system, managing safety-critical real-time tasks, or operating on a coin-cell
battery for years.20

The Cortex-A (Application) Profile

The Cortex-A profile is designed for high-performance systems capable of running complex
operating systems like Linux, Android, or Windows.20 These processors are equipped with a
Memory Management Unit (MMU), which supports virtual memory and process isolation—
features necessary for multitasking and security in modern computing. 20 Cortex-A cores utilize
deep pipelines, superscalar execution, and advanced branch prediction to maximize
performance.8

Within the A-series, there is a broad range of performance levels. For instance, the Cortex-A5
and A7 are optimized for energy efficiency, whereas the A15 and A78 target high-end mobile
and server performance.22 The A15, for example, offers up to higher performance than
the A9 in certain workloads.22 Furthermore, newer iterations like the Cortex-A510 and A710
implement the Armv9 architecture, which includes significant machine learning and security
enhancements such as Scalable Vector Extension 2 (SVE2) and Realm Management Extension
(RME).3

The Cortex-R (Real-Time) Profile

The Cortex-R family targets embedded systems where determinism and reliability are more
important than raw peak performance.20 These processors are used in automotive applications
(e.g., ABS, engine control), industrial controllers, and high-performance storage such as SSD
controllers.20 Unlike the A-series, Cortex-R processors typically use a Memory Protection Unit
(MPU) rather than an MMU, which provides predictable memory access times by avoiding the
non-deterministic overhead of virtual-to-physical address translation.20

A hallmark of the Cortex-R profile is the support for "lockstep" configurations, where two
identical cores execute the same code in parallel.20 If the results of the two cores diverge—
perhaps due to a hardware fault or transient error—the system can detect the error and
transition to a safe state, making it critical for safety-critical environments.20

The Cortex-M (Microcontroller) Profile

The Cortex-M family is optimized for the microcontroller market, where small silicon area, ultra-
low power consumption, and ease of use are paramount.20 These cores power billions of IoT
devices, sensors, and wearables.20 The Cortex-M architecture utilizes the Thumb and Thumb-2
instruction sets, which provide a high degree of code density, allowing complex programs to fit
into small amounts of on-chip Flash memory.7

The Cortex-M series includes several tiers: the M0 and M0+ are designed for maximum
efficiency; the M3 and M4 introduce more advanced instruction sets and optional hardware
floating-point units (FPU); and the M7 offers higher clock frequencies and dual-issue superscalar
pipelines for intensive embedded processing.24 A defining feature of this profile is the Nested
Vectored Interrupt Controller (NVIC), which provides fast, low-latency, and deterministic
interrupt handling with built-in support for interrupt nesting and prioritization.20

Summary of ARM Cortex Profiles and Characteristics

Attribute Cortex-A Cortex-R (Real- Cortex-M

(Application) Time) (Microcontroller)

Memory MMU (Supports MPU (Region-based MPU (Optional)

Management Virtual Memory) protection)

Typical OS Linux, Android, RTOS (Real-Time OS) Bare-metal or RTOS

Windows

Instruction Set ARM, Thumb-2, ARM, Thumb-2, DSP Thumb-2, DSP (M4/M7)
NEON, SVE2

Primary Goal High Determinism and Low cost and low

performance/throug reliability power
hput

Architecture Armv7-A, Armv8-A, Armv7-R, Armv8-R Armv6-M, Armv7-M,

Armv9-A Armv8-M

Key Feature TrustZone, NEON Lockstep Cores NVIC, Ultra-low power

8
The ARM7TDMI Architecture: An In-Depth Hardware
Perspective
The ARM7TDMI represents a critical milestone in the transition from simple microcontroller
cores to sophisticated 32-bit embedded processors. As a synthesizable macrocell, the
ARM7TDMI was one of the most widely deployed 32-bit cores in history, serving as the
foundation for early digital cell phones, handheld gaming consoles like the Game Boy Advance,
and industrial controllers.1 The "TDMI" suffix denotes its specific architectural extensions: Thumb
(16-bit compressed instruction set), Debug (hardware support for breakpoints and
watchpoints), Multiplier (enhanced 32x8 hardware multiplier), and ICE (EmbeddedICE logic for
real-time debugging).17

Internal Microarchitecture and Data Path

The ARM7TDMI utilizes a Von Neumann architecture, where both instructions and data are
accessed over a single 32-bit data bus.2 While this simplifies the bus interface, it can lead to a
performance bottleneck because the processor cannot fetch an instruction and access data
simultaneously.26 To mitigate this, the core implements a three-stage instruction pipeline: Fetch,
Decode, and Execute.15

1. Fetch: The instruction is retrieved from memory and placed into the pipeline.17
2. Decode: The instruction is analyzed to determine the required operation and identifying
the source and destination registers.17
3. Execute: The actual operation is performed, such as an ALU calculation, a memory
load/store, or a branch.17

This three-stage pipeline allows the processor to complete one instruction per clock cycle under
ideal conditions.15 However, when a branch instruction occurs or the Program Counter (PC) is
modified, the pipeline must be flushed because the fetched instructions are no longer relevant
to the new execution flow.1 This penalty is typically three cycles as the pipeline is refilled from
the new branch target.28

PC Behavior and Offset Calculation

A critical nuance for assembly programmers is the behavior of the Program Counter (PC, or R15)
in the three-stage pipeline. Because the PC points to the instruction being fetched, and the fetch
occurs two stages ahead of the execute stage, the value of the PC is always the address of the
currently executing instruction plus 8 bytes (in ARM mode) or plus 4 bytes (in Thumb mode). 15
This offset must be accounted for when calculating relative branch offsets or when an exception
occurs and the return address is saved.28
Functional Units: Multiplier and Barrel Shifter
The ARM7TDMI includes specialized functional units that enhance its performance in data-
intensive applications. The hardware multiplier (the "M" in TDMI) uses a Booth algorithm to
perform fast multiplications.15 It can handle 32-bit inputs and produce the 32 least significant
bits of the product, with higher-end variants supporting 64-bit "long" multiplication results.15

The inline barrel shifter is perhaps the most unique feature of the ARM data path. 1 It is located
on the second operand path to the ALU, allowing a register operand to be shifted or rotated by
an immediate value or another register in a single cycle before the ALU operation is performed.15
This enables efficient array indexing and complex arithmetic operations. For example, the
instruction ADD R0, R1, R2, LSL #2 calculates in one cycle.16

Barrel Shifter Operation Mnemonic Description

Logical Shift Left LSL Bits shifted left; zero filled at the

bottom. Multiplies by

Logical Shift Right LSR Bits shifted right; zero filled at

the top. Divides by

(unsigned)

Arithmetic Shift Right ASR Bits shifted right; sign bit copied
into vacated positions. Divides

by (signed)

Rotate Right ROR Bits shifted right; bits falling off

the end re-enter at the top

Rotate Right Extend RRX 33-bit rotation using the Carry

flag as the 33rd bit

16
The Programmer’s Model and Register Organization
The ARM7TDMI provides a consistent and powerful programmer's model that supports multiple
operating modes and a large register file.27 In total, the processor has 37 registers, but only a
subset is visible to the programmer at any given time, depending on the current processor
mode.15

Operating Modes
The architecture defines seven basic operating modes, each with a specific purpose and level
of privilege.26

1. User Mode: The normal unprivileged mode in which most applications run. It has restricted
access to system resources.7
2. FIQ (Fast Interrupt Request): Entered when a high-priority interrupt is signaled. It features
extra banked registers to minimize interrupt latency.7
3. IRQ (Interrupt Request): Entered for standard, lower-priority interrupts.7
4. Supervisor (SVC) Mode: Entered on processor reset or when a Software Interrupt (SWI)
instruction is executed. Typically used for OS kernels.26
5. Abort Mode: Entered when a memory access violation (either prefetch or data abort)
occurs.26
6. Undefined Mode: Entered when the processor encounters an opcode it cannot decode as
a valid instruction.26
7. System Mode: A privileged mode that uses the same registers as User mode, allowing the
OS to access system state without the overhead of register banking.26

Register File and Register Banking

Registers R0 through R12 are general-purpose registers.17 R13 is the Stack Pointer (SP), R14 is
the Link Register (LR), and R15 is the Program Counter (PC). 27 The Current Program Status
Register (CPSR) contains condition flags (Negative, Zero, Carry, Overflow), interrupt mask bits,
and mode bits.27

Register banking is a mechanism where certain registers are "swapped out" with private, mode-
specific versions when the processor transitions to a privileged mode.17 This allows an exception
handler to preserve the state of the user program without manually saving registers to the
stack.17 For instance, FIQ mode has its own private R8-R14, which is why it is "fast"—the handler
can use seven registers immediately without affecting the background task.27
Register User/Syste FIQ IRQ SVC Abort Undef
Type m

General R0-R7 R0-R7 R0-R7 R0-R7 R0-R7 R0-R7

Banked R8-R12 R8_fiq- R8-R12 R8-R12 R8-R12 R8-R12

R12_fiq

SP (R13) R13 R13_fiq R13_irq R13_svc R13_abt R13_und

LR (R14) R14 R14_fiq R14_irq R14_svc R14_abt R14_und

PC (R15) R15 R15 R15 R15 R15 R15

Status CPSR CPSR CPSR CPSR CPSR CPSR

Saved - SPSR_fiq SPSR_irq SPSR_svc SPSR_abt SPSR_und

Status

17

Interrupts, Exceptions, and Vectoring

Exception handling in the ARM architecture is deterministic and efficient. When an exception
occurs, the hardware automatically saves the current CPSR into the SPSR of the exception
mode, updates the CPSR to set the new mode and disable interrupts (if necessary), saves the
return address into the LR of the new mode, and sets the PC to the corresponding entry in the
exception vector table.27

The Exception Vector Table

The vector table is a set of fixed addresses, typically at the bottom of memory (

to ), where the processor jumps in response to specific events.15

Exception Vector Address Priority Mode on Entry

Reset 0x00000000 1 (Highest) Supervisor

Undefined 0x00000004 6 Undefined

Instruction

Software Interrupt 0x00000008 6 Supervisor

(SWI)

Prefetch Abort 0x0000000C 5 Abort

Data Abort 0x00000010 2 Abort

Reserved 0x00000014 - -

IRQ 0x00000018 4 IRQ

FIQ 0x0000001C 3 FIQ

15

Returning from an exception involves restoring the CPSR from the SPSR and restoring the PC
from the LR. Because of the pipeline offset, the return instruction often needs to adjust the LR
value.27 For example, a return from an IRQ requires the instruction SUBS PC, LR, #4 to return to
the instruction that was about to be executed when the interrupt occurred. 27

Comprehensive ARM Instruction Set and Addressing

Modes
The ARM instruction set is designed to be highly regular, facilitating efficient hardware decoding
while providing significant power to the assembly programmer.12 All instructions are 32 bits long
(in ARM state) and are word-aligned in memory.13
Data Processing Instructions
Data processing instructions only operate on registers or immediate values. 14 They follow a
three-operand format: Rd = Rn <Op> Operand2. If the 'S' bit is set in the instruction (e.g., ADDS),
the ALU condition flags in the CPSR are updated based on the result.16

● Arithmetic: ADD, ADC (Add with Carry), SUB, SBC (Subtract with Carry), RSB (Reverse
Subtract).16
● Logical: AND, ORR (Logical OR), EOR (Exclusive OR), BIC (Bit Clear). 16
● Move: MOV (Copy value), MVN (Move Not/Bitwise NOT).16
● Comparison: CMP (Compare), TST (Test bits), TEQ (Test Equivalence). These instructions
always set flags and do not save a result in a destination register.16

Memory Access (Load/Store) Architecture

The only way to access memory in ARM is through Load (LDR) and Store (STR) instructions. 14
These instructions support byte (8-bit), halfword (16-bit), and word (32-bit) transfers.27 A
significant feature is the Load/Store Multiple (LDM/STM) instructions, which can transfer any
subset of the 16 general-purpose registers to or from memory in a single instruction—highly
efficient for stack operations and context switching.13

Advanced Addressing Modes

ARM's memory addressing modes are particularly versatile, providing several ways to calculate
the Effective Address (EA).13

1. Register Indirect: The address is in a register. LDR R0,.13

2. Pre-indexed: An offset is added to the base register before access. LDR R0, (EA = R1 + 4).13
3. Pre-indexed with Writeback: Same as pre-indexed, but the base register is updated with
the new address after the access. LDR R0,! (EA = R1 + 4; R1 = R1 + 4). 13
4. Post-indexed: The address in the base register is used for the access, and then the offset
is added to the base register. LDR R0,, #4 (EA = R1; R1 = R1 + 4).13
5. Scaled Register: The offset is another register, optionally scaled by the barrel shifter. LDR
R0, (EA = R1 + (R2 * 4)).13
Addressing Form Syntax Example Effective Address Base Writeback?
(EA)

Immediate Offset `` Rn + imm No

Register Offset `` Rn + Rm No

Scaled Register `` Rn + (Rm << n) No

Pre-indexed! ! Rn + imm Yes (Rn = EA)

Post-indexed , #imm Rn Yes (Rn = Rn + imm)

13

Comparative Analysis: ARM vs. Arduino Processor

Designs
A practical illustration of ARM's architectural advantages can be found by comparing the classic
8-bit AVR architecture (used in the Arduino Uno) with the 32-bit ARM Cortex-M0+ (used in
modern Arduino boards like the Zero and MKR series).25

The ATmega328P (AVR) Architecture

The ATmega328P is an 8-bit RISC processor with a modified Harvard architecture, where
program and data memory exist in separate physical address spaces.38 While simple and highly
deterministic (1 clock cycle per instruction), it is limited by its 8-bit data path. A 32-bit integer
addition on an AVR requires multiple 8-bit instructions, whereas an ARM core performs it in one
cycle.38 Furthermore, the AVR lacks advanced features like DMA or a unified memory space,
forcing programmers to use specialized macros like PROGMEM to store constants in Flash.25

The SAMD21 (ARM Cortex-M0+) Architecture

The SAMD21, used in modern Arduino designs, provides a significant leap in computational
capability. It features a 32-bit data path, a 48 MHz clock (vs. 16 MHz for the Uno), and a unified
address space where Flash, RAM, and peripherals are all mapped into a single memory
map.25

The SAMD21 also introduces advanced peripheral architectures:

● SERCOM (Serial Communication Interface): Six configurable modules that can each be
programmed as a UART, SPI, or I2C interface, providing unprecedented pin flexibility. 40
● DMA (Direct Memory Access): A 12-channel controller that can transfer data between
peripherals and memory without CPU intervention, enabling high-speed tasks like audio
streaming while the CPU handles other logic.38
● Event System: Allows peripherals to trigger actions in other peripherals directly through a
hardware matrix, reducing interrupt overhead and power consumption.38

Architectural Benchmarks: ATmega328P vs. SAMD21

Specification ATmega328P (AVR) SAMD21 (ARM Cortex-M0+)

Architecture 8-bit AVR RISC 32-bit ARM Cortex-M0+

Operating Voltage 1.8V - 5.5V (5V standard) 1.62V - 3.63V (3.3V standard)

Clock Speed 16 MHz 48 MHz

SRAM 2 KB 32 KB

Flash Memory 32 KB 256 KB

DMA Channels None 12

ADC Resolution 10-bit 12-bit

USB Support External chip needed Native USB Host/Device

The transition from 8-bit to 32-bit in the Arduino ecosystem highlights the core strengths of the
ARM architecture: high code density, powerful peripherals, and a scalable performance curve
that addresses the complexity of modern embedded applications.25