1/31/2026

ADVANCED TOPICS
4 Hours
3 Marks (Approximately)

OUTLINES
• Multiprocessing Systems • Features of Typical Operating System
• Real and Pseudo‐Parallelism • Different Microprocessor Architectures
• Flynn’s Classification • Register Based and Accumulator Based
• Instruction Level, Thread Level and Architecture
Process Level Parallelism • RISC and CISC Architectures
• Interprocess Communication, Resource • Digital Signal Processors
Allocation and Deadlock

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MULTIPROCESSING SYSTEMS
• Contains two or more similar general purpose processors of comparable capability
• All processors share access to common memory.
• All processors share access to I/O devices either through the same channels that
provide paths to the same devices
• System is controlled by an integrated operating system that provides interaction
between processors and their programs
• Processors can communicate with each other through memory
• Categorized into three types

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ORGANIZATION OF MULTIPROCESSING SYSTEMS

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ORGANIZATION OF MULTIPROCESSING SYSTEMS

• Time shared or Common Bus
• Multiport Memory
• Central Control Unit

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TIME SHARED or COMMON BUS

• Multiple CPUs, I/O modules and memory modules connected to the same bus
• Time shared system must distinguish the modules on the bus to determine the source
and destination of the data
• Any module in the bus can temporarily act as a master
• When one module is controlling the bus, the other should be locked out
• Access to each module is divided on the basis of time

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TIME SHARED or COMMON BUS

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MULTIPORT MEMORY
• Each processor and I/O module has dedicated path to each memory module
• More performance and complexity than earlier one
• Possible to configure portions of memory as private to one or more CPUs and or I/O
modules
• Allows increasing security against unauthorized access and the storage of recovery
routines from other processors

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MULTIPORT MEMORY

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CENTRAL CONTROL UNIT

• Manages the transfer of separate data streams back and forth between independent
modules like CPU, memory and I/O
• Controller can buffer requests and perform arbitration and timing functions
• Pass status and control messages between CPUS
• Co-ordination is concentrated in the central control unit un-disturbing the modules
• More flexible and complex as well

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REAL AND PSEUDO‐PARALLELISM

• Parallelism is the simultaneous use of multiple computer resources to solve a
computational problem
• Problem is broken in discrete parts that can be solved concurrently
• Instructions are executed one after another
• Only one instruction may execute at any moment in time
• Each part is further broken down to a series of instructions
• Instructions from each part execute simultaneously on different CPUs

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REAL AND PSEUDO‐PARALLELISM

• Real Parallelism consists of the parallel modes of physical devices so that each can
carry parallel operations to each other
• Core parallelism consists of real parallelism
• Multiple core processes which are physically different and performs their own operations
in parallel

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REAL AND PSEUDO‐PARALLELISM

• Pseudo parallelism consists of the same device carrying the parallel operation
• Logical management for the parallelism in system
• Concurrent processing using parallelism is the pseudo parallelism
• Operates either in time division or using other types of parallel algorithms

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FLYNN’S CLASSIFICATION
• Distinguishes multi-processor computer architectures according to how they can be
classified along the two independent dimensions of Instruction and Data
• Each of these dimensions can have only one of two possible states: Single or Multiple.
• Four possible classifications according to Flynn
• Single Instruction, Single Data (SISD)
• Single Instruction, Multiple Data (SIMD)
• Multiple Instruction, Single Data (MISD)
• Multiple Instruction, Multiple Data (MIMD)

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SINGLE INSTRUCTION, SINGLE DATA (SISD)

• Serial (non-parallel) computer
• Single Instruction
• Only one instruction stream is being acted on by the CPU during any one clock
cycle
• Single Data
• Only one data stream is being used as input during any one clock cycle
• Single instruction is performed on a single set of data in a sequential form.
• Examples: Older generation mainframes, minicomputers and workstations

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SINGLE INSTRUCTION, MULTIPLE DATA (SIMD)

• Type of parallel computer
• Single Instruction
• All processing units execute the same instruction at any given clock cycle
• Multiple Data
• Each processing unit can operate on a different data element
• Suited for specialized problems characterized by a high degree of regularity, such as
graphics/image processing.
• Single Instruction is performed on multiple data
• Example: 'For' loop statement

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MULTIPLE INSTRUCTION, SINGLE DATA (MISD)

• Type of parallel computer
• Multiple Instruction
• Each processing unit operates on the data independently via separate instruction
streams
• Single Data
• A single data stream is fed into multiple processing units
• N numbers of processors are working on different set of instruction on the same set of
data
• Examples: Experimental Carnegie-Mellon [Link] computer (1971)
• Applicable to multiple frequency filters, multiple cryptography algorithms
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MULTIPLE INSTRUCTION, MULTIPLE DATA (MIMD)

• Type of parallel computer
• Multiple Instruction
• Every processor may be executing a different instruction stream
• Multiple Data
• Every processor may be working with a different data stream
• An interaction of N numbers of processors on a same data stream shared by all
processors
• Execution can be synchronous or asynchronous, deterministic or non-deterministic
• Examples: Supercomputers, networked parallel computer clusters and "grids", multi-
processor SMP computers, multi-core PCs
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INSTRUCTION LEVEL PARALLELISM(ILP)

• Measure of how many of the operations in a computer program can be performed
simultaneously
• Consider the following program
• 1. e = a + b
• 2. f = c + d
• 3. g = e * f
• Operation 3 depends on the results of operations 1 and 2
• Operation 3 cannot be calculated until both of them are completed
• Operations 1 and 2 do not depend on any other operation, so they can be calculated
simultaneously

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INSTRUCTION LEVEL PARALLELISM(ILP)

• If we assume that each operation can be completed in one unit of time then these three
instructions can be completed in a total of two units of time, giving an ILP of 3/2
• A goal of compiler and processor designers is to identify and take advantage of as much
ILP as possible
• Allows the compiler and the processor to overlap the execution of multiple instructions or
even to change the order in which instructions are executed
• No. of ILP existing in programs is very application specific
• For example graphics and scientific computing the amount can be very large

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THREAD LEVEL PARALLELISM

• Task Parallelism, function parallelism and control parallelism
• Form of parallelization of computer code across multiple processors in parallel
computing environments
• Focuses on distributing execution processes (threads) across different parallel
computing nodes
• Contrasts to data parallelism as another form of parallelism
• Single program might have several threads (or functions) that could be executed
separately or in parallel
• Example: Direct Memory Access as a separate thread from the computation thread

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THREAD LEVEL PARALLELISM

• Multi-threading (MT) general approach was introduced in • Example:
the 1970s when systems were designed to run multiple
• if CPU="a" then
computation threads in parallel
• do task "A"
• Emphasizes the distributed (parallelized) nature of the
processing (i.e. threads), as opposed to the data (data • else if CPU="b" then
parallelism) • do task "B"
• end if
• ...
• end program

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PROCESS LEVEL PARALLELISM

• Use of one or more central processing units (CPUs) within a single computer system
• Refers to the ability of a system to support more than one processor and/or the ability to
allocate tasks between them
• Trends indicated by ever faster networks, distributed systems, and multi-processor
computer architectures (even at the desktop level) clearly show parallelism

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INTER-PROCESS COMMUNICATION (IPC)

• Set of methods for the exchange of data among multiple threads in one or more
processes
• Processes may be running on one or more computers connected by a network
• IPC methods are divided into methods for message passing, synchronization, shared
memory, and remote procedure calls (RPC)
• Combination of IPC with the address space concept is the foundation for address space
independence/isolation
• Single operating system controls the use of system resources in a multiprocessing
environment

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INTER-PROCESS COMMUNICATION

• IPC allows the processes running on the single system to

communicate with other.
• Two basic communication model for providing IPC are:
• Shared Memory
• Message Passing

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SHARED MEMORY

• Communication between processes using shared memory requires

processes to share some variable and it completely depends on how
programmer will implement it.
• One way of communication using shared memory can be imagined like
this:
• Suppose process1 and process2 are executing simultaneously and
they share some resources or use some information from other
process, process1 generate information about certain computations or
resources being used and keeps it as a record in shared memory.
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SHARED MEMORY

• When process2 need to use the shared

information, it will check in the record stored in
shared memory and take note of the information
generated by process1 and act accordingly.
• Processes can use shared memory for
extracting information as a record from other
process as well as for delivering any specific
information to other process.

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MESSAGE PASSING

• In this method, processes communicate with each other

without using any kind of shared memory.
• If two processes p1 and p2 want to communicate with each
other, they proceed as follow:
• Establish a communication link (if a link already exists, no
need to establish it again).
• Start exchanging messages using basic primitives.

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MESSAGE PASSING

• We need at least two primitives:

• send(message, destination) or send(message)
• receive(message, host) or receive(message)

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RESOURCE ALLOCATION
• Resources could be access to a section of the computer's memory, data in a device
interface buffer, one or more files, or the required amount of processing power.
• Computer with a single processor can only perform one process at a time, regardless of
the amount of programs loaded by the user (or initiated on start-up)
• Computers using single processors appear to be running multiple programs at once
• Processor quickly alternates between programs, processing what is needed in very
small amounts of time→multitasking or time slicing
• Computer with multiple processors different processes can be allocated to different
processors

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DEADLOCK – [1]
• Process requests resources
• If the resources are not available at that time, the process enters a wait state
• Waiting processes may never again change state, because the resources they have
requested are held by other waiting processes→deadlock
• Processes need access to resources in reasonable order
• Suppose a process holds resource A and requests resource B, at same time another
process holds B and requests A; both are blocked and remain in deadlock

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DEADLOCK – [2]

• Deadlock is a situation where a set of processes are blocked

because each process is holding a resource and waiting for another
resource acquired by some other process.
• Deadlock occurs when a process in a set are in simultaneously wait
state for the release of resource held exclusively by one of the
waiting process in the set.

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CONDITION FOR DEADLOCK

• Mutual Exclusion condition

• Hold and wait condition
• No preemption condition
• Circular wait condition

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MUTUAL EXCLUSION CONDITION

• There should be a resource that can only be held by one process at

a time.
• In the diagram above, there is a single instance of Resource-1 and
it is held by Process-1 only.
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HOLD AND WAIT CONDITION

• A process can hold multiple resources and still request more resources
from other processes which are holding them.
• In the diagram given above, Process 2 holds Resource 2 and Resource 3
and is requesting the Resource 1 which is held by Process 1.
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NO PREEMPTION CONDITION

• A process can hold multiple resources and still request more resources
from other processes which are holding them.
• In the diagram given above, Process 2 holds Resource 2 and Resource 3
and is requesting the Resource 1 which is held by Process 1.
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CIRCULAR WAIT CONDITION

• A process is waiting for the resource held by the second process, which is waiting
for the resource held by the third process and so on, till the last process is waiting
for a resource held by the first process. This forms a circular chain.
• For example: Process 1 is allocated Resource2 and it is requesting Resource 1.
Similarly, Process 2 is allocated Resource 1 and it is requesting Resource 2. This
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forms a circular wait loop.

INTRODUCTION OPERATING SYSTEM

• Operating system is a program that acts as an interface between the user and
the computer hardware and controls the execution of all kinds of programs.
• An interface between a computer user and computer hardware.
• A software which performs all the basic tasks like file management, memory
management, process management, handling input and output, and controlling
peripheral devices such as disk drives and printers.
• Some popular Operating Systems include Linux Operating System, Windows
Operating System, VMS, OS/400, AIX, z/OS, etc.

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PICTORIAL VISUALIZATION OF OS

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• Operating System hides the complexity of hardware and presents a

beautiful interface to the users.

Figure: Operating Systems turn ugly hardware into beautiful abstractions.

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DIFFERENT MICROPROCESSOR ARCHITECTURES

• Register Based Architectures
• Accumulator Based Architecture

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ACCUMULATOR BASED ARCHITECTURE

• Accumulator is a most significant register then compared to other registers
• Most of the arithmetic and logic operations are performed using the accumulator
.performed via the accumulator
• Internal architecture of 8085 shows that the registers B,C,D,E,H and L are connected
with the ALU through the accumulator and temporary register
• Data can only enter into the ALU from accumulator and the out pot of the ALU can be
stared in accumulator through data bus

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REGISTER BASED ARCHITECTURE

• All the arithmetic and logical operation consists of the operands of any registers
• Input/output operations here register A and register B are similar
• Internal architecture of 8086 shows that the registers A, B, C, D and others directly with
the ALU.
• Data can enter into the ALU from any registers, and for I/O operation register A only can
be used
• Advantage of register based architecture is that extendibility and flexibility in
programming.
• Processor will be enhanced in register based architecture.
• Disadvantage is requirement of complex circuitry.
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RISC AND CISC ARCHITECTURE

RISC CISC
Some of the instructions refer to memory Most of the instructions refer to Memory
There are few addressing modes. Mostly There are many addressing modes
Register to register addressing modes
There are few instructions There are many instructions
It can include simple instructions and takes one It can include complex instructions and takes
cycle multiple cycles
Hardware executes the instructions Micro-program executes the instructions
There are Fixed format instructions There are Variable format instructions
It can be easier to decode as instructions have a It can be complex to decode as instructions have
fixed format variable format
There are multiple register sets are used A single register set is used
RISC is highly pipelined CISC is not pipelined or less pipelined
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END OF CHAPTER

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