NCP1217

Enhanced PWM Current−Mode

Controller for High−Power
Universal Off−Line Supplies
Housed in an SO−8 or PDIP−7 package, the NCP1217 represents
the enhanced version of the NCP1203−based controllers. Thanks to its [Link]
high drive capability, NCP1217 drives large gate−charge MOSFETs,
which together with internal ramp compensation and built−in
overvoltage protection, ease the design of modern AC/DC adapters. MINIATURE PWM
NCP1217 offers a true alternative to UC384X−based designs. CONTROLLER FOR HIGH
With an internal structure operating at different fixed frequencies
(65–100–133 kHz), the controller features a high−voltage start−up POWER AC/DC WALL
FET, which ensures a clean and loss less start−up sequence. Its ADAPTERS AND OFFLINE
current−mode control topology provides an excellent input audio−
susceptibility and inherent pulse−by−pulse control. Internal ramp BATTERY CHARGERS
compensation easily prevents subharmonic oscillations from taking
place in continuous conduction mode designs.
MARKING
When the current setpoint falls below a given value, e.g. the output
DIAGRAMS
power demand diminishes, the IC automatically enters the so−called
skip cycle mode and provides excellent efficiency at light loads. 8
Because this occurs at a user adjustable low peak current, no acoustic SO−8 17Dyy
noise takes place. D SUFFIX ALYW
8 CASE 751
The NCP1217 features two efficient protective circuitries: 1) In
presence of an overcurrent condition, the output pulses are disabled 1 1
and the device enters a safe burst mode, trying to restart. Once the
default has gone, the device auto−recovers. 2) If an external signal
PDIP−7 P1217Pxxx
(e.g. a temperature sensor) pulls pin1 above 3.2 V, output pulses are P SUFFIX AWL
immediately stopped and the NCP1217 stays latched in this position. CASE 626B YYWW
Reset occurs when the VCC collapses to ground, e.g. the user unplugs 8
the power supply. 1
1
Features
• Current−Mode with Adjustable Skip−Cycle Capability xxx = Device Code: 065, 100 or 133
• Built−in Internal Ramp Compensation
yy = Device Code:
06 for 65
• Auto−Recovery Internal Output Short−Circuit Protection 10 for 100
• Full Latch−Off if Adjustment Pin is Brought High 13 for 133
• Extremely Low No−Load Standby Power
A = Assembly Location
WL, L = Wafer Lot
• Internal Temperature Shutdown YY, Y = Year
• 500 mA Peak Current Capability WW, W = Work Week

• Fixed Frequency Versions at 65 kHz, 100 kHz and 133 kHz

• Direct Optocoupler Connection PIN CONNECTIONS
• Internal Leading Edge Blanking
• SPICE Models Available for TRANsient and AC Analysis Adj 1 8 HV

Typical Applications FB 2 7 NC
• High Power AC/DC Converters for TVs, Set−Top Boxes, etc. CS 3 6 VCC
• Offline Adapters for Notebooks Gnd 4 5 Drv
• Telecom DC−DC Converters
• All Power Supplies (Top View)

ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 15 of this data sheet.

 Semiconductor Components Industries, LLC, 2004 1 Publication Order Number:

March, 2004 − Rev. 1 NCP1217/D
 NCP1217

See Application
Section VOUT
Aux. +
+

NCP1217
Adj HV
1 8
FB
2 7
EMI CS VCC
3 6
FILTER Gnd Drv
4 5

UNIVERSAL
INPUT Ramp Adjustment +

Figure 1. Typical Application Example

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PIN FUNCTION DESCRIPTION
Pin No. Pin Name Function Description
1 Adj Adjust the skipping peak current This pin lets you adjust the level at which the cycle skipping process
takes place. Shorting this pin to ground permanently disables the skip
cycle feature.
By bringing this pin above 3.1 V, you permanently shut off the device.
2 FB Sets the peak current setpoint By connecting an optocoupler to this pin, the peak current setpoint is
adjusted accordingly to the output power demand.

3 CS Current sense input This pin senses the primary current and routes it to the internal
comparator via an L.E.B. By inserting a resistor in series with the pin, you
control the amount of ramp compensation you need.
4 Gnd The IC ground −
5 Drv Driving pulses The driver’s output to an external MOSFET.
6 VCC Supplies the IC This pin is connected to an external bulk capacitor of typically 22 F.
7 NC − This unconnected pin ensures adequate creepage distance.
8 HV Ensures a clean and lossless Connected to the high−voltage rail, this pin injects a constant current into
start−up sequence the VCC capacitor during the start−up sequence.

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 NCP1217

Latch−Off
Comparator
Adj + HV
−
1 8
+ Set HV Current
3.1 V UVLO
− Reset Source
Latch

80 k Skip Cycle
FB 1.1 V Comparator NC
+
2 − UVLO High and Low 7
Internal VCC
24 k

Current Reset
Sense Q Flip−Flop VCC
250 ns 65−100−133 kHz Set DCmax = 74% Q Overload
3 6
L.E.B. Clock Management
Reset
19 k

Ramp
Compensation
20 k 57 k +
−
Ground Drv
VREF
4 + 25 k 1V ±500 mA 5
−

Figure 2. Internal Circuit Architecture

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MAXIMUM RATINGS

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Rating Symbol Value Unit
Power Supply Voltage VCC 16 V
Power Supply Voltage on All Other Pins Except Pin 8 (HV), Pin 6 (VCC) and − −0.3 to 10 V
Pin 5 (Drv)

Maximum Voltage on Pin 8 (HV), Pin 6 (VCC) Decoupled to Ground with 10 F VHV 500 V
Maximum Voltage on Pin 8 (HV), Pin 6 (VCC) Grounded VHV 450 V
Maximum Current into All Pins Except VCC (6) and HV (8) when 10 V ESD − 5.0 mA
Diodes are Activated

Thermal Resistance, Junction−to−Case RθJ−C 57 °C/W

Thermal Resistance, Junction−to−Air, PDIP−7 Version RθJ−A 100 °C/W
Thermal Resistance, Junction−to−Air, SO−8 Version RθJ−A 178
Maximum Junction Temperature TJMAX 150 °C
Temperature Shutdown − 155 °C
Hysteresis in Shutdown − 30 °C
Storage Temperature Range − −60 to +150 °C
ESD Capability, HBM Model (All Pins Except VCC and HV) − 2.0 kV
ESD Capability, Machine Model − 200 V

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 NCP1217

ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = 0°C to +125°C, Max TJ = 150°C,
VCC= 11 V unless otherwise noted.)
Characteristic Pin Symbol Min Typ Max Unit
SUPPLY SECTION (All frequency versions, unless otherwise noted)
Turn−On Threshold Level, VCC Going Up 6 VCCON 11.8 12.8 13.8 V
Minimum Operating Voltage After Turn−On 6 VCCmin 6.9 7.6 8.3 V
VCC Decreasing Level at which the Latch−Off Phase Ends 6 VCClatch − 5.6 − V
Internal IC Consumption, No Output Load on Pin 5, FSW = 65 kHz 6 ICC1 − 960 1110 A
(Note 1)
Internal IC Consumption, No Output Load on Pin 5, FSW = 100 kHz 6 ICC1 − 1020 1180 A
(Note 1)
Internal IC Consumption, No Output Load on Pin 5, FSW = 133 kHz 6 ICC1 − 1060 1200 A
(Note 1)
Internal IC Consumption, 1.0 nF Output Load on Pin 5, 6 ICC2 − 1.7 2.0 mA
FSW = 65 kHz (Note 1)
Internal IC Consumption, 1.0 nF Output Load on Pin 5, 6 ICC2 − 2.1 2.4 mA
FSW = 100 kHz (Note 1)
Internal IC Consumption, 1.0 nF Output Load on Pin 5, 6 ICC2 − 2.4 2.9 mA
FSW = 133 kHz (Note 1)
Internal IC Consumption, Latch−Off Phase, VCC = 6.0 V 6 ICC3 − 230 − A
INTERNAL START−UP CURRENT SOURCE (TJ  0°C)
High−Voltage Current Source, VCC = 10 V 8 IC1 3.5 6.0 7.8 mA
(Note 2)
High−Voltage Current Source, VCC = 0 8 IC2 − 7.0 − mA
DRIVE OUTPUT
Output Voltage Rise−Time @ CL = 1.0 nF, 10−90% of a 12 V 5 Tr − 60 − ns
Output Signal
Output Voltage Fall−Time @ CL = 1.0 nF, 10−90% of a 12 V 5 Tf − 20 − ns
Output Signal
Source Resistance 5 ROH 15 20 35 
Sink Resistance 5 ROL 5.0 10 18 
CURRENT COMPARATOR (Pin 5 Unloaded)
Input Bias Current @ 1.0 V Input Level on Pin 3 3 IIB − 0.02 − A
Maximum Internal Current Setpoint 3 ILimit 0.9 1.0 1.1 V
Default Internal Current Setpoint for Skip Cycle Operation 3 ILskip − 330 − mV
Propagation Delay from Current Detection to Gate OFF State 3 TDEL − 90 150 ns
Leading Edge Blanking Duration 3 TLEB − 250 − ns
INTERNAL OSCILLATOR (VCC = 11 V, Pin 5 Loaded by 1.0 k)
Oscillation Frequency, 65 kHz Version − fOSC 58.5 65 71.5 kHz
Oscillation Frequency, 100 kHz Version − fOSC 90 100 110 kHz
Oscillation Frequency, 133 kHz Version − fOSC 120 133 146 kHz
Maximum Duty−Cycle, NCP1217 − Dmax 69 74 80 %
1. Maximum Value @ TJ = 0°C.
2. Minimum Value @ TJ = 125°C.

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 NCP1217

ELECTRICAL CHARACTERISTICS (continued) (For typical values TJ = 25°C, for min/max values TJ = 0°C to +125°C,
Max TJ = 150°C, VCC= 11 V unless otherwise noted.)
Characteristic Pin Symbol Min Typ Max Unit
FEEDBACK SECTION (VCC = 11 V, Pin 5 Loaded by 1.0 k)
Internal Pull−Up Resistor 2 Rup − 19 − k
Pin 2 (FB) to Internal Current Setpoint Division Ratio − Iratio − 3.3 − −
SKIP CYCLE GENERATION
Default Skip Mode Level 1 Vskip 0.93 1.1 1.26 V
Pin 1 Internal Output Impedance 1 Zout − 27 − kΩ
INTERNAL RAMP COMPENSATION
Internal Ramp Level @ 25°C (Note 3) 3 Vramp 2.6 2.9 3.2 V
Internal Ramp Resistance to CS Pin 3 Rramp − 19 − kΩ
ADJUSTMENT LATCH−OFF LEVEL
Latching Level 1 Vlatch 2.69 3.10 3.42 V
3. A 1.0 M resistor is connected to the ground for the measurement.

TYPICAL CHARACTERISTICS
80 14.0
HV PIN LEAKAGE CURRENT @ 500V (µA)

70
13.5
60
13.0
VCCOFF, (V)

50

40 12.5

30
12.0
20
11.5
10

0 11.0
−25 0 25 50 75 100 125 −25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 3. High Voltage Pin Leakage Current vs. Figure 4. VCCOFF vs. Temperature
Temperature

9.0 1200

1100 100 kHz

133 kHz
8.5
1000
VCCMIN, (V)

ICC1, (µA)

900 65 kHz
8.0
800

700
7.5

600

7.0 500
−25 0 25 50 75 100 125 −25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 5. VCCMIN vs. Temperature Figure 6. ICC1 (@ VCC=11V) vs. Temperature

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 NCP1217

TYPICAL CHARACTERISTICS (continued)

2.80 150

2.60 133 kHz

133 kHz
2.40 130

2.20 100 kHz

FOSC, (kHz)
ICC2, (mA)

110 100 kHz

2.00

1.80 65 kHz 90
1.60
1.40 65 kHz
70
1.20
1.00 50
−25 0 25 50 75 100 125 −25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 7. ICC2 vs. Temperature Figure 8. Switching Frequency vs.

Temperature

5.90 400

5.80
350
5.70
VCClatch, (V)

ICC3, (µA)

5.60 300

5.50
250
5.40

5.30 200
−25 0 25 50 75 100 125 −25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 9. VCClatch vs. Temperature Figure 10. ICC3 vs. Temperature

30 1.10
CURRENT SENSE LIMIT, (V)

25
DRIVER RESISTANCE, ()

1.05
20 Source

15 1.00

10
Sink
0.95
5

0 0.90
−25 0 25 50 75 100 125 −25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 11. Drive Sink and Source Resistance Figure 12. Current Sense Limit vs.
vs. Temperature Temperature

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 NCP1217

TYPICAL CHARACTERISTICS (continued)

1.20 80

78
1.15

DUTY CYCLE, (%)

Vskip, (V)

76
1.10
74

1.05
72

1.00 70
−25 0 25 50 75 100 125 −25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 13. Vskip vs. Temperature Figure 14. Max Duty−Cycle vs. Temperature

3.10 8.0

3.05
7.0
3.00

2.95
Vramp, (V)

6.0
IC1, (mA)

2.90

2.85 5.0

2.80
4.0
2.75

2.70 3.0
−25 0 25 50 75 100 125 −25 0 25 50 75 100 125
TEMPERATURE (°C) TEMPERATURE (°C)

Figure 15. Vramp vs. Temperature Figure 16. High Voltage Current Source
(@ Vcc=10V) vs. Temperature

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 NCP1217

APPLICATION INFORMATION

Introduction reducing magnetics or improve the EMI signature before

The NCP1217 implements a standard current mode reaching the 150 kHz starting point.
architecture where the switch−off event is dictated by the Over Current Protection (OCP): By continuously
peak current setpoint. This component represents the ideal monitoring the Vcc auxiliary winding voltage, NCP1217
candidate where low part−count is the key parameter, enters burst mode as soon as the power supply undergoes an
particularly in low−cost AC/DC adapters, TV power overload: when the Vcc voltage goes down until it crosses
supplies, etc. Due to its high−performance High−Voltage the undervoltage lockout level (Vccmin). When the
technology, the NCP1217 incorporates all the necessary NCP1217 reaches this level (typically 7.6 V), it stops the
components normally needed in UC384X based supplies: switching pulses until the Vcc pin voltage reaches Vcclatch
timing components, feedback devices, low−pass filter and (5.6 V). At Vcclatch, the NCP1217 attempts to restart. As
start−up device but also enhances the original component soon as the default disappears, the power supply resumes
by offering: 1) an externally triggerable latch−off operation.
2) ramp compensation and finally, 3) short−circuit
Over Voltage Protection (OVP): If pin1 is brought to a
protection. Due to its high−voltage current source,
level higher than the internal 3.2 V reference voltage, the
ON Semiconductor’s NCP1217 does not need an external
controller is permanently shut down until the user cycles the
start−up resistance but supplies the start−up current directly
VCC OFF and ON again. This allows the building of efficient
from the high−voltage rail. On the other hand, more and
and low−cost over voltage protection circuits.
more applications are requiring low no−load standby power,
e.g. for AC/DC adapters, VCRs, etc. UC384X series have a Wide Duty−Cycle Operation: Wide mains operation
lot of difficulty to reduce the switching losses at low power requires a large duty−cycle excursion. The NCP1217 can go
levels. NCP1217 elegantly solves this problem by skipping up to 74% typically.
unwanted switching cycles at a user−adjustable power level. Low Standby−Power: If SMPS naturally exhibit a good
By ensuring that skip cycles take place at low peak current, efficiency at nominal load, they begin to be less efficient
the device ensures quiet, noise−free operation: when the output power demand diminishes. By skipping
Current−Mode Operation: As the UC384X series, the unneeded switching cycles, the NCP1217 drastically
NCP1217 features a well−known current mode control reduces the power wasted during light load conditions. In
architecture which provides superior input audio− no−load conditions, the NPC1217 allows the total standby
susceptibility compared to traditional voltage−mode power to easily reach next International Energy Agency
controllers. Primary current pulse−by−pulse checking (IEA) recommendations.
together with a fast over current comparator offers greater No Acoustic Noise While Operating: Instead of skipping
security in the event of a difficult fault condition, e.g. a cycles at high peak currents, the NCP1217 waits until the
saturating transformer. peak current demand falls below a user−adjustable 1/3 of the
Ramp Compensation: By inserting a resistor between the maximum limit. As a result, cycle skipping can take place
current−sense (CS) pin and the actual sense resistor, it without having a singing transformer … You can thus select
becomes possible to inject a given amount of ramp cheap magnetic components free of noise problems.
compensation since the internal saw tooth clock is routed to External MOSFET Connection: By leaving the external
the CS pin. Subharmonic oscillations in Continuous MOSFET external to the IC, you can select avalanche proof
Conduction Mode (CCM) can thus be compensated via a devices, which in certain cases (e.g. low output powers), let
single resistor. you work without an active clamping network. Also, by
Adjustable Skip Cycle Level: By offering the ability to controlling the MOSFET gate signal flow, you have an
tailor the level at which the skip cycle takes place, the option to slow down the device commutation, therefore
designer can make sure that the skip operation only occurs reducing the amount of ElectroMagnetic Interference
at low peak current. This point guarantees a noise−free (EMI).
operation with cheap transformers. Skip cycle offers a SPICE Model: A dedicated model to run transient
proven mean to reduce the standby power in no or light loads cycle−by−cycle simulations is available but also an
situations. averaged version to help you closing the loop. Ready−to−use
Wide Switching−Frequency Offer: Three different options templates can be downloaded in OrCAD’s Pspice and
are available: 65 kHz–100 kHz–133 kHz. Depending on the INTUSOFT’s IsSpice from ON Semiconductor web site,
application, the designer can pick up the right device to help NCP1217 related section.

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 NCP1217

Start−Up Sequence 12.8 V), the current source turns off and no longer wastes
When the power supply is first powered from the mains any power. At this time, the VCC capacitor only supplies the
outlet, the internal current source (typically 7.0 mA) is controller and the auxiliary supply is supposed to take over
biased and charges up the VCC capacitor. When the voltage before VCC collapses below VCCmin. Figure 17 shows the
on this VCC capacitor reaches the VCCON level (typically internal arrangement of this structure.

8 HV

12.8 V/5.6 V +
− 6 mA or 0

CVCC Aux

Figure 17. The Current Source Brings VCC Above 12.8 V and then Turns Off

Once the power supply has started, the VCC shall be level, preventing a bias current to circulate in the
constrained below 16 V, which is the maximum rating on optocoupler LED. As a result, the auxiliary voltage also
pin 6. Figure 18 portrays a typical start−up sequence with a decreases because it also operates in Flyback and thus
VCC regulated at 12.5 V. duplicates the output voltage, providing the leakage
inductance between windings is kept low. To account for this
situation and properly protect the power supply, NCP1217
13.5 hosts a dedicated overload detection circuitry. Once
activated, this circuitry imposes to deliver pulses in a burst
12.8 V REGULATION
12.5 manner with a low duty−cycle. The system auto−recovers
when the fault condition disappears.
During the start−up phase, the peak current is pushed to
11.5
the maximum until the output voltage reaches its target and
the feedback loop takes over. The auxiliary voltage takes
10.5 place after a few switching cycles and self−supplies the IC.
In presence of a short circuit on the output, the auxiliary
voltage will go down until it crosses the undervoltage
9.5
lockout level of typically 7.6 V. When this happens,
3.00 M 8.00 M 13.0 M 18.0 M 23.0 M NCP1217 immediately stops the switching pulses and
t, TIME (sec) unbiases all unnecessary logical blocks. The overall
consumption drops, while keeping the gate grounded, and
Figure 18. A Typical Start−Up Sequence for
the VCC slowly falls down. As soon as VCC reaches typically
the NCP1217
5.6 V, the start−up source turns−on again and a new start−up
sequence occurs, bringing VCC toward 12.8 V as an attempt
Overload Operation
to restart. If the default has gone, then the power supply
In applications where the output current is purposely not
normally restarts. If not, a new protective burst is initiated,
controlled (e.g. wall adapters delivering raw DC level), it is
shielding the SMPS from any runaway. Figure 19 portrays
interesting to implement a true short−circuit protection. A
the typical operating signals in short circuit.
short−circuit actually forces the output voltage to be at a low

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 NCP1217

VCCON = 12.8 V
VCCmin = 7.6 V
VCC

VCClatch = 5.6 V

DRIVING PULSES

Figure 19. Typical Waveforms in Short Circuit Conditions

Calculating the VCC Capacitor The theoretical power transfer is therefore:

The VCC capacitor can be calculated knowing the IC 1 · Lp · Ip2 · Fsw  4.1 W. If this IC enters skip cycle
consumption as soon as VCC reaches 12.8 V. Suppose that a 2
NCP1217P065 is used and drives a MOSFET with a 30 nC mode with a bunch length of 10 ms over a recurrent
total gate charge (Qg). The total average current is thus period of 100 ms, then the total power transfer is:
made of ICC1 (750 A) plus the driver current, 4.1 * 0.1  410 mW.
Fsw * Qg  1.95 mA. The total current is therefore 2.7 mA. To better understand how this skip cycle mode takes place,
The V available to fully start−up the circuit (e.g. never a look at the operation mode versus the FB level
reach the 8.2 V VCCmin during power on) is immediately gives the necessary insight.
13.7−8.2  5.5 V best case or 4.9 V worse case (11.9−7.0) .
FB
We have a capacitor that then needs to supply the NCP1217
with 2.7 mA during a given time until the auxiliary supply 4.2 V, FB Pin Open
takes over. Suppose that this time was measured at around 3.2 V, Upper
15 ms. CVCC is calculated using the equation C  t · i or
NORMAL CURRENT Dynamic Range
V MODE OPERATION
C  8.3 F. Select a 22 F/25 V and this will fit.

Skipping Cycle Mode 1V

SKIP CYCLE OPERATION
The NCP1217 automatically skips switching cycles when IP(min) = 333 mV/RSENSE
the output power demand drops below a given level. This is Time
accomplished by monitoring the FB pin. In normal Figure 20.
operation, pin 2 imposes a peak current accordingly to the
load value. If the load demand decreases, the internal loop When FB is above the skip cycle threshold (1.0 V by
asks for less peak current. When this setpoint reaches a default), the peak current cannot exceed 1.0 V/Rsense.
determined level (Vpin 1), the IC prevents the current from When the IC enters the skip cycle mode, the peak current
decreasing further down and starts to blank the output cannot go below Vpin1/3.3. The user still has the flexibility
pulses: the IC enters the so−called skip cycle mode, also to alter this 1.0 V by either shunting pin 1 to ground through
named controlled burst operation. The power transfer now a resistor or raising it through a resistor up to the desired
depends upon the width of the pulse bunches (Figure 21). level. In this later case, care must be taken to keep sufficient
Suppose we have the following component values: margin between this pin 1 adjustment level and the latch−off
Lp, primary inductance = 350 H level. Grounding pin 1 permanently invalidates the skip
Fsw, switching frequency = 65 kHz cycle operation.
Ip skip = 600 mA (or 333 mV/Rsense)

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 NCP1217

Power P1

Power P2

Power P3

Figure 21. Output Pulses at Various Power Levels (X = 5.0
s/div) P1
P2
P3

MAX PEAK
300 M CURRENT

200 M SKIP CYCLE

CURRENT LIMIT

100 M

315.40 U 882.70 U 1.450 M 2.017 M 2.585 M

Figure 22. The Skip Cycle Takes Place at Low Peak Currents which Guarantees Noise−Free Operation

Sufficient margin shall be kept between normal pin1 level and the latch−off point in order to avoid false triggering.

Ramp Compensation Continuous Conduction Mode (CCM) with a duty−cycle

Ramp compensation is a known mean to cure greater than 50%. To lower the current loop gain, one usually
subharmonic oscillations. These oscillations take place at injects between 50 and 100% of the inductor down−slope.
half the switching frequency and occur only during Figure 23 depicts how internally the ramp is generated.

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 NCP1217

Duty Cycle Typ = 74% Latching Off the NCP1217

2.9 V Total latched shutdown can easily be implemented
through a simple PNP bipolar transistor as depicted by
0V
Figure 24. When OFF, Q1 is transparent to the operation.
When forward biased, the transistor pulls the ADJ pin
19 k toward VCC and permanently latches−off the IC as soon Vadj
Rcomp goes above the latching level (typical 3.1 V). Figure 24
+ L.E.B. shows how to wire the bipolar transistor to activate the
− CS
latch−off. A typical candidate for Q1 could be an
Rsense MMBT3906 from ON Semiconductor.

From VCC
Setpoint

Figure 23. Inserting a Resistor in Series with the Current

Sense Information Brings Ramp Compensation
Off Q1
In the NCP1217, the ramp features a swing of 2.9 V with
a duty cycle max at 74%. Over a 65 kHz frequency, for
instance, it corresponds to a 254 mV/s ramp. In our Rlimit
FLYBACK design, let’s suppose that our primary
inductance Lp is 350 H, delivering 12 V with a Np:Ns ratio 1 8
of 1:0.1. The OFF time primary current slope is thus given 2 7
Np
(Vout
Vf) · Ns 3 6
by:  371 mAs or 37 mVs when
Lp 4 5 CVCC
projected over an Rsense of 0.1 , for instance. If we select
75% of the downslope as the required amount of ramp
compensation, then we shall inject 27 mV/s. Our
internal compensation being of 254 mV/s, the divider
ratio (divratio) between Rcomp and the 19 k is 0.106. Figure 24. A Simple Bipolar Transistor Totally
A few lines of algebra to determine Rcomp: Disables the IC
19 k · divratio  2.26 k.
(1−divratio)

VCC
The start−up current source keeps the
device latched until reset occurs.
VCCON = 12.8 V

VCCmin = 7.6 V
VCCLATCH = 5.6 V
Reset level
Time
Drv

Driver
Pulses Latched−off
Time
Adj

Default
adj level
Time
Fault brings adj above latching level

Figure 25. When Vadj is Pulled Above 3.1 V, NCP1217 Permanently Latches−Off the Output Pulses

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 NCP1217

In normal operation, the Adj pin level is kept at a fixed output pulses are disabled as long as FB is pulled below
level, the default one or lower. As soon as some external pin 1. As soon as FB is relaxed, the IC resumes its operation.
signal pulls this Adj pin level above 3.1 V typical, the output Figure 27 depicts the application example.
pulses are permanently disabled. Care must be taken to limit
the injected current into pin 1 to less than 2.0 mA, e.g.
through a series resistor of 5.6 k with a 10 V VCC. The 1 8
start−up switch is activated every time VCC reaches 5.6 V 2 7
and maintains a VCC voltage ramping up and down between 3 6
5.6 V and 12.8 V. Reset occurs when VCC falls below 5.6 V, ON/OFF Q1 4 5
e.g. when the user cycle the SMPS down. Figure 26
illustrates the operation. Adding a zener diode from Q1 base
to ground makes a cheap OVP, protecting the supply from
any lethal open−loop operation. If a thermistor (NTC) is
added in parallel with the zener−diode, overtemperature Figure 27. Another Way of Shutting Down the IC
protection is also ensured. Without a Definitive Latch−Off State

Vaux
Protecting the Controller Against Negative Spikes
As with any controller built upon a CMOS technology, it
is the designer’s duty to avoid the presence of negative
spikes on sensitive pins. Negative signals have the bad habit
to forward bias the controller substrate and induce erratic
behaviors. Sometimes, the injection can be so strong that
1 8 internal parasitic SCRs are triggered, engendering
OVP 2 7 16 V irremediable damages to the IC if a low impedance path is
T
offered between VCC and GND. If the current sense pin is
3 6
often the seat of such spurious signals, the high−voltage pin
4 5 Laux can also be the source of problems in certain circumstances.
CVCC
During the turn−off sequence, e.g. when the user unplugs the
power supply, the controller is still fed by its VCC capacitor
and keeps activating the MOSFET ON and OFF with a peak
current limited by Rsense. Unfortunately, if the quality
Figure 26. A Thermistor and a Zener Diode Offer coefficient Q of the resonating network formed by Lp and
Both OVP and Overtemperature Latched−Off Cbulk is low (e.g. the MOSFET Rdson + Rsense are small),
Protection
conditions are met to make the circuit resonate and thus
negatively bias the controller. Since we are talking about ms
Non−Latching Shutdown
pulses, the amount of injected charge (Q = I * t) immediately
In some cases, it might be desirable to shut off the part latches the controller that brutally discharges its VCC
temporarily and authorize its restart once the default has capacitor. If this VCC capacitor is of sufficient value, its
disappeared. This option can easily be accomplished stored energy damages the controller. Figure 28 depicts a
through a single NPN bipolar transistor wired between FB typical negative shot occurring on the HV pin where the
and ground. By pulling FB below the Adj pin 1 level, the brutal VCC discharge testifies for latch−up.

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 NCP1217

Vcc 5 V/DIV
Vlatch 1 V/DIV
Time 10 ms/DIV

Figure 28. A Negative Spike Takes Place on the Bulk Capacitor at the Switch−Off Sequence

Simple and inexpensive cures exist to prevent from Another option (Figure 30) consists in wiring a diode
internal parasitic SCR activation. One of them consists in from VCC to the bulk capacitor to force VCC to reach
inserting a resistor in series with the high−voltage pin to VCCON sooner and thus stops the switching activity before
keep the negative current to the lowest when the bulk the bulk capacitor gets deeply discharged. For security
becomes negative (Figure 29). Please note that the negative reasons, two diodes can be connected in series.
spike is clamped to (−2*Vf) thanks to the diode bridge. Also,
the power dissipation of this resistor is extremely small since
it only heats up during the startup sequence.

Rbulk
4.7 k

+ 1 8 2 + 1 8 3
Cbulk Cbulk D3
2 7 2 7 1N4007
3 6 1 3 6 1
+ 4 5 +
4 5
CVCC CVCC

Figure 29. A simple resistor in series avoids any Figure 30. . . . or one diode forces VCC to reach
latch−up in the controller . . . VCCON sooner.

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 NCP1217

ORDERING INFORMATION
Device Version Marking Package Shipping
NCP1217P065 65 kHz P1217P065 PDIP−7 50 Units/Rail
NCP1217D065 65 kHz 17D06 SO−8 2500 Units/Reel
NCP1217P100 100 kHz P1217P100 PDIP−7 50 Units/Rail
NCP1217D100 100 kHz 17D10 SO−8 2500 Units/Reel
NCP1217P133 133 kHz P1217P133 PDIP−7 50 Units/Rail
NCP1217D133 133 kHz 17D13 SO−8 2500 Units/Reel

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 NCP1217

PACKAGE DIMENSIONS

SO−8
D SUFFIX
CASE 751−07
ISSUE AA

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
−X− Y14.5M, 1982.
A 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
8 5 SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
1 EXCESS OF THE D DIMENSION AT MAXIMUM
4 MATERIAL CONDITION.
−Y− K 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.

G MILLIMETERS INCHES
DIM MIN MAX MIN MAX
C N X 45
A 4.80 5.00 0.189 0.197
B 3.80 4.00 0.150 0.157
SEATING
PLANE C 1.35 1.75 0.053 0.069
−Z− D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
0.10 (0.004) H 0.10 0.25 0.004 0.010
H M J J 0.19 0.25 0.007 0.010
D K 0.40 1.27 0.016 0.050
M 0
8
0
8

N 0.25 0.50 0.010 0.020
0.25 (0.010) M Z Y S X S
S 5.80 6.20 0.228 0.244

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 NCP1217

PACKAGE DIMENSIONS

PDIP−7
P SUFFIX
CASE 626B−01
ISSUE A

NOTES:
1. DIMENSIONS AND TOLERANCING PER
J ASME Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETERS.
3. DIMENSION L TO CENTER OF LEAD
8 5 WHEN FORMED PARALLEL.
M 4. PACKAGE CONTOUR OPTIONAL
(ROUND OR SQUARE CORNERS).
B 5. DIMENSIONS A AND B ARE DATUMS.
L
1 4 MILLIMETERS
DIM MIN MAX
A 9.40 10.16
B 6.10 6.60
F C 3.94 4.45
D 0.38 0.51
NOTE 2 A F 1.02 1.78
G 2.54 BSC
H 0.76 1.27
J 0.20 0.30
K 2.92 3.43
C L 7.62 BSC
M −−− 10 °
N 0.76 1.01
−T−
SEATING N
PLANE
H D K
G
0.13 (0.005) M T A M B M

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 NCP1217

The product described herein (NCP1217), may be covered by the following U.S. patents: 6,271,735, 6,362,067, 6,385,060, 6,429,709, 6,587,357. There may
be other patents pending.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: [Link]
Literature Distribution Center for ON Semiconductor USA/Canada
P.O. Box 5163, Denver, Colorado 80217 USA Order Literature: [Link]
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada 2−9−1 Kamimeguro, Meguro−ku, Tokyo, Japan 153−0051 For additional information, please contact your
Email: orderlit@[Link] Phone: 81−3−5773−3850 local Sales Representative.

[Link] NCP1217/D
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