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Upcode Microprocessor

The document provides an extensive overview of the instruction set for the 8051 microcontroller, detailing various operations including arithmetic, logical, data transfer, and program branching instructions. It includes mnemonics, descriptions, and byte sizes for each instruction, along with information on how they interact with registers and memory. Additionally, it outlines the effects of specific operations on flag settings and provides a hexadecimal opcode table for reference.
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0% found this document useful (0 votes)
8 views12 pages

Upcode Microprocessor

The document provides an extensive overview of the instruction set for the 8051 microcontroller, detailing various operations including arithmetic, logical, data transfer, and program branching instructions. It includes mnemonics, descriptions, and byte sizes for each instruction, along with information on how they interact with registers and memory. Additionally, it outlines the effects of specific operations on flag settings and provides a hexadecimal opcode table for reference.
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF or read online on Scribd
“51 INSTRUCT; Teble 10081 ION SET Instruction Set g Tnerrpt Response Time: Refer summary scription Chapter. (0 Hardware De. ‘i Instructions that Affect Fiag Settingatt) an Memonie Description veitator Insrucion Fag Intron [:RE ETC orenamng “re © Ovi ac Mietlon | Bag AN Ren ADD x xX X circ ~, A ‘Accumulator 1 2 aoc X XX oHG | y PP Adrost ndddiecoroty ‘suBB ANLC bit Xx ADD mutator mu 8X anew x Nem ilndecitan 4, ov ORLCbit x ADD As, ec acuudet DA x ORLCbit x. ‘dat, Ad inmoata 2 2 fc x MovCRit x ‘tlt RUC CUNE x ADOC ARN Add regi itor to ere coer ote that operations on SER byte address 208 o with Cony Bit addres 209-215 (ie, the PSWer bts in he | |*7PS Adhoct Aaddrstbyoto 2 PSW) will also affect flag settings. ‘Accumulator with Cary Note on instruction set and addressing modes: ADOC AGRI Addindrect 1 Rn — Register R7-RO of the currently e- vce reenact eo direct — S+it internal data location's addres. | |ao00 Aedata ™ Sa a on ats Mew tetas 2g location (0-127) or a SR fie, VO with Cary port control register, status register, | |SUBB_ARn Subtecthogter 1 etc. (128-255)]. toa e @Ri — 8-bit internal data RAM location O- borrow: 255) addressed indirectly through reg- | [SUBS Adkect Suovactdrect 2p ister R1 or RO. byte from Ace #data__— 8-bit constant included in instruction. with borrow #data 16 — 16-bit constant included in instruction. SUBB A@RI — Subtractindiroct 1 12 addr 16 — 16-bit destination address. Used by RAM from ACC LCALL & LIMP. A branch can be with borrow anywhere within the 64K-byte Pro- SUBB A,#data Subtract 2 2 gram Memory address space. immediate data addr 11 — 11-bit destination address. Used by from Acc with ACALL & AJMP. The branch will be borrow within the same 2K-byte page of pro-| [INCA Increment 48 gram memory as the first byte of the Accumulator following instruction. INC An Incromentregister_ 112 rel — Signed (two's complement) 8-bit offset INC direct Incrementdirect. «2 12 byte. Used by SIMP and all condition- byte he al jumps. Range is. —128 to +127 INC @Ri Intent" bytes relative to first byte of the fol- Ceeeael 1 2 : owing instruction. peo A yensialiie bit — Direct Addressed bit in Internal Data Deleon 1 12 L RAM or Special Function Register. DEC Rn Gece DEC direct Decrement direct 2 2 vec eR bomomet 1 indirect RAM 0 ‘Al mnemonics copyrighted ©Intel Corporation 198 2-21 : ND INS InESs- int: mes®-51 pROGRAMMER'S GUIDE A intel. tinued) sot summary (Cor Oveitator| ‘rabje 10,0081 Intructlon s,_beveripton —_BY'® “period one Oneaor nemo ee Mnemonic __Deverpton _DY'? Pete} |roaicaLorenarions Comme 1 SaaTAMERCOPERATIONS Coninved |g ALA frecurutator Lott ATA incrmantOata otato 4 Fonte ” ric A coumuator Lett aut £8 Mampyase 1 na DIV AB DidonbyB | a + eA) ta eee pecumsator LOGICAL OPERATIONS. Fight ; ARC Afin ANDRegiserto t 12 Fotate 1 2 ‘Accumulator re ‘Accumulator lant. Adrect —ANDGrectbyto «212 Fight trough to Accuruiator the cary 1 lane A@Ri —ANDindect «112 ie Swapnibbles 1 2 RAM to jswar win the AN Acounuiter at ‘accumulator data. ANDInmedato 2 i neers DATATRANSFER atone. ‘Accumulator Mov ARN JANL directa AND Accumulator 2 12 register to cae ‘accumulator JANL diroct,#data ANDimmediato 924 Mov Adrect — Movedirect goer ee datato direct byte byteto JORL AR ORregisterto 112 ‘Accumulator ‘Accumulator MOV A@Ri — Movaindrect «= 112 ORL Adroct Oftdrectbyeto 212 RAM to ‘Accumulator ‘Accumulator ORL AeA —ORRindvect RAM 412 MOV Asdata Move 2 2 to Accumulator immediate JORL A¢data —ORimmedate, © 212 ata to aa ‘Accumulator \coumlator eo ont cect Ontrcamuner 2 tz | A Nutr | todrect byte i ORL. cect weal toresister dincvaea ORinmadlo 924 MOV Rndirect — Movedirect, 2 24 XAL An ExcusveOR 112 ne register to register ‘Accumulator MOV Rn,edata Move els ae XL Adrect ExclusveOR 242 eae direct byte to toregister ‘Accumulator MOY. recA Move 2 2 XRL_ A@Ri Exclusive-OR 1 12 ‘Accumulator indirect RAM to to direct byte Accumulator MOV directn Move register st 2 26 Atdata — Exclusive-OR 2 12 Mov to direct byte immediate data to [Link] Move direct 3 24 : ‘Accumulator byte to direct RL direct Exctusive-OR 2 12 MOV [Link] Move indirect 2 24 ‘Accumulator to RAM to direct byte MOV direct, #data Move aeeag immediate data to direct byte MOV eRiA Move pt Accumulator to indirect RAM Al can ll mnemonics copyrighted ©ntel Corporation 1860 2-22 mcse- ‘51 PROGRAMMER’S GUIDE AND INSTRUCTION SET ‘Summary (Continued) Mnemonic Description Byte % IGATATRANSFER (Continues) PAA TeRidroct — [Link] byteto Indirect RAM asta Move jwov @Fecaiemeciato ata to indirect RAM DpTR,#dataté Load Data wow Pointor witha 16-bit constant Iyovs A@A+OPTR Move Code byte relative to DPTR to Aco ove ACAFPC Move Code byte relative to PCto Aco Nov Aer Move External RAM (6it add to Ace ovK A@DPTA Move External RAM (16-bit addr to Ace Move Acc to External RAM (e-bit ade) Move Acs to External RAM (1e-bitader) PUSH direct Push direct byte onto stack POP. direct Pop direct byte from stack cH An Exchange register with ‘Accumulator KoH Adirect Exchange direct byte with ‘Accumulator CH ARI Exchange indirect RAM with ‘Accumulator Exchange low- ordor Digit indiroct RAM IMOVX @RiA IMOVX @DPTRA CHO Aer ____winace 2 24 26 24 24 24 24 24 24 2 2 12 12 Mnemonic Deseription _yte sllator| ‘BOOLEAN VARIABLE MANIPULATION CLR Cloae Carry 1 2 CLR bit Cloarciroctbit, «2 ta SET CG — SotCarry 1 2 SETB bit Sot droct bit 2 GLC Complement 1+ 42 ty CPL bit Complement 2 2 diroctbit ANL Chit ANDdirctbit = 22 toCARAY ANL —Gybit ANDomplement 2 24 of drect bit toCarry OAL Git ORdrectbit 2 2 toCarry ORL Gb ORcomplement 224 of drect bit toCany MOV Chit Movedrectbit = 212 toCarry MOV bit MoveCaryto = 224 droct bit JC rel Jumpit Carry 2 28 inset UNG rol Jumpit Carry 2 A rot set JB bitrel— Jumpif direct 3 Bitis set NB bityel_— Jumpif direct 3 8 Bitis Not set JBC bitrel_ Jumpit direct 3 2 Bitis set & clear bit PROGRAM BRANCHING ACALL addr1t Absolute 2 2 ‘Subroutine Cal LCALL addrt6 Long 3 Subroutine Call RET Rotur from 1 2 ‘Subroutine RETI Return from, 1 a4 interrupt AMP addrit Absolute: 2 24 Jump LIMP addr16_ Long Jump 8 reading SUMP rel Short Jump 7 (lative add) ‘Aimomonios copyrighted ©rntel Corporation 1980 MCS®.51 PROGRAMMER'S GUIDE AND INSTRUCTION SET Table 10. 8051 Instruction Set Summary (Continued) Osciatr| | fascahaas, Descraton Byte Ovelator Mnemonic Description Byte Opcliato PROGRAM BRANCHING (Continued) PROGRAM BRANGHING (Continued) MP @A+DPTR Jump indirect 1 24 CJNE Rin,#data,rel Compare: 3 24 relative tothe immediate to pate register and 2 i ep aaDT ae lo Jump it Not Accumulator Equal isZero CJNE @Ri,#data,rel Compare 3 24 NZ ro sJumpit 2 ae immodiate to ‘Accumulator indirect and is Not Zero Jump if Not CINE Adirect,rei Compare 3 24 Equal direct bye to DINZ. Rinse! Decrement 2a Acc and Jump register and itNot Equal Jump if Not CINE A, #data,rel Compare 3 24 Zero immediate to DINZ directrel Decrement «3g ‘Ace and Jump direct byte HH Not Equal and Jump i Not Zero NOP No Operation 4 12 ‘All mnemonics copyrighted ©Intel Corporation 1880 y ie McS®-51 PROGRAMMER'S GUIDE AND INSTRUCTION SET ‘Table 11. Instruction Opcodes In Hoxadecimal Order ber aR Mex Number Ses Mrnmone ‘Operand co Mnomonie__operanae | & 1 NOP Fy Fue 2 AIMP code ade 34 ‘Aooc ot 3 Lp code ade 35 ‘A000 s 1. BR a 38 x000 7 + INC a 37 ‘aDoc rn - spe & $ ING eno 39 ‘Doc ARI 7 + ING ent aA ADDG = AR2 oi + ING Fo 38 DDC ARO . + ING Ri 30 ‘aD0C ARS 7 + ING Re 20 ‘a00C ARS 7 + WNC RS 3E ‘ADC ARS 2 + ING Re oF ‘aD0C ART x 1 INC RS 40 wc code ads ro + INC Re “a ‘AMP code addr - + INC R7 42 ‘on data ade.A q 3 BC bit, code adr 43 ont, data addr, # data 7 2 ACALL © codeadar “4 ont Aedata o 3 LCALL. «code adr 45 onL ‘Agata addr 8 4 RRC A 6 ont Kero " + DEC A a ont AeRt s 2 (DEC data addr 8 OAL ARO 8 + DEC ero 4 ont, ARI ” + DEC ert 4A ont AR2 8 1 DEC FO 48 onL ARS 9 + DEC Rt 4c ont. ARS A + DEC Re 40 ORL ARS B 1 DEC RS 4E ORL ARE 1c + DEC Re ae ORL ART 10 + DEC RS 50 Nc code addr» 1€ + DEC Re st ACALL code acd F 1 DEC R7 52 ANL dataaddcA 2 a B bit addr, code ada 53 ANL data addr, # data a 2 AINP code adr 54 AN Asdata 2 + RET 55 ANL ‘Reata addr 2B + RL A 56 ANE R@RO 2 2 ADD Asdata 57 ANL eR 2B 2 ADD Adata add 58 ANE ‘ARO 2 + ADD ‘A@RO 59 ANC, ARI a 1 ADD AeRt 5A ANL ARQ 2 1 ADD ‘ARO 5B ANL ARS 2 + ADD ARI 5c ANL, ARG a 1 ADD AR2 5D ANL ARS 2B 1 ADD ARS 8E ANL AR x 1 ADD ARS SF ANL ART 2 1 ADD ARS 60 wz code addr = 1 ADD ARG 61 ‘AJMP code addr ” + ADD ART 62 XAL data addrA. a 3 NB bit addr, code addr 63 XAL data addr, # data ts 2 ACALL ~— code addr 64 XRL Addata 1 RET 65 XAL ‘Adata addr 2-25 MCS®.51 PROGRAMMERS GUIDE AND INSTRUCTION SET Table 11. Instruction Opcodes In Hexadecimal Order (Continued) 7 Hex Number tanemonic Operands. ME nemonle Operands Code _ofbytes_™ = et AeRo Wacentge popeaue ae 1 ome RS 4° See ane eA 69 1 XxRL ARI 9c 1 ae ven eo ame a © 4 : et Om Re % =f 8uBBARS a 5 ‘SUBB ART se of om | OAR oF OR ow. AR a0 2 ORL” ade ee 1 XxRL ARG AL 2 AJMP code addr oe oe Ae n2 2) MOV. tac 7 2 wuz code adr 43 1 ING ere nt 2 ACL aeaceh M4 MLB 72 2 ORL Cibit addr AS rasarved % ASMP.” Sacer 28° 2 MOV eROdeta ade 4 2 ‘MOV A,#data AT 2 MOV @[Link] addr 75 3 Mov data addr, #data AB 2 MoV ‘[Link] addr 76 2 MOV @RO, #data Aa 2 MOV [Link] addr Fao uo acerca aA 2 MOV Raat ae * 2 “wey Row a8 2 MOV Radata aoe ~ 25 Mov "Ree aC 2 MOV Raata ace 7A. <2 yay. + < Baia aD 2 MOV guata aaah 7 2° Mov Raat AB BS Movs. Aeaaaeae 702K Mov“ — esa AF 2 Mov aata cat i 2 ao me BO 2 ANL C/bit addr (at 8 0 add 2 RM sea ae Se code a oe as eae 38 ane Aiea 7 owe Sitka 3 ne Seat actcode a .# [Link] ace fe : ion iaaae eee 87 3 CJNE @R1, # data,code addr oy «Savas ct wig. SNE Aiedtacote na @ 2 mov data adr ent BA 3 GINE Re. édataccode auth e . iw o ser oe 3 CJNE RS, # data,code addr 8A 2 MOV data addr,A2 BD 3 one Recon fr 2 FNL dames 3 GINE RG ,adatacode at f REGUS! ONES. Repeat aeate ec 2 Mov Gata acre code te a RS ONE. rece addes co Pek pune Gala aE 2 Mov aeaauarne 2 urn" aaaaaere AMP xen 8 oy pa? @ of ga: fede 1 2 ACALL code addr C4 tes oa i 2 2 omg aia Sb. sas A re | 2 os F red A#data, c7 4. XCH A@RI = 2 ce 1 xcH Ro of ee a ee 4 i 2 CA SoH Ane Bt cn ARs 2.26 MCS®-51 PROGRAMMER’S GUIDE AND INSTRUCTION SET Table 11. Instruction Opcodes In Hexadecimal Order_ (Continued) Number ez amber aemonte__Operende ex Hamber numeric Operands | oC 1 XCH ARS £6 1 MOV ‘A@RO co 1 XCH ARS &7 1 Mov AGRI ce 1 XCH ARG £8 1 MoV ARO oF 1 XCH ART es 1 Mov ARI Do 2 POP data addr EA 1 Mov AR2 pt 2 ACALL ~— code addr 8 1 Mov ‘ARS be 2 SETB bit addr EC 1 Mov ARG 03 + SETB c ED 1 Mov ARS De 1 DA A EE 1 MoV ARG D5 3 DUNZ data addr,code addr EF 1 MOV ART Ds + XCHD AeRO FO 1 Movx @DPTRA 7 4 XCHD A@Rt FA 2 ACALL code addr oe 2 DUNZ. _-RO,code addr F2 1 Movx @ROA De 2 DJNZ Ri,code addr F3 1 MOVx @RLA DA 2 DUNZ R2,code addr Fa 1 CPL A pa 2 DUNZ F3,code add F5 2 Mov data addrA pc 2 DUNZ Ré,code addr F6 1 MoV eROA Do 2 -DINZ 5,code addr F7 1 Mov @RtA DE 2 DUNZ R6,code addr Fe 1 Mov ROA DF 2 -DINZ R7,code addr Fo 1 MoV RLA £0 1 MOVX A@DPTR FA 1 Mov RA a 2 AJMP code addr FB 1 Mov RBA 2 + MOVX A@RO FC 1 Mov AA 53 4 MOVX A@Rt FD 1 Mov RSA Es 1 GR A FE 1 Mov RGA 5 2 MOV Adata addr FF. 1 Mov. RA Instruction Set Summary AIMEL 7 G ~ . 2 Nz . Hi ic z " ° NOP 06 0 re a a 2 6 tre moe | ome | emzr | nz | ranzecr | worry wezc | a20) | (98,20) - CALL AMP CALL 1 MP ACALL IMP HEAL ni (2) (Pa) 8 2 ‘on ‘ro e) ey eazy | 5.201 | (28,20) | (26,20) were | wor) | poe | e620) s ‘OAL = ORL NL Es Cit z wwe] cea RET a ora dea ane c ORL ant ae oF a RR RC AL v¥ dir, tata | oir, tata ir, #data_ | @A+DPTA 7 7 (38,20) | (08,20) | (38,20 feo} xAL Mov 4 ine DEC ‘ADD ‘ADDC ORL, At ‘data a * Ata Avtoata | A tdata | A, adata “per | ‘ca (2) (28) (8) (26) oy 3 wwe DEC 1c ont ANE a “ ar ar ner ‘ner Ar Age fo | een ay 25) (3) 8) 8} 23} te Se.2e1 6 NC DEC ‘x00 ‘ADOC ont. os RL ne ero oe [sem] wer | scene | Ay | 2B FO, @data [ ay, 7 ine Eo 00 ‘ADOC ont NL xAL Mov on ent Kent fomem | nem | am | 2B, @R!, reata ae Ee | (23) 8 we DES 200 A006 ORL ANE xAL Mov Ro ARO ARO ARO ARO APO | Ro,sdota fal (ea Tees | 3 Ne ves 0 p06 ont aN xAL Mov Rt ARI AR ARt ARI Rt, fata a Ne DES 200 7 mo Pc = A006 on "AN xRL Mov . ARe ARO Ane AR2 | peedata 0 ee ap ‘x00 ope OAL we be NL RL Mov ARS ARS ARG ARS . ARS | pssedata c WN pec | op ‘006 ont ‘aN le Ra Ra Ane ARE ARE R cn wo Are ARG | Re tdata > We bee Age] jog | tes) 7 000 ‘onL NL ; 6 ARS ARS a XAL Mov . ARS ApS | re. edata e NC DEC “aboe | og 7 ‘ADD A000 [a | ——— 6 re ORL AN AR ARE Ane ae Kes Mov | : : 76 Te pet aoa "7 Rr ‘000 nL AN AR? aR pa xRL Mov Le | : AR? AR? | pp data : ae 8) ie zom anon | tes BO = 2 Cyee, 4c) 24 6 ete Blank = 1 byte cyelg 2-72 - ues Instruction Set ‘ tion Set Summary (Continued) ers 7 7 wor Jone 7 | Se onmme Gt a, | Goes | nse 8. faees_| [jar Pea + | feo a) es) eta | emer | poz | +" Por [Now os oo (3) wwe ortn tac) wut swe |x can | or ae A A A a ue) yor ene | ner | now | Gite | Rae | aca to) | ese |e a wow yor | xc [Nov | Mov eno, RGto | Xeno | sero | oro, reel sues | Nov yon | xen | wor [wow 2 | tee | omicnmins | xem | Aom | sent | Ont poze | waect sues] nov cane xen pn | wo | Mow sus] MO | moran | Amo | poet | ARO | ROA 8.20) (28,26) (28,201 sues | Nov une yn) oz | wo | OW ge | | yeas | Amt | tm) | ARH | RUA (28, 20) (3B, 20) (28, 2c) sue | Nov oun yor} nz | wo | gue | MOL | pan | Ame | feel | Ame | REA (2B, 20) {98, 2C] (28, 2¢) sues | mov cane son} owe | wor | MOV gue | MO | panaamet | ARS | nal | ARO | POA (28,201 (38,20) B20) sues | (NOV cone XxGH pinz | wov wor wor f sue] AS | ass | AE | Re, | APE | MA (28,20) (28, 20} (28, 20) . ‘MOV ‘SUBB MOV xCH DUNZ ‘mov MOV curs | Ans | RS Re | pe | wns | ASA $28, 20) (2B, 2c) (28, 20) . Mov suBe MOV XCH DUNZ MOV MOV di, AB ARE 6, dir ARE 6, rel ARE REA 8,20) (28, 2C) (28, 20) ‘ wor ‘SUBB MOV CINE XCH DUNZ ‘MOV a a ART 7, dir 7, Adata, rol ART 7, rol ART Rr {22,20} (2B, 2C) {38, 2C) (2B, 20] PACKAGING intel. PACKAGE TYPES momma pais CERAMIC PACKAGES ‘Surface Mount COFP at ee Flatpack) — Loa (Land Grid Array) Socket Mount L_ pea (Pin Grid Array) Gottom View) cpr (Ceramic Dual Insertion /Socket Mount ee ntsc Faagy ee 240817-1 13 (Reprinted by permis {ston of Intel Corporation, COPYE Intel Corp, 1992) st oh 3 TL180F | exist Muy Lybt : ts yovaivn Lompoc pedieig pend) eS 2 oper aur af) “Moy Pend) Eo’ ais Cmpoyy Kowayy ‘ssoqpea'] 9ur]-Uy jus) WAIS ‘qunoyg 258350) (pedpend anwex93) avnouwi cs (eae dp popes ansea) “ S01 (mopur, An Sumy uoRasuy) (@8eyoeg aura reng ae:93) acs ma (68epea sumo pews us) S¥OV2DVa GITVAS-SSV1D pe) coun LOS (peat) (@8ey2eq auTpAO yeuIs) Qunoyy aoezing) 301 fos = Buytn) @8ey>eg auTpNg WeuIg) == fea, (bonunues) SAdAL BOWNOWE (penunves) S3dAL IOVNOVE 5 = a nom /E en eee ae or TZ180KE (o8eypeg aurT-ur jena Auurys) did ANNIXS S-z180%7 Sam (oSepeq ourruy tena ras) did 3NTIHS Aowea sopeuveg: a (e8e peg aurT-uy Tend Hse) aad THdAL ens sam (efeoea ourr-u1 Sez81z) az semews09) unoyy wopeeuT- | aa W34ALGNY | 34AL—GUYO Od VIOWSd onIDyyOVd (penunues) SadAL SOVHOVE (Penunuec) SAdAL FOVHOVd “1Pyuy ONIDVHOVE “ayy -APPENDI

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